diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
| commit | 57e5401d954d46fea45ca3eaafa8ae655659da39 (patch) | |
| tree | 7108ae4d529338b13daa49308c85bb7a680f7b58 /tests/quick/se/00.hello/ref/mips | |
| parent | aa329f4757639820f921bf4152c21e79da74c034 (diff) | |
| download | gem5-57e5401d954d46fea45ca3eaafa8ae655659da39.tar.xz | |
stats: Bump stats for the fixes, and mostly DRAM controller changes
Diffstat (limited to 'tests/quick/se/00.hello/ref/mips')
5 files changed, 543 insertions, 398 deletions
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 5e15549ca..12868f8fc 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 24975000 # Number of ticks simulated -final_tick 24975000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 24907000 # Number of ticks simulated +final_tick 24907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 86020 # Simulator instruction rate (inst/s) -host_op_rate 86001 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 369354314 # Simulator tick rate (ticks/s) -host_mem_usage 263428 # Number of bytes of host memory used +host_inst_rate 84163 # Simulator instruction rate (inst/s) +host_op_rate 84145 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 360406899 # Simulator tick rate (ticks/s) +host_mem_usage 264444 # Number of bytes of host memory used host_seconds 0.07 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 20288 # Nu system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 455 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 812332332 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 353633634 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1165965966 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 812332332 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 812332332 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 812332332 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 353633634 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1165965966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 814550126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 354599109 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1169149235 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 814550126 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 814550126 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 814550126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 354599109 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1169149235 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 455 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 455 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 24894000 # Total gap between requests +system.physmem.totGap 24826000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -186,34 +186,32 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 75 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 267.093333 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 186.339521 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 256.296765 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18 24.00% 24.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 29 38.67% 62.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 12.00% 74.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 10.67% 85.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 5.33% 90.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 1.33% 92.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 1.33% 93.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 6.67% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 75 # Bytes accessed per row activation -system.physmem.totQLat 3086250 # Total ticks spent queuing -system.physmem.totMemAccLat 13542500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 106 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 268.075472 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.680617 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 244.800860 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 25 23.58% 23.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40 37.74% 61.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14 13.21% 74.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 10 9.43% 83.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 7 6.60% 90.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 1.89% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 2.83% 95.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 4.72% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 106 # Bytes accessed per row activation +system.physmem.totQLat 4873000 # Total ticks spent queuing +system.physmem.totMemAccLat 13404250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2275000 # Total ticks spent in databus transfers -system.physmem.totBankLat 8181250 # Total ticks spent accessing banks -system.physmem.avgQLat 6782.97 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 17980.77 # Average bank access latency per DRAM burst +system.physmem.avgQLat 10709.89 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29763.74 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1165.97 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29459.89 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1169.15 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1165.97 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1169.15 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.11 # Data bus utilization in percentage -system.physmem.busUtilRead 9.11 # Data bus utilization in percentage for reads +system.physmem.busUtil 9.13 # Data bus utilization in percentage +system.physmem.busUtilRead 9.13 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.51 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -221,10 +219,14 @@ system.physmem.readRowHits 344 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 75.60 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 54712.09 # Average gap between requests +system.physmem.avgGap 54562.64 # Average gap between requests system.physmem.pageHitRate 75.60 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.04 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1165965966 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem.memoryStateTime::REF 780000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 22841500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1169149235 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 404 # Transaction distribution system.membus.trans_dist::ReadResp 404 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution @@ -237,8 +239,8 @@ system.membus.data_through_bus 29120 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 552000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4258000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4259500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 1156 # Number of BP lookups system.cpu.branchPred.condPredicted 861 # Number of conditional branches predicted @@ -268,7 +270,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 49951 # number of cpu cycles simulated +system.cpu.numCycles 49815 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 432 # Number of Branches Predicted As Taken (True). @@ -290,12 +292,12 @@ system.cpu.execution_unit.executions 3133 # Nu system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9487 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9486 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 463 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 44568 # Number of cycles cpu's stages were not processed +system.cpu.timesIdled 462 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 44432 # Number of cycles cpu's stages were not processed system.cpu.runCycles 5383 # Number of cycles cpu stages are processed. -system.cpu.activity 10.776561 # Percentage of cycles cpu is active +system.cpu.activity 10.805982 # Percentage of cycles cpu is active system.cpu.comLoads 1163 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 915 # Number of Branches instructions committed @@ -307,36 +309,36 @@ system.cpu.committedInsts 5814 # Nu system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total) -system.cpu.cpi 8.591503 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 8.568111 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 8.591503 # CPI: Total CPI of All Threads -system.cpu.ipc 0.116394 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 8.568111 # CPI: Total CPI of All Threads +system.cpu.ipc 0.116712 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.116394 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 46303 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.116712 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 46167 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 3648 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 7.303157 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 47138 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 7.323095 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 47002 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 2813 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 5.631519 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 47184 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 5.646894 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 47048 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 2767 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 5.539429 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 48713 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 5.554552 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 48577 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1238 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.478429 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 47063 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.485195 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46927 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 2888 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 5.781666 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 5.797451 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 150.508435 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 150.585033 # Cycle average of tags in use system.cpu.icache.tags.total_refs 428 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1.341693 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 150.508435 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073490 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073490 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 150.585033 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073528 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073528 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 306 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id @@ -355,12 +357,12 @@ system.cpu.icache.demand_misses::cpu.inst 350 # n system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses system.cpu.icache.overall_misses::total 350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25364500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25364500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25364500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25364500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25364500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25364500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25291750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25291750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25291750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25291750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25291750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25291750 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 778 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses @@ -373,12 +375,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.449871 system.cpu.icache.demand_miss_rate::total 0.449871 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.449871 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.449871 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72470 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72470 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72470 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72470 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72470 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72470 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72262.142857 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72262.142857 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72262.142857 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72262.142857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72262.142857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72262.142857 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -399,26 +401,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319 system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23031000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23031000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23031000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23031000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23031000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23031000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22956750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22956750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22956750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22956750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22956750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22956750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.410026 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.410026 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.410026 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72197.492163 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72197.492163 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72197.492163 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72197.492163 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72197.492163 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72197.492163 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71964.733542 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71964.733542 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71964.733542 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71964.733542 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71964.733542 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71964.733542 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1171091091 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1174288353 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution @@ -433,21 +435,21 @@ system.cpu.toL2Bus.data_through_bus 29248 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 228500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 538000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 538750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 225500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 226250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 208.255183 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 208.347330 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.186433 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.068750 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004644 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.267110 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.080220 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004647 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001711 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006355 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006358 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 249 # Occupied blocks per task id @@ -471,17 +473,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22685500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6903000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29588500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3846500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3846500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22685500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10749500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33435000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22685500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10749500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33435000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22611250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6877000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29488250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3810250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3810250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22611250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10687250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33298500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22611250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10687250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33298500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -504,17 +506,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71563.091483 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79344.827586 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73238.861386 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75421.568627 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75421.568627 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71563.091483 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77894.927536 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73483.516484 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71563.091483 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77894.927536 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73483.516484 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71328.864353 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79045.977011 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72990.717822 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74710.784314 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74710.784314 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71328.864353 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77443.840580 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73183.516484 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71328.864353 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77443.840580 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73183.516484 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -534,17 +536,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18705000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5824500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24529500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3204500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3204500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18705000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9029000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27734000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18705000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9029000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27734000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18629250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5798500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24427750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3166750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3166750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18629250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8965250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27594500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18629250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8965250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27594500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -556,27 +558,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59006.309148 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66948.275862 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60716.584158 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62833.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62833.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59006.309148 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65427.536232 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60953.846154 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59006.309148 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65427.536232 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60953.846154 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58767.350158 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66649.425287 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60464.727723 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62093.137255 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62093.137255 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58767.350158 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64965.579710 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60647.252747 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58767.350158 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64965.579710 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60647.252747 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 90.278621 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 90.296415 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1638 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.869565 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 90.278621 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022041 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022041 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 90.296415 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022045 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022045 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id @@ -599,14 +601,14 @@ system.cpu.dcache.demand_misses::cpu.data 450 # n system.cpu.dcache.demand_misses::total 450 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 450 # number of overall misses system.cpu.dcache.overall_misses::total 450 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7687000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7687000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21761250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21761250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29448250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29448250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29448250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29448250 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7634750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7634750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21637250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21637250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29272000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29272000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29272000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29272000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -623,14 +625,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.215517 system.cpu.dcache.demand_miss_rate::total 0.215517 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.215517 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.215517 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79247.422680 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 79247.422680 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61646.600567 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61646.600567 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65440.555556 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65440.555556 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65440.555556 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65440.555556 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78708.762887 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 78708.762887 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61295.325779 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61295.325779 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65048.888889 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65048.888889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65048.888889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65048.888889 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked @@ -655,14 +657,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6996500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6996500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3900500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3900500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10897000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10897000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10897000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10897000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6970500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6970500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3864250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3864250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10834750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10834750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10834750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10834750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -671,14 +673,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80419.540230 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80419.540230 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76480.392157 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76480.392157 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78963.768116 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78963.768116 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78963.768116 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78963.768116 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80120.689655 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80120.689655 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75769.607843 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75769.607843 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78512.681159 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78512.681159 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78512.681159 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78512.681159 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index cbbbf2296..6e934b1b9 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 21918500 # Number of ticks simulated -final_tick 21918500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21843500 # Number of ticks simulated +final_tick 21843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56826 # Simulator instruction rate (inst/s) -host_op_rate 56817 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 241494238 # Simulator tick rate (ticks/s) -host_mem_usage 266500 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 63396 # Simulator instruction rate (inst/s) +host_op_rate 63384 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 268482897 # Simulator tick rate (ticks/s) +host_mem_usage 267540 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21440 # Nu system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory system.physmem.num_reads::total 477 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 978169127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 414626913 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1392796040 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 978169127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 978169127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 978169127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 414626913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1392796040 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 981527686 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 416050541 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1397578227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 981527686 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 981527686 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 981527686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 416050541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1397578227 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 477 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 477 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21839000 # Total gap between requests +system.physmem.totGap 21764000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 285 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,34 +186,33 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 87 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 246.436782 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 168.540369 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 250.647056 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 26 29.89% 29.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 32 36.78% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13 14.94% 81.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6 6.90% 88.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 2.30% 90.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 1.15% 91.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 2.30% 94.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 5.75% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 87 # Bytes accessed per row activation -system.physmem.totQLat 2715000 # Total ticks spent queuing -system.physmem.totMemAccLat 13776250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 109 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 254.238532 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.990405 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 249.769927 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 31 28.44% 28.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40 36.70% 65.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 16 14.68% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8 7.34% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 3.67% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 0.92% 91.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 2.75% 94.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 0.92% 95.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 4.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 109 # Bytes accessed per row activation +system.physmem.totQLat 4715500 # Total ticks spent queuing +system.physmem.totMemAccLat 13659250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2385000 # Total ticks spent in databus transfers -system.physmem.totBankLat 8676250 # Total ticks spent accessing banks -system.physmem.avgQLat 5691.82 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 18189.20 # Average bank access latency per DRAM burst +system.physmem.avgQLat 9885.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28881.03 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1392.80 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28635.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1397.58 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1392.80 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1397.58 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.88 # Data bus utilization in percentage -system.physmem.busUtilRead 10.88 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.92 # Data bus utilization in percentage +system.physmem.busUtilRead 10.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -221,10 +220,14 @@ system.physmem.readRowHits 357 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 74.84 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45784.07 # Average gap between requests +system.physmem.avgGap 45626.83 # Average gap between requests system.physmem.pageHitRate 74.84 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1392796040 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem.memoryStateTime::REF 520000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 15319000 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1397578227 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 426 # Transaction distribution system.membus.trans_dist::ReadResp 426 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution @@ -235,10 +238,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 30528 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 604500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4473250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 20.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 4474250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 20.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 2174 # Number of BP lookups system.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted @@ -268,7 +271,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 43838 # number of cpu cycles simulated +system.cpu.numCycles 43688 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 8831 # Number of cycles fetch is stalled on an Icache miss @@ -277,18 +280,18 @@ system.cpu.fetch.Branches 2174 # Nu system.cpu.fetch.predictedBranches 753 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 3213 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1374 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1408 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 1402 # Number of cycles fetch has spent blocked system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps system.cpu.fetch.CacheLines 1965 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 277 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14505 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.908859 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.220900 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 14499 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.909235 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.221283 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11292 77.85% 77.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1317 9.08% 86.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 104 0.72% 87.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 131 0.90% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11286 77.84% 77.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1317 9.08% 86.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 104 0.72% 87.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 131 0.90% 88.54% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 305 2.10% 90.65% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 115 0.79% 91.44% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 150 1.03% 92.48% # Number of instructions fetched each cycle (Total) @@ -297,11 +300,11 @@ system.cpu.fetch.rateDist::8 933 6.43% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14505 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.049592 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.300721 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::total 14499 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.049762 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.301753 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 8899 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1660 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 1654 # Number of cycles decode is blocked system.cpu.decode.RunCycles 3025 # Number of cycles decode is running system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 868 # Number of cycles decode is squashing @@ -311,8 +314,8 @@ system.cpu.decode.DecodedInsts 12292 # Nu system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 868 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 9081 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 527 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 983 # count of cycles rename stalled for serializing inst +system.cpu.rename.BlockCycles 531 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 973 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2898 # Number of cycles rename is running system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 11862 # Number of instructions processed by rename @@ -339,14 +342,14 @@ system.cpu.iq.iqSquashedInstsIssued 39 # Nu system.cpu.iq.iqSquashedInstsExamined 3412 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 2076 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14505 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.571734 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.240341 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14499 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.571970 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.240543 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10922 75.30% 75.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1422 9.80% 85.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 891 6.14% 91.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 553 3.81% 95.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10916 75.29% 75.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1422 9.81% 85.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 891 6.15% 91.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 553 3.81% 95.05% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 355 2.45% 97.50% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 226 1.56% 99.06% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 89 0.61% 99.68% # Number of insts issued each cycle @@ -355,7 +358,7 @@ system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14505 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14499 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 5 3.12% 3.12% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available @@ -425,10 +428,10 @@ system.cpu.iq.FU_type_0::MemWrite 1104 13.31% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 8293 # Type of FU issued -system.cpu.iq.rate 0.189174 # Inst issue rate +system.cpu.iq.rate 0.189823 # Inst issue rate system.cpu.iq.fu_busy_cnt 160 # FU busy when requested system.cpu.iq.fu_busy_rate 0.019293 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31286 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 31280 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 12643 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 7453 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads @@ -469,23 +472,23 @@ system.cpu.iew.exec_nop 1512 # nu system.cpu.iew.exec_refs 3186 # number of memory reference insts executed system.cpu.iew.exec_branches 1344 # Number of branches executed system.cpu.iew.exec_stores 1079 # Number of stores executed -system.cpu.iew.exec_rate 0.180483 # Inst execution rate +system.cpu.iew.exec_rate 0.181102 # Inst execution rate system.cpu.iew.wb_sent 7546 # cumulative count of insts sent to commit system.cpu.iew.wb_count 7455 # cumulative count of insts written-back system.cpu.iew.wb_producers 2921 # num instructions producing a value system.cpu.iew.wb_consumers 4197 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.170058 # insts written-back per cycle +system.cpu.iew.wb_rate 0.170642 # insts written-back per cycle system.cpu.iew.wb_fanout 0.695973 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 4914 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13637 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.426267 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.206560 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 13631 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.426454 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.206792 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11235 82.39% 82.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11229 82.38% 82.38% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 999 7.33% 89.71% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 630 4.62% 94.33% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 315 2.31% 96.64% # Number of insts commited each cycle @@ -497,7 +500,7 @@ system.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13637 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13631 # Number of insts commited each cycle system.cpu.commit.committedInsts 5813 # Number of instructions committed system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -508,25 +511,60 @@ system.cpu.commit.branches 915 # Nu system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. system.cpu.commit.int_insts 5111 # Number of committed integer instructions. system.cpu.commit.function_calls 87 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 657 11.30% 11.30% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 3062 52.68% 63.98% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 3 0.05% 64.03% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 1 0.02% 64.05% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 2 0.03% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.08% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1163 20.01% 84.09% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 925 15.91% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 5813 # Class of committed instruction system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 24245 # The number of ROB reads +system.cpu.rob.rob_reads 24239 # The number of ROB reads system.cpu.rob.rob_writes 22333 # The number of ROB writes -system.cpu.timesIdled 286 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29333 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 287 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29189 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5156 # Number of Instructions Simulated system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5156 # Number of Instructions Simulated -system.cpu.cpi 8.502327 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.502327 # CPI: Total CPI of All Threads -system.cpu.ipc 0.117615 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.117615 # IPC: Total IPC of All Threads +system.cpu.cpi 8.473235 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.473235 # CPI: Total CPI of All Threads +system.cpu.ipc 0.118019 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.118019 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 10743 # number of integer regfile reads system.cpu.int_regfile_writes 5234 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 148 # number of misc regfile reads -system.cpu.toL2Bus.throughput 1401555763 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1406368027 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 429 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution @@ -541,19 +579,19 @@ system.cpu.toL2Bus.data_through_bus 30720 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 570750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 571500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 227000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 228250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 161.390328 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 161.382673 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1514 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 4.479290 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 161.390328 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078804 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078804 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 161.382673 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078800 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078800 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id @@ -572,12 +610,12 @@ system.cpu.icache.demand_misses::cpu.inst 451 # n system.cpu.icache.demand_misses::total 451 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 451 # number of overall misses system.cpu.icache.overall_misses::total 451 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31256750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31256750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31256750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31256750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31256750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31256750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31159250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31159250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31159250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31159250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31159250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31159250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses @@ -590,12 +628,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.229517 system.cpu.icache.demand_miss_rate::total 0.229517 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.229517 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.229517 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69305.432373 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69305.432373 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69305.432373 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69305.432373 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69305.432373 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69305.432373 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69089.246120 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69089.246120 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69089.246120 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69089.246120 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69089.246120 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69089.246120 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -616,36 +654,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 338 system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24262750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24262750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24262750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24262750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24262750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24262750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24154000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24154000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24154000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24154000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24154000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24154000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172010 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.172010 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.172010 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71783.284024 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71783.284024 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71783.284024 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71783.284024 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71783.284024 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71783.284024 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71461.538462 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71461.538462 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71461.538462 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71461.538462 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71461.538462 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71461.538462 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 221.496759 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 221.484913 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.678282 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.818477 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.674419 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.810494 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004995 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001764 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006760 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006759 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 426 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id @@ -669,17 +707,17 @@ system.cpu.l2cache.demand_misses::total 477 # nu system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses system.cpu.l2cache.overall_misses::total 477 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23894750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7065750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30960500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3800750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3800750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23894750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10866500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34761250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23894750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10866500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34761250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23786000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7056500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 30842500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3776250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3776250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 23786000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10832750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34618750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 23786000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10832750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34618750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 429 # number of ReadReq accesses(hits+misses) @@ -702,17 +740,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993750 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993750 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71327.611940 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77645.604396 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72677.230047 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74524.509804 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74524.509804 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71327.611940 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76524.647887 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72874.737945 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71327.611940 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76524.647887 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72874.737945 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71002.985075 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77543.956044 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72400.234742 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74044.117647 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74044.117647 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71002.985075 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76286.971831 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72575.995807 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71002.985075 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76286.971831 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72575.995807 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -732,17 +770,17 @@ system.cpu.l2cache.demand_mshr_misses::total 477 system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 477 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19660250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5948250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25608500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3170750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3170750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19660250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9119000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28779250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19660250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9119000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28779250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19551000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5938500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25489500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3144250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3144250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19551000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9082750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28633750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19551000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9082750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28633750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993007 # mshr miss rate for ReadReq accesses @@ -754,27 +792,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993750 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993750 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58687.313433 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65365.384615 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60113.849765 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62171.568627 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62171.568627 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58687.313433 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64218.309859 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60333.857442 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58687.313433 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64218.309859 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60333.857442 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58361.194030 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65258.241758 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59834.507042 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61651.960784 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61651.960784 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58361.194030 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63963.028169 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60028.825996 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58361.194030 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63963.028169 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60028.825996 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 91.623425 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 91.603992 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 91.623425 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022369 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022369 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 91.603992 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022364 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022364 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id @@ -797,14 +835,14 @@ system.cpu.dcache.demand_misses::cpu.data 510 # n system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses system.cpu.dcache.overall_misses::total 510 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10261250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10261250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22413999 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22413999 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32675249 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32675249 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32675249 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32675249 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10242750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10242750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22302249 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22302249 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32544999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32544999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32544999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32544999 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1980 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -821,19 +859,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.175559 system.cpu.dcache.demand_miss_rate::total 0.175559 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.175559 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.175559 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69332.770270 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 69332.770270 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61917.124309 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61917.124309 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64069.115686 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64069.115686 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64069.115686 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64069.115686 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 605 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69207.770270 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 69207.770270 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61608.422652 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61608.422652 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63813.723529 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63813.723529 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63813.723529 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63813.723529 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 611 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.545455 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -853,14 +891,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7160250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7160250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3852749 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3852749 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11012999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11012999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11012999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11012999 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7151000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7151000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3828249 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3828249 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10979249 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10979249 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10979249 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10979249 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045960 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045960 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -869,14 +907,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048881 system.cpu.dcache.demand_mshr_miss_rate::total 0.048881 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.048881 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78684.065934 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78684.065934 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75544.098039 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75544.098039 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77556.330986 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77556.330986 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77556.330986 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77556.330986 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78582.417582 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78582.417582 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75063.705882 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75063.705882 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77318.654930 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77318.654930 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77318.654930 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77318.654930 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt index b2f335f88..c5418ef55 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2907000 # Number of ticks simulated final_tick 2907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99853 # Simulator instruction rate (inst/s) -host_op_rate 99820 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49894332 # Simulator tick rate (ticks/s) -host_mem_usage 269208 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 1298058 # Simulator instruction rate (inst/s) +host_op_rate 1293725 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 644853594 # Simulator tick rate (ticks/s) +host_mem_usage 255756 # Number of bytes of host memory used +host_seconds 0.00 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -81,5 +81,40 @@ system.cpu.num_busy_cycles 5815 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 915 # Number of branches fetched +system.cpu.op_class::No_OpClass 657 11.30% 11.30% # Class of executed instruction +system.cpu.op_class::IntAlu 3063 52.67% 63.97% # Class of executed instruction +system.cpu.op_class::IntMult 3 0.05% 64.02% # Class of executed instruction +system.cpu.op_class::IntDiv 1 0.02% 64.04% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 64.08% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::MemRead 1163 20.00% 84.08% # Class of executed instruction +system.cpu.op_class::MemWrite 926 15.92% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5815 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 24111f1bf..88e0b5c68 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000125 # Nu sim_ticks 125334 # Number of ticks simulated final_tick 125334 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 32356 # Simulator instruction rate (inst/s) -host_op_rate 32352 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 697352 # Simulator tick rate (ticks/s) -host_mem_usage 176168 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 56489 # Simulator instruction rate (inst/s) +host_op_rate 56481 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1217426 # Simulator tick rate (ticks/s) +host_mem_usage 162604 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -146,6 +146,41 @@ system.cpu.num_busy_cycles 125334 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 915 # Number of branches fetched +system.cpu.op_class::No_OpClass 657 11.30% 11.30% # Class of executed instruction +system.cpu.op_class::IntAlu 3063 52.67% 63.97% # Class of executed instruction +system.cpu.op_class::IntMult 3 0.05% 64.02% # Class of executed instruction +system.cpu.op_class::IntDiv 1 0.02% 64.04% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 64.08% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::MemRead 1163 20.00% 84.08% # Class of executed instruction +system.cpu.op_class::MemWrite 926 15.92% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5815 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.954490 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1493 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1489 diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index d941cff49..ee2cc6627 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000032 # Nu sim_ticks 31633000 # Number of ticks simulated final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119247 # Simulator instruction rate (inst/s) -host_op_rate 119199 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 648290000 # Simulator tick rate (ticks/s) -host_mem_usage 277916 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 474922 # Simulator instruction rate (inst/s) +host_op_rate 474341 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2577866515 # Simulator tick rate (ticks/s) +host_mem_usage 263440 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -87,6 +87,41 @@ system.cpu.num_busy_cycles 63266 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 915 # Number of branches fetched +system.cpu.op_class::No_OpClass 657 11.30% 11.30% # Class of executed instruction +system.cpu.op_class::IntAlu 3063 52.67% 63.97% # Class of executed instruction +system.cpu.op_class::IntMult 3 0.05% 64.02% # Class of executed instruction +system.cpu.op_class::IntDiv 1 0.02% 64.04% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 64.08% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.08% # Class of executed instruction +system.cpu.op_class::MemRead 1163 20.00% 84.08% # Class of executed instruction +system.cpu.op_class::MemWrite 926 15.92% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5815 # Class of executed instruction system.cpu.icache.tags.replacements 13 # number of replacements system.cpu.icache.tags.tagsinuse 132.545353 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5513 # Total number of references to valid blocks. |