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authorSteve Reinhardt <steve.reinhardt@amd.com>2014-06-22 14:33:09 -0700
committerSteve Reinhardt <steve.reinhardt@amd.com>2014-06-22 14:33:09 -0700
commit5b08e211ab35fd6d936dafda45014c78b5e68300 (patch)
tree771950b6f1e0c775d83a5f03f2387f2e3850cc58 /tests/quick/se/00.hello/ref/mips
parentb085db84afcbb4824d34b8755f4c09c1fcfefcee (diff)
downloadgem5-5b08e211ab35fd6d936dafda45014c78b5e68300.tar.xz
stats: update for O3 changes
Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
Diffstat (limited to 'tests/quick/se/00.hello/ref/mips')
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini28
-rwxr-xr-xtests/quick/se/00.hello/ref/mips/linux/o3-timing/simout12
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt968
3 files changed, 509 insertions, 499 deletions
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
index df84ba05d..d92641c25 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
@@ -18,6 +18,7 @@ eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
+load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
@@ -115,6 +116,7 @@ smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
+socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
@@ -601,7 +603,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/dist/test-progs/hello/bin/mips/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -630,9 +632,9 @@ master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
@@ -643,27 +645,33 @@ device_rowbuffer_size=1024
devices_per_rank=8
eventq_index=0
in_addr_map=true
+max_accesses_per_row=16
mem_sched_policy=frfcfs
+min_writes_per_switch=16
null=false
-page_policy=open
+page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
-tRFC=300000
+tRFC=260000
tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
index 3925c4814..f2d8bae1a 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/simout
+Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 22 2014 16:53:01
-gem5 started Jan 22 2014 17:28:02
-gem5 executing on u200540-lin
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing
+gem5 compiled Jun 21 2014 10:59:13
+gem5 started Jun 21 2014 10:59:41
+gem5 executing on phenom
+command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
-Exiting @ tick 21898500 because target called exit()
+Exiting @ tick 21842500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
index dc9e77234..46dc5a264 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -1,42 +1,42 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000022 # Number of seconds simulated
-sim_ticks 21843500 # Number of ticks simulated
-final_tick 21843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 21842500 # Number of ticks simulated
+final_tick 21842500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 63396 # Simulator instruction rate (inst/s)
-host_op_rate 63384 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 268482897 # Simulator tick rate (ticks/s)
-host_mem_usage 267540 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_inst_rate 54203 # Simulator instruction rate (inst/s)
+host_op_rate 54195 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 229554116 # Simulator tick rate (ticks/s)
+host_mem_usage 222444 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
sim_insts 5156 # Number of instructions simulated
sim_ops 5156 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory
-system.physmem.bytes_read::total 30528 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory
+system.physmem.bytes_read::total 30464 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 477 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 981527686 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 416050541 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1397578227 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 981527686 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 981527686 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 981527686 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 416050541 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1397578227 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 477 # Number of read requests accepted
+system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 476 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 981572622 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 413139522 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1394712144 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 981572622 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 981572622 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 981572622 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 413139522 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1394712144 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 476 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 477 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 476 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 30528 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 30464 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 30528 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 30464 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
@@ -56,7 +56,7 @@ system.physmem.perBankRdBursts::11 20 # Pe
system.physmem.perBankRdBursts::12 51 # Per bank write bursts
system.physmem.perBankRdBursts::13 29 # Per bank write bursts
system.physmem.perBankRdBursts::14 77 # Per bank write bursts
-system.physmem.perBankRdBursts::15 8 # Per bank write bursts
+system.physmem.perBankRdBursts::15 7 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 21764000 # Total gap between requests
+system.physmem.totGap 21770000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 477 # Read request sizes (log2)
+system.physmem.readPktSize::6 476 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@@ -91,7 +91,7 @@ system.physmem.writePktSize::4 0 # Wr
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 284 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
@@ -186,72 +186,72 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 109 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 254.238532 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 174.990405 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 249.769927 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 31 28.44% 28.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 40 36.70% 65.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 16 14.68% 79.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 8 7.34% 87.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 4 3.67% 90.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1 0.92% 91.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 3 2.75% 94.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1 0.92% 95.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 5 4.59% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 109 # Bytes accessed per row activation
-system.physmem.totQLat 4715500 # Total ticks spent queuing
-system.physmem.totMemAccLat 13659250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2385000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 9885.74 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 108 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 255.407407 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 175.497802 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 250.634672 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 31 28.70% 28.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 39 36.11% 64.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 16 14.81% 79.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 8 7.41% 87.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 4 3.70% 90.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1 0.93% 91.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 3 2.78% 94.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1 0.93% 95.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 5 4.63% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 108 # Bytes accessed per row activation
+system.physmem.totQLat 4718000 # Total ticks spent queuing
+system.physmem.totMemAccLat 13643000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2380000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 9911.76 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 28635.74 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1397.58 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 28661.76 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1394.71 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1397.58 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1394.71 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 10.92 # Data bus utilization in percentage
-system.physmem.busUtilRead 10.92 # Data bus utilization in percentage for reads
+system.physmem.busUtil 10.90 # Data bus utilization in percentage
+system.physmem.busUtilRead 10.90 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 357 # Number of row buffer hits during reads
+system.physmem.readRowHits 358 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 74.84 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 75.21 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 45626.83 # Average gap between requests
-system.physmem.pageHitRate 74.84 # Row buffer hit rate, read and write combined
+system.physmem.avgGap 45735.29 # Average gap between requests
+system.physmem.pageHitRate 75.21 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 11000 # Time in different power states
system.physmem.memoryStateTime::REF 520000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 15319000 # Time in different power states
+system.physmem.memoryStateTime::ACT 15316000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.membus.throughput 1397578227 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 426 # Transaction distribution
-system.membus.trans_dist::ReadResp 426 # Transaction distribution
+system.membus.throughput 1394712144 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 425 # Transaction distribution
+system.membus.trans_dist::ReadResp 425 # Transaction distribution
system.membus.trans_dist::ReadExReq 51 # Transaction distribution
system.membus.trans_dist::ReadExResp 51 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 954 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 954 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 30528 # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 952 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 952 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30464 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 30464 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 30464 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 604500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4474250 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 20.5 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4464750 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 20.4 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 2174 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted
+system.cpu.branchPred.lookups 2178 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1497 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 1651 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 492 # Number of BTB hits
+system.cpu.branchPred.BTBLookups 1659 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 491 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 29.800121 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 261 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 29.596142 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 258 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 66 # Number of incorrect RAS predictions.
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
@@ -271,236 +271,236 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 8 # Number of system calls
-system.cpu.numCycles 43688 # number of cpu cycles simulated
+system.cpu.numCycles 43686 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 8831 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 13183 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2174 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 753 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 3213 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1374 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 1402 # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles 8839 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 13190 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2178 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 749 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 3214 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1378 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 1314 # Number of cycles fetch has spent blocked
system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 1965 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 277 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 14499 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.909235 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.221283 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 1971 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 279 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 14424 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.914448 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.226738 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 11286 77.84% 77.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1317 9.08% 86.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 104 0.72% 87.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 131 0.90% 88.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 305 2.10% 90.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 115 0.79% 91.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 150 1.03% 92.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 158 1.09% 93.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 933 6.43% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 11210 77.72% 77.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1316 9.12% 86.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 106 0.73% 87.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 131 0.91% 88.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 305 2.11% 90.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 113 0.78% 91.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 150 1.04% 92.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 160 1.11% 93.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 933 6.47% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 14499 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.049762 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.301753 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 8899 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 1654 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 3025 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 868 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 157 # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total 14424 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.049856 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.301927 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 8852 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 1624 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 3059 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 17 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 872 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 158 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 12292 # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts 12284 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 868 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 9081 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 531 # Number of cycles rename is blocking
+system.cpu.rename.SquashCycles 872 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 9006 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 365 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 973 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2898 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 11862 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 7176 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 14099 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 13870 # Number of integer rename lookups
+system.cpu.rename.RunCycles 2923 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 285 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 11879 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full
+system.cpu.rename.SQFullEvents 266 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 7180 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 14112 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 13884 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 3778 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 16 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 328 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2457 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1193 # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts 151 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2468 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1195 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 9210 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded 9223 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 8293 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 3412 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 2076 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 8300 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 3436 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 2075 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 14499 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.571970 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.240543 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 14424 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.575430 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.252383 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 10916 75.29% 75.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1422 9.81% 85.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 891 6.15% 91.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 553 3.81% 95.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 355 2.45% 97.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 226 1.56% 99.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 89 0.61% 99.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 30 0.21% 99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 10895 75.53% 75.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1375 9.53% 85.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 844 5.85% 90.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 571 3.96% 94.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 375 2.60% 97.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 225 1.56% 99.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 91 0.63% 99.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 31 0.21% 99.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 14499 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 14424 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 5 3.12% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 101 63.12% 66.25% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 54 33.75% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 5 3.09% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 102 62.96% 66.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 55 33.95% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 4933 59.48% 59.48% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.59% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2247 27.10% 86.69% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1104 13.31% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 4936 59.47% 59.47% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.53% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.58% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2249 27.10% 86.67% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1106 13.33% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 8293 # Type of FU issued
-system.cpu.iq.rate 0.189823 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 160 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.019293 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 31280 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 12643 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 7453 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 8300 # Type of FU issued
+system.cpu.iq.rate 0.189992 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 162 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.019518 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 31229 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 12679 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 7467 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 8451 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 8460 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 68 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1294 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1305 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 270 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 32 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 868 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 349 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 10734 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2457 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles 872 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 287 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 10750 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 86 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2468 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1195 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 362 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 463 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 7912 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2107 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 381 # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 100 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 365 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 465 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 7921 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2110 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 379 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1512 # number of nop insts executed
-system.cpu.iew.exec_refs 3186 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1344 # Number of branches executed
-system.cpu.iew.exec_stores 1079 # Number of stores executed
-system.cpu.iew.exec_rate 0.181102 # Inst execution rate
-system.cpu.iew.wb_sent 7546 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 7455 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 2921 # num instructions producing a value
-system.cpu.iew.wb_consumers 4197 # num instructions consuming a value
+system.cpu.iew.exec_nop 1515 # number of nop insts executed
+system.cpu.iew.exec_refs 3187 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1350 # Number of branches executed
+system.cpu.iew.exec_stores 1077 # Number of stores executed
+system.cpu.iew.exec_rate 0.181317 # Inst execution rate
+system.cpu.iew.wb_sent 7554 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 7469 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 2985 # num instructions producing a value
+system.cpu.iew.wb_consumers 4341 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.170642 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.695973 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.170970 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.687630 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 4914 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 4930 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 13631 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.426454 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.206792 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 13552 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.428940 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.213640 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 11229 82.38% 82.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 999 7.33% 89.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 630 4.62% 94.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 315 2.31% 96.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 149 1.09% 97.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 94 0.69% 98.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 68 0.50% 98.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 41 0.30% 99.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 11200 82.64% 82.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 943 6.96% 89.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 594 4.38% 93.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 344 2.54% 96.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 162 1.20% 97.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 97 0.72% 98.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 69 0.51% 98.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 41 0.30% 99.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 102 0.75% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 13631 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 13552 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5813 # Number of instructions committed
system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -546,93 +546,93 @@ system.cpu.commit.op_class_0::MemWrite 925 15.91% 100.00% # Cl
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 5813 # Class of committed instruction
-system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 24239 # The number of ROB reads
-system.cpu.rob.rob_writes 22333 # The number of ROB writes
-system.cpu.timesIdled 287 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 29189 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 24180 # The number of ROB reads
+system.cpu.rob.rob_writes 22370 # The number of ROB writes
+system.cpu.timesIdled 295 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 29262 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5156 # Number of Instructions Simulated
system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 8.473235 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 8.473235 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.118019 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.118019 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 10743 # number of integer regfile reads
-system.cpu.int_regfile_writes 5234 # number of integer regfile writes
+system.cpu.cpi 8.472847 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 8.472847 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.118024 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.118024 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 10764 # number of integer regfile reads
+system.cpu.int_regfile_writes 5241 # number of integer regfile writes
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
system.cpu.misc_regfile_reads 148 # number of misc regfile reads
-system.cpu.toL2Bus.throughput 1406368027 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 429 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution
+system.cpu.toL2Bus.throughput 1403502346 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 428 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 676 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 960 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 958 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21632 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size::total 30720 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 30720 # Total data (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 30656 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 30656 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.occupancy 239500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 571500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 571750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 228250 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 226500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
system.cpu.icache.tags.replacements 17 # number of replacements
-system.cpu.icache.tags.tagsinuse 161.382673 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 1514 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 161.396825 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 1520 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 4.479290 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 4.497041 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 161.382673 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.078800 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.078800 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 161.396825 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.078807 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.078807 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.156738 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 4268 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 4268 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 1514 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1514 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1514 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1514 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1514 # number of overall hits
-system.cpu.icache.overall_hits::total 1514 # number of overall hits
+system.cpu.icache.tags.tag_accesses 4280 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 4280 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 1520 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1520 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1520 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1520 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1520 # number of overall hits
+system.cpu.icache.overall_hits::total 1520 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 451 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 451 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 451 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 451 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 451 # number of overall misses
system.cpu.icache.overall_misses::total 451 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 31159250 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 31159250 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 31159250 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 31159250 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 31159250 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 31159250 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1965 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1965 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1965 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229517 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.229517 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.229517 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.229517 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.229517 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.229517 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69089.246120 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 69089.246120 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 69089.246120 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 69089.246120 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 69089.246120 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 69089.246120 # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 31166000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 31166000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 31166000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 31166000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 31166000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 31166000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1971 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1971 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1971 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1971 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1971 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228818 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.228818 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.228818 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.228818 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.228818 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.228818 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69104.212860 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 69104.212860 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 69104.212860 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 69104.212860 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 69104.212860 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 69104.212860 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
@@ -653,42 +653,42 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 338
system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24154000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 24154000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24154000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 24154000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24154000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 24154000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172010 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.172010 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.172010 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71461.538462 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71461.538462 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71461.538462 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 71461.538462 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71461.538462 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 71461.538462 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24162750 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 24162750 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24162750 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 24162750 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24162750 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 24162750 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.171487 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.171487 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.171487 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.171487 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.171487 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.171487 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71487.426036 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71487.426036 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71487.426036 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 71487.426036 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71487.426036 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 71487.426036 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 221.484913 # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse 221.498533 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 425 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 0.007059 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.674419 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 57.810494 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.688333 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 57.810199 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004995 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001764 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.006759 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 426 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_percent::total 0.006760 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 425 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 188 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 4317 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 4317 # Number of data accesses
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012970 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 4308 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 4308 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
@@ -696,60 +696,60 @@ system.cpu.l2cache.demand_hits::total 3 # nu
system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
system.cpu.l2cache.overall_hits::total 3 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 426 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 90 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 425 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 477 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 476 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses
-system.cpu.l2cache.overall_misses::total 477 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23786000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7056500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 30842500 # number of ReadReq miss cycles
+system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses
+system.cpu.l2cache.overall_misses::total 476 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23794750 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6985750 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 30780500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3776250 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 3776250 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 23786000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 10832750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 34618750 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 23786000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 10832750 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 34618750 # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 23794750 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 10762000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 34556750 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 23794750 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 10762000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 34556750 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 429 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 428 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 338 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 480 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 479 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 338 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 480 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 479 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991124 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.993007 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.992991 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991124 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.993750 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.993737 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.993750 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71002.985075 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77543.956044 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 72400.234742 # average ReadReq miss latency
+system.cpu.l2cache.overall_miss_rate::total 0.993737 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71029.104478 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77619.444444 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 72424.705882 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74044.117647 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74044.117647 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71002.985075 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76286.971831 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72575.995807 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71002.985075 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76286.971831 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72575.995807 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71029.104478 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76326.241135 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 72598.214286 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71029.104478 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76326.241135 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72598.214286 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -759,113 +759,113 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 426 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 477 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 476 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 477 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19551000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5938500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25489500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 476 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19559250 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5880750 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25440000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3144250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3144250 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19551000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9082750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 28633750 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19551000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9082750 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 28633750 # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19559250 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9025000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 28584250 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19559250 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9025000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 28584250 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993007 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.992991 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.993750 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.993737 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.993750 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58361.194030 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65258.241758 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59834.507042 # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.993737 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58385.820896 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65341.666667 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59858.823529 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61651.960784 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61651.960784 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58361.194030 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63963.028169 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60028.825996 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58361.194030 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63963.028169 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60028.825996 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58385.820896 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64007.092199 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60050.945378 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58385.820896 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64007.092199 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60050.945378 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 91.603992 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 91.608220 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 17.021277 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 91.603992 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.022364 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.022364 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data 91.608220 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.022365 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.022365 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.034668 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 5952 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 5952 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 5965 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 5965 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 1837 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1837 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 563 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits
-system.cpu.dcache.overall_hits::total 2395 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 148 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 148 # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data 2400 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2400 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2400 # number of overall hits
+system.cpu.dcache.overall_hits::total 2400 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 150 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 150 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 362 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 362 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses
-system.cpu.dcache.overall_misses::total 510 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 10242750 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 10242750 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 22302249 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 22302249 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 32544999 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 32544999 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 32544999 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 32544999 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1980 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data 512 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 512 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 512 # number of overall misses
+system.cpu.dcache.overall_misses::total 512 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 10436500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 10436500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 22532249 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 22532249 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 32968749 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 32968749 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 32968749 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 32968749 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1987 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1987 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2905 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2905 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2905 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2905 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074747 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.074747 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2912 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2912 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2912 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2912 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075491 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.075491 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.391351 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.391351 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.175559 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.175559 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.175559 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.175559 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69207.770270 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 69207.770270 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61608.422652 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 61608.422652 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 63813.723529 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 63813.723529 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 63813.723529 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 63813.723529 # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data 0.175824 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.175824 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.175824 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.175824 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69576.666667 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 69576.666667 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62243.781768 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 62243.781768 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 64392.087891 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 64392.087891 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 64392.087891 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 64392.087891 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 611 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked
@@ -874,46 +874,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.545455
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 311 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 311 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 368 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 368 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 368 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 368 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data 371 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 371 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 371 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 371 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7151000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 7151000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7079250 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 7079250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3828249 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3828249 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10979249 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 10979249 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10979249 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 10979249 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045960 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045960 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10907499 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10907499 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10907499 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10907499 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045294 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045294 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.048881 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.048881 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78582.417582 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78582.417582 # average ReadReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048420 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.048420 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048420 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.048420 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78658.333333 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78658.333333 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75063.705882 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75063.705882 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77318.654930 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 77318.654930 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77318.654930 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 77318.654930 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77358.148936 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 77358.148936 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77358.148936 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 77358.148936 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------