diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
| commit | 57e5401d954d46fea45ca3eaafa8ae655659da39 (patch) | |
| tree | 7108ae4d529338b13daa49308c85bb7a680f7b58 /tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt | |
| parent | aa329f4757639820f921bf4152c21e79da74c034 (diff) | |
| download | gem5-57e5401d954d46fea45ca3eaafa8ae655659da39.tar.xz | |
stats: Bump stats for the fixes, and mostly DRAM controller changes
Diffstat (limited to 'tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt | 495 |
1 files changed, 266 insertions, 229 deletions
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index d62c7aac6..810e47329 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 19079500 # Number of ticks simulated -final_tick 19079500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19030500 # Number of ticks simulated +final_tick 19030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 82615 # Simulator instruction rate (inst/s) -host_op_rate 82599 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 272039638 # Simulator tick rate (ticks/s) +host_inst_rate 79159 # Simulator instruction rate (inst/s) +host_op_rate 79144 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 259986612 # Simulator tick rate (ticks/s) host_mem_usage 262500 # Number of bytes of host memory used host_seconds 0.07 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 22080 # Nu system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1157263031 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 338792945 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1496055976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1157263031 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1157263031 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1157263031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 338792945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1496055976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1160242768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 339665274 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1499908042 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1160242768 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1160242768 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1160242768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 339665274 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1499908042 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 446 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 18951000 # Total gap between requests +system.physmem.totGap 18902000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 143 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see @@ -186,45 +186,47 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 379.586207 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 226.841802 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 367.136049 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 17 29.31% 29.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14 24.14% 53.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6 10.34% 63.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3 5.17% 68.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 6.90% 75.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.45% 79.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.72% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 11 18.97% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58 # Bytes accessed per row activation -system.physmem.totQLat 2851500 # Total ticks spent queuing -system.physmem.totMemAccLat 11984000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 77 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 342.441558 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 198.974683 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 351.274465 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 28 36.36% 36.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17 22.08% 58.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6 7.79% 66.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 5 6.49% 72.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5 6.49% 79.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 2.60% 81.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 3.90% 85.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 11 14.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 77 # Bytes accessed per row activation +system.physmem.totQLat 3599250 # Total ticks spent queuing +system.physmem.totMemAccLat 11961750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2230000 # Total ticks spent in databus transfers -system.physmem.totBankLat 6902500 # Total ticks spent accessing banks -system.physmem.avgQLat 6393.50 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 15476.46 # Average bank access latency per DRAM burst +system.physmem.avgQLat 8070.07 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26869.96 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1496.06 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26820.07 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1499.91 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1496.06 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1499.91 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.69 # Data bus utilization in percentage -system.physmem.busUtilRead 11.69 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.72 # Data bus utilization in percentage +system.physmem.busUtilRead 11.72 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.79 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 358 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.27 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42491.03 # Average gap between requests +system.physmem.avgGap 42381.17 # Average gap between requests system.physmem.pageHitRate 80.27 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1496055976 # Throughput (bytes/s) +system.physmem.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem.memoryStateTime::REF 520000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 15315250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 1499908042 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 399 # Transaction distribution system.membus.trans_dist::ReadResp 399 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution @@ -235,10 +237,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 28544 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 567500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 565500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4177500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 4183750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 2235 # Number of BP lookups system.cpu.branchPred.condPredicted 1802 # Number of conditional branches predicted @@ -268,55 +270,55 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 38160 # number of cpu cycles simulated +system.cpu.numCycles 38062 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7440 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 7441 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 13154 # Number of instructions fetch has processed system.cpu.fetch.Branches 2235 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 800 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 2260 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1225 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 1309 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1810 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 309 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11787 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.115975 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.532873 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 11872 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.107985 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.525542 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9527 80.83% 80.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 176 1.49% 82.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 176 1.49% 83.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 142 1.20% 85.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 227 1.93% 86.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 132 1.12% 88.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 257 2.18% 90.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 110 0.93% 91.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1040 8.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9612 80.96% 80.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 176 1.48% 82.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 176 1.48% 83.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 142 1.20% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 227 1.91% 87.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 132 1.11% 88.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 257 2.16% 90.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 110 0.93% 91.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1040 8.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11787 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.058569 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.344706 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7519 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1384 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2094 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 81 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 11872 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.058720 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.345594 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7525 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1463 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2089 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 86 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 709 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 340 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction system.cpu.decode.DecodedInsts 11724 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 431 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 709 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7704 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 677 # Number of cycles rename is blocking +system.cpu.rename.IdleCycles 7710 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 717 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 445 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1984 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 268 # Number of cycles rename is unblocking +system.cpu.rename.RunCycles 1980 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 311 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 11305 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 230 # Number of times rename has blocked due to LSQ full +system.cpu.rename.LSQFullEvents 264 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 9699 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 18187 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 18161 # Number of integer rename lookups @@ -325,7 +327,7 @@ system.cpu.rename.CommittedMaps 4998 # Nu system.cpu.rename.UndoneMaps 4701 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 582 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 615 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 2023 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. @@ -337,23 +339,23 @@ system.cpu.iq.iqSquashedInstsIssued 241 # Nu system.cpu.iq.iqSquashedInstsExamined 4242 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 3488 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11787 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.755154 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.486388 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 11872 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.749747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.477871 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8427 71.49% 71.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1098 9.32% 80.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 791 6.71% 87.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 500 4.24% 91.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 455 3.86% 95.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 306 2.60% 98.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 132 1.12% 99.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8485 71.47% 71.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1128 9.50% 80.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 793 6.68% 87.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 504 4.25% 91.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 456 3.84% 95.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 296 2.49% 98.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 132 1.11% 99.34% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 45 0.38% 99.72% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 33 0.28% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11787 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11872 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 8 4.62% 4.62% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.62% # attempts to use FU when none available @@ -423,10 +425,10 @@ system.cpu.iq.FU_type_0::MemWrite 1627 18.28% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 8901 # Type of FU issued -system.cpu.iq.rate 0.233255 # Inst issue rate +system.cpu.iq.rate 0.233855 # Inst issue rate system.cpu.iq.fu_busy_cnt 173 # FU busy when requested system.cpu.iq.fu_busy_rate 0.019436 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29941 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 30026 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 14573 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 8128 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads @@ -467,35 +469,35 @@ system.cpu.iew.exec_nop 0 # nu system.cpu.iew.exec_refs 3201 # number of memory reference insts executed system.cpu.iew.exec_branches 1350 # Number of branches executed system.cpu.iew.exec_stores 1523 # Number of stores executed -system.cpu.iew.exec_rate 0.222746 # Inst execution rate +system.cpu.iew.exec_rate 0.223320 # Inst execution rate system.cpu.iew.wb_sent 8270 # cumulative count of insts sent to commit system.cpu.iew.wb_count 8155 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4217 # num instructions producing a value -system.cpu.iew.wb_consumers 6678 # num instructions consuming a value +system.cpu.iew.wb_producers 4187 # num instructions producing a value +system.cpu.iew.wb_consumers 6623 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.213705 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.631476 # average fanout of values written-back +system.cpu.iew.wb_rate 0.214256 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.632191 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 4574 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11078 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.522838 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.323591 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11163 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.518857 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.312790 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8698 78.52% 78.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1008 9.10% 87.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 609 5.50% 93.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 270 2.44% 95.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 170 1.53% 97.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 108 0.97% 98.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 70 0.63% 98.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 44 0.40% 99.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 101 0.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8756 78.44% 78.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1031 9.24% 87.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 625 5.60% 93.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 263 2.36% 95.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 174 1.56% 97.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 104 0.93% 98.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 65 0.58% 98.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 44 0.39% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 101 0.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11078 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11163 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -506,24 +508,59 @@ system.cpu.commit.branches 1037 # Nu system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. system.cpu.commit.int_insts 5698 # Number of committed integer instructions. system.cpu.commit.function_calls 103 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 3783 65.31% 65.31% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 0 0.00% 65.31% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 2 0.03% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 961 16.59% 81.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 5792 # Class of committed instruction system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21343 # The number of ROB reads +system.cpu.rob.rob_reads 21428 # The number of ROB reads system.cpu.rob.rob_writes 21442 # The number of ROB writes -system.cpu.timesIdled 246 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 26373 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 247 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 26190 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5792 # Number of Instructions Simulated -system.cpu.cpi 6.588398 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.588398 # CPI: Total CPI of All Threads -system.cpu.ipc 0.151782 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.151782 # IPC: Total IPC of All Threads +system.cpu.cpi 6.571478 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.571478 # CPI: Total CPI of All Threads +system.cpu.ipc 0.152173 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.152173 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 13470 # number of integer regfile reads system.cpu.int_regfile_writes 7047 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.toL2Bus.throughput 1519536675 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1523449200 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution @@ -538,19 +575,19 @@ system.cpu.toL2Bus.data_through_bus 28992 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 585250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 587750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 161250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 163000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 168.852168 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 168.931685 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1369 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.900285 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 168.852168 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.082447 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.082447 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 168.931685 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082486 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082486 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id @@ -569,12 +606,12 @@ system.cpu.icache.demand_misses::cpu.inst 441 # n system.cpu.icache.demand_misses::total 441 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 441 # number of overall misses system.cpu.icache.overall_misses::total 441 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30135000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30135000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30135000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30135000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30135000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30135000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30033500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30033500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30033500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30033500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30033500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30033500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1810 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1810 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1810 # number of demand (read+write) accesses @@ -587,12 +624,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.243646 system.cpu.icache.demand_miss_rate::total 0.243646 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.243646 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.243646 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68333.333333 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68333.333333 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68333.333333 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68333.333333 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68333.333333 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68333.333333 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68103.174603 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68103.174603 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68103.174603 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68103.174603 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68103.174603 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68103.174603 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 460 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked @@ -613,36 +650,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 351 system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24444750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24444750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24444750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24444750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24444750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24444750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24362250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24362250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24362250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24362250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24362250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24362250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193923 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.193923 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193923 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.193923 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69643.162393 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69643.162393 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69643.162393 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 69643.162393 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69643.162393 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 69643.162393 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69408.119658 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69408.119658 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69408.119658 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69408.119658 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69408.119658 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69408.119658 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 199.197303 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 199.280245 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.017544 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.717049 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.480255 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005118 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.794904 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.485341 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005121 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000961 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006079 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006082 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 216 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id @@ -669,17 +706,17 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24033250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4074500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28107750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3621750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3621750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 24033250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7696250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31729500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 24033250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7696250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31729500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23950750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4072250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28023000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3614250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3614250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 23950750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7686500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31637250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 23950750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7686500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31637250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -702,17 +739,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.984547 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69661.594203 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75453.703704 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70445.488722 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77058.510638 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77058.510638 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69661.594203 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76200.495050 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71142.376682 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69661.594203 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76200.495050 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71142.376682 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69422.463768 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75412.037037 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70233.082707 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76898.936170 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76898.936170 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69422.463768 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76103.960396 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70935.538117 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69422.463768 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76103.960396 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70935.538117 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -732,17 +769,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19691750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3410500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23102250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3044750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3044750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19691750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6455250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26147000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19691750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6455250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26147000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19603250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3407750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23011000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3033250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3033250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19603250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6441000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26044250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19603250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6441000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26044250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses @@ -754,25 +791,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57077.536232 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63157.407407 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57900.375940 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64781.914894 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64781.914894 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57077.536232 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63913.366337 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58625.560538 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57077.536232 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63913.366337 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58625.560538 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56821.014493 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63106.481481 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57671.679198 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64537.234043 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64537.234043 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56821.014493 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63772.277228 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58395.179372 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56821.014493 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63772.277228 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58395.179372 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 63.689105 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 63.690367 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2188 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 21.450980 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 63.689105 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 63.690367 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.015549 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.015549 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id @@ -797,14 +834,14 @@ system.cpu.dcache.demand_misses::cpu.data 435 # n system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses system.cpu.dcache.overall_misses::total 435 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7364750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7364750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20363246 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20363246 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27727996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27727996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27727996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27727996 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7366750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7366750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20319996 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20319996 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27686746 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27686746 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27686746 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27686746 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1577 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1577 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -821,19 +858,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.165841 system.cpu.dcache.demand_miss_rate::total 0.165841 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.165841 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.165841 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70814.903846 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70814.903846 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61520.380665 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61520.380665 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63742.519540 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63742.519540 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63742.519540 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63742.519540 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 501 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70834.134615 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70834.134615 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61389.716012 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61389.716012 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63647.691954 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63647.691954 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63647.691954 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63647.691954 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 492 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 100.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 98.400000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -853,14 +890,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4140000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4140000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3671748 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3671748 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7811748 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7811748 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7811748 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7811748 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4137750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4137750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3664248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3664248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7801998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7801998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7801998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7801998 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034876 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses @@ -869,14 +906,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038887 system.cpu.dcache.demand_mshr_miss_rate::total 0.038887 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.038887 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75272.727273 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75272.727273 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78122.297872 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78122.297872 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76585.764706 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76585.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76585.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76585.764706 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75231.818182 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75231.818182 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77962.723404 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77962.723404 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76490.176471 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76490.176471 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76490.176471 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76490.176471 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |