diff options
| author | Gabe Black <gabeblack@google.com> | 2017-03-29 16:14:05 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2017-04-05 18:40:59 +0000 |
| commit | f7ddc4672a17ee4fab3011bb1b570cc7c17dff28 (patch) | |
| tree | 1b09ee7160f513160fdbd766af3afed63f053e1d /tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt | |
| parent | 8ebc3834651857ae5e2ea755844f263d9a8c34ae (diff) | |
| download | gem5-f7ddc4672a17ee4fab3011bb1b570cc7c17dff28.tar.xz | |
stats: Update some stats after simulated program exit behavior was changed.
The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.
commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600
syscall-emul: Rewrite system call exit code
Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt | 2016 |
1 files changed, 1008 insertions, 1008 deletions
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 804710aed..189de9f2f 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,1012 +1,1012 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21189000 # Number of ticks simulated -final_tick 21189000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 143245 # Simulator instruction rate (inst/s) -host_op_rate 143198 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 523712790 # Simulator tick rate (ticks/s) -host_mem_usage 249592 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -sim_insts 5792 # Number of instructions simulated -sim_ops 5792 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 21824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 6528 # Number of bytes read from this memory -system.physmem.bytes_read::total 28352 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21824 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 341 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 102 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1029968380 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 308084383 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1338052763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1029968380 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1029968380 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1029968380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 308084383 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1338052763 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 444 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28416 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28416 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 71 # Per bank write bursts -system.physmem.perBankRdBursts::1 42 # Per bank write bursts -system.physmem.perBankRdBursts::2 55 # Per bank write bursts -system.physmem.perBankRdBursts::3 58 # Per bank write bursts -system.physmem.perBankRdBursts::4 53 # Per bank write bursts -system.physmem.perBankRdBursts::5 61 # Per bank write bursts -system.physmem.perBankRdBursts::6 52 # Per bank write bursts -system.physmem.perBankRdBursts::7 10 # Per bank write bursts -system.physmem.perBankRdBursts::8 9 # Per bank write bursts -system.physmem.perBankRdBursts::9 28 # Per bank write bursts -system.physmem.perBankRdBursts::10 1 # Per bank write bursts -system.physmem.perBankRdBursts::11 0 # Per bank write bursts -system.physmem.perBankRdBursts::12 0 # Per bank write bursts -system.physmem.perBankRdBursts::13 0 # Per bank write bursts -system.physmem.perBankRdBursts::14 4 # Per bank write bursts -system.physmem.perBankRdBursts::15 0 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21128500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 444 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.631579 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 212.894378 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 337.912685 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24 31.58% 31.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 22.37% 53.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 12 15.79% 69.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2 2.63% 72.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 3.95% 76.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4 5.26% 81.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 2.63% 84.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 3.95% 88.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 11.84% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation -system.physmem.totQLat 5920000 # Total ticks spent queuing -system.physmem.totMemAccLat 14245000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13333.33 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32083.33 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1341.07 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1341.07 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.48 # Data bus utilization in percentage -system.physmem.busUtilRead 10.48 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 358 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 47586.71 # Average gap between requests -system.physmem.pageHitRate 80.63 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 528360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 254265 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2870280 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3925590 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 28320 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5657820 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 38400 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 14532315 # Total energy per rank (pJ) -system.physmem_0.averagePower 685.810052 # Core power per rank (mW) -system.physmem_0.totalIdleTime 12505250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 17500 # Time in different power states -system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 100250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8146250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 12405000 # Time in different power states -system.physmem_1.actEnergy 85680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 34155 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 299880 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 759810 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1412160 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 6380010 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 712320 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 10913295 # Total energy per rank (pJ) -system.physmem_1.averagePower 515.021000 # Core power per rank (mW) -system.physmem_1.totalIdleTime 13660000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3594000 # Time in different power states -system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1854750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1229000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 13991250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2458 # Number of BP lookups -system.cpu.branchPred.condPredicted 2033 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 409 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2104 # Number of BTB lookups -system.cpu.branchPred.BTBHits 724 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 34.410646 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 228 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 36 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 135 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 18 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 117 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 37 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 9 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 21189000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 42379 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7639 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13455 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2458 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 970 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4277 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 847 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 146 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1865 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12512 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.075368 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.471061 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10164 81.23% 81.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 163 1.30% 82.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 210 1.68% 84.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 146 1.17% 85.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 247 1.97% 87.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 148 1.18% 88.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 304 2.43% 90.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 158 1.26% 92.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 972 7.77% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12512 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.058000 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.317492 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7217 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2933 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1957 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 275 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 791 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 149 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11520 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 456 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 275 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7386 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 930 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 461 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1904 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1556 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11074 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 22 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1496 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9775 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17991 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17965 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4777 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 27 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 402 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1923 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1570 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 32 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10204 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 65 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8807 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 41 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4477 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3567 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12512 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.703884 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.500750 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9387 75.02% 75.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 964 7.70% 82.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 667 5.33% 88.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 467 3.73% 91.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 439 3.51% 95.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 290 2.32% 97.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 213 1.70% 99.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 56 0.45% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 29 0.23% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12512 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 12 6.22% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 87 45.08% 51.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 83 43.01% 94.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 94.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 11 5.70% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5542 62.93% 62.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1815 20.61% 83.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1422 16.15% 99.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 2 0.02% 99.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 24 0.27% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8807 # Type of FU issued -system.cpu.iq.rate 0.207815 # Inst issue rate -system.cpu.iq.fu_busy_cnt 193 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021914 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30293 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14716 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8133 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 67 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8961 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 39 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 84 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 962 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 524 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 275 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 818 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 73 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10269 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 43 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1923 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1570 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 53 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 60 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 71 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 256 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 327 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8488 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1719 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 319 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3083 # number of memory reference insts executed -system.cpu.iew.exec_branches 1364 # Number of branches executed -system.cpu.iew.exec_stores 1364 # Number of stores executed -system.cpu.iew.exec_rate 0.200288 # Inst execution rate -system.cpu.iew.wb_sent 8262 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8160 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4466 # num instructions producing a value -system.cpu.iew.wb_consumers 7207 # num instructions consuming a value -system.cpu.iew.wb_rate 0.192548 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.619675 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4479 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 270 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11808 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.490515 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.351526 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9643 81.66% 81.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 845 7.16% 88.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 531 4.50% 93.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 215 1.82% 95.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 177 1.50% 96.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 110 0.93% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 132 1.12% 98.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 50 0.42% 99.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 105 0.89% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11808 # Number of insts commited each cycle -system.cpu.commit.committedInsts 5792 # Number of instructions committed -system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 2007 # Number of memory references committed -system.cpu.commit.loads 961 # Number of loads committed -system.cpu.commit.membars 7 # Number of memory barriers committed -system.cpu.commit.branches 1037 # Number of branches committed -system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. -system.cpu.commit.int_insts 5698 # Number of committed integer instructions. -system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 3783 65.31% 65.31% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 0 0.00% 65.31% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 2 0.03% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 960 16.57% 81.92% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 1027 17.73% 99.65% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 1 0.02% 99.67% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 19 0.33% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 5792 # Class of committed instruction -system.cpu.commit.bw_lim_events 105 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 21974 # The number of ROB reads -system.cpu.rob.rob_writes 21247 # The number of ROB writes -system.cpu.timesIdled 227 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29867 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 5792 # Number of Instructions Simulated -system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.316816 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.316816 # CPI: Total CPI of All Threads -system.cpu.ipc 0.136671 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.136671 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13468 # number of integer regfile reads -system.cpu.int_regfile_writes 7187 # number of integer regfile writes -system.cpu.fp_regfile_reads 25 # number of floating regfile reads -system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 66.953799 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2204 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 104 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 21.192308 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 66.953799 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.016346 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.016346 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 104 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 80 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.025391 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5386 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5386 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1483 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1483 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 721 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 721 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2204 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2204 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2204 # number of overall hits -system.cpu.dcache.overall_hits::total 2204 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 112 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 112 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 325 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 325 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses -system.cpu.dcache.overall_misses::total 437 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8129500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8129500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 32497996 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 32497996 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 40627496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 40627496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 40627496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 40627496 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1595 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1595 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2641 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2641 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2641 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2641 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070219 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070219 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.310707 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.310707 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.165468 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.165468 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.165468 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.165468 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72584.821429 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72584.821429 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99993.833846 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 99993.833846 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 92969.098398 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 92969.098398 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 92969.098398 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 92969.098398 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 749 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.222222 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 54 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 278 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 278 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 332 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 332 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 332 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 332 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 58 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 58 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 105 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 105 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 105 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 105 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4818000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4818000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4694498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4694498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9512498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9512498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9512498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9512498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036364 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036364 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.039758 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.039758 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.039758 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.039758 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83068.965517 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83068.965517 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99882.936170 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99882.936170 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90595.219048 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 90595.219048 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90595.219048 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 90595.219048 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 168.700112 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1435 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.111748 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 168.700112 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.082373 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.082373 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4079 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4079 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1435 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1435 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1435 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1435 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1435 # number of overall hits -system.cpu.icache.overall_hits::total 1435 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 430 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 430 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 430 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 430 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 430 # number of overall misses -system.cpu.icache.overall_misses::total 430 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 33426000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 33426000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 33426000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 33426000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 33426000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 33426000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1865 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1865 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1865 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1865 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1865 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1865 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230563 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.230563 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.230563 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.230563 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.230563 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.230563 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77734.883721 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77734.883721 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77734.883721 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77734.883721 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77734.883721 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77734.883721 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 569 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 113.800000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 80 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 80 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 80 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28154000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 28154000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28154000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 28154000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28154000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 28154000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.187668 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.187668 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.187668 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.187668 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.187668 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.187668 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80440 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80440 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80440 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 80440 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80440 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 80440 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 232.210591 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 443 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.022573 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 166.990617 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 65.219974 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005096 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001990 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007087 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 443 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013519 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4083 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4083 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 8 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 10 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2 # number of overall hits -system.cpu.l2cache.overall_hits::total 10 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 342 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 342 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 56 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 56 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 342 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 103 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 445 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 342 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 103 # number of overall misses -system.cpu.l2cache.overall_misses::total 445 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4620500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4620500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27538000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 27538000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4709000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4709000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27538000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9329500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 36867500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27538000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9329500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 36867500 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 350 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 350 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 58 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 58 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 350 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 105 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 455 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 350 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 105 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 455 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.977143 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.977143 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.965517 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.965517 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.977143 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.980952 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.978022 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.977143 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.980952 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.978022 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98308.510638 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98308.510638 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80520.467836 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80520.467836 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84089.285714 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84089.285714 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80520.467836 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90577.669903 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82848.314607 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80520.467836 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90577.669903 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82848.314607 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 342 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 342 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 56 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 56 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 342 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 103 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 445 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 342 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 103 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4150500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4150500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24128000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24128000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4159000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4159000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24128000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8309500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 32437500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24128000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8309500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 32437500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.977143 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.977143 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.965517 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.965517 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.977143 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980952 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.978022 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.977143 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980952 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.978022 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88308.510638 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88308.510638 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70549.707602 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70549.707602 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74267.857143 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74267.857143 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70549.707602 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80674.757282 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72893.258427 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70549.707602 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.757282 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72893.258427 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 455 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 10 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 350 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 58 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 209 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 908 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 455 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.021978 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.146773 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 445 97.80% 97.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 10 2.20% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 455 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 227500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 523500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 156000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 444 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 396 # Transaction distribution -system.membus.trans_dist::ReadExReq 47 # Transaction distribution -system.membus.trans_dist::ReadExResp 47 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 397 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 887 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28352 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 444 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 444 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 444 # Request fanout histogram -system.membus.reqLayer0.occupancy 553000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2325750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.0 # Layer utilization (%) +sim_seconds 0.000021 +sim_ticks 21189000 +final_tick 21189000 +sim_freq 1000000000000 +host_inst_rate 70012 +host_op_rate 69995 +host_tick_rate 256014000 +host_mem_usage 260844 +host_seconds 0.08 +sim_insts 5792 +sim_ops 5792 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 21189000 +system.physmem.bytes_read::cpu.inst 21824 +system.physmem.bytes_read::cpu.data 6528 +system.physmem.bytes_read::total 28352 +system.physmem.bytes_inst_read::cpu.inst 21824 +system.physmem.bytes_inst_read::total 21824 +system.physmem.num_reads::cpu.inst 341 +system.physmem.num_reads::cpu.data 102 +system.physmem.num_reads::total 443 +system.physmem.bw_read::cpu.inst 1029968380 +system.physmem.bw_read::cpu.data 308084383 +system.physmem.bw_read::total 1338052763 +system.physmem.bw_inst_read::cpu.inst 1029968380 +system.physmem.bw_inst_read::total 1029968380 +system.physmem.bw_total::cpu.inst 1029968380 +system.physmem.bw_total::cpu.data 308084383 +system.physmem.bw_total::total 1338052763 +system.physmem.readReqs 444 +system.physmem.writeReqs 0 +system.physmem.readBursts 444 +system.physmem.writeBursts 0 +system.physmem.bytesReadDRAM 28416 +system.physmem.bytesReadWrQ 0 +system.physmem.bytesWritten 0 +system.physmem.bytesReadSys 28416 +system.physmem.bytesWrittenSys 0 +system.physmem.servicedByWrQ 0 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 71 +system.physmem.perBankRdBursts::1 42 +system.physmem.perBankRdBursts::2 55 +system.physmem.perBankRdBursts::3 58 +system.physmem.perBankRdBursts::4 53 +system.physmem.perBankRdBursts::5 61 +system.physmem.perBankRdBursts::6 52 +system.physmem.perBankRdBursts::7 10 +system.physmem.perBankRdBursts::8 9 +system.physmem.perBankRdBursts::9 28 +system.physmem.perBankRdBursts::10 1 +system.physmem.perBankRdBursts::11 0 +system.physmem.perBankRdBursts::12 0 +system.physmem.perBankRdBursts::13 0 +system.physmem.perBankRdBursts::14 4 +system.physmem.perBankRdBursts::15 0 +system.physmem.perBankWrBursts::0 0 +system.physmem.perBankWrBursts::1 0 +system.physmem.perBankWrBursts::2 0 +system.physmem.perBankWrBursts::3 0 +system.physmem.perBankWrBursts::4 0 +system.physmem.perBankWrBursts::5 0 +system.physmem.perBankWrBursts::6 0 +system.physmem.perBankWrBursts::7 0 +system.physmem.perBankWrBursts::8 0 +system.physmem.perBankWrBursts::9 0 +system.physmem.perBankWrBursts::10 0 +system.physmem.perBankWrBursts::11 0 +system.physmem.perBankWrBursts::12 0 +system.physmem.perBankWrBursts::13 0 +system.physmem.perBankWrBursts::14 0 +system.physmem.perBankWrBursts::15 0 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 21128500 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 444 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 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+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21189000 +system.cpu.toL2Bus.trans_dist::ReadResp 406 +system.cpu.toL2Bus.trans_dist::ReadExReq 47 +system.cpu.toL2Bus.trans_dist::ReadExResp 47 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 350 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 58 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 209 +system.cpu.toL2Bus.pkt_count::total 908 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6656 +system.cpu.toL2Bus.pkt_size::total 28992 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 455 +system.cpu.toL2Bus.snoop_fanout::mean 0.021978 +system.cpu.toL2Bus.snoop_fanout::stdev 0.146773 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 445 97.80% 97.80% +system.cpu.toL2Bus.snoop_fanout::1 10 2.20% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 455 +system.cpu.toL2Bus.reqLayer0.occupancy 227500 +system.cpu.toL2Bus.reqLayer0.utilization 1.1 +system.cpu.toL2Bus.respLayer0.occupancy 523500 +system.cpu.toL2Bus.respLayer0.utilization 2.5 +system.cpu.toL2Bus.respLayer1.occupancy 156000 +system.cpu.toL2Bus.respLayer1.utilization 0.7 +system.membus.snoop_filter.tot_requests 444 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 21189000 +system.membus.trans_dist::ReadResp 396 +system.membus.trans_dist::ReadExReq 47 +system.membus.trans_dist::ReadExResp 47 +system.membus.trans_dist::ReadSharedReq 397 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887 +system.membus.pkt_count::total 887 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28352 +system.membus.pkt_size::total 28352 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 444 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 444 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 444 +system.membus.reqLayer0.occupancy 553000 +system.membus.reqLayer0.utilization 2.6 +system.membus.respLayer1.occupancy 2325750 +system.membus.respLayer1.utilization 11.0 ---------- End Simulation Statistics ---------- |