diff options
author | Ali Saidi <saidi@eecs.umich.edu> | 2012-06-05 01:23:16 -0400 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2012-06-05 01:23:16 -0400 |
commit | c49e739352b6d6bd665c78c560602d0cff1e6a1a (patch) | |
tree | 5d32efd82f884376573604727d971a80458ed04a /tests/quick/se/00.hello/ref/power/linux/o3-timing | |
parent | e5f0d6016ba768c06b36d8b3d54f3ea700a4aa58 (diff) | |
download | gem5-c49e739352b6d6bd665c78c560602d0cff1e6a1a.tar.xz |
all: Update stats for memory per master and total fix.
Diffstat (limited to 'tests/quick/se/00.hello/ref/power/linux/o3-timing')
3 files changed, 69 insertions, 20 deletions
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini index b22bc0367..928f0469f 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini @@ -475,9 +475,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -508,9 +507,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index 7aac87cd9..b797dcfe3 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:03:54 -gem5 started May 8 2012 15:36:49 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:59:33 +gem5 started Jun 4 2012 14:44:10 +gem5 executing on zizzer command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 129f4d9d2..975867801 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000011 # Nu sim_ticks 11243500 # Number of ticks simulated final_tick 11243500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73653 # Simulator instruction rate (inst/s) -host_op_rate 73641 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 142731766 # Simulator tick rate (ticks/s) -host_mem_usage 211540 # Number of bytes of host memory used +host_inst_rate 72271 # Simulator instruction rate (inst/s) +host_op_rate 72256 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 140039967 # Simulator tick rate (ticks/s) +host_mem_usage 211876 # Number of bytes of host memory used host_seconds 0.08 # Real time elapsed on the host sim_insts 5800 # Number of instructions simulated sim_ops 5800 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 28736 # Number of bytes read from this memory -system.physmem.bytes_inst_read 22400 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 449 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2555787789 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1992262196 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2555787789 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 22400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 6336 # Number of bytes read from this memory +system.physmem.bytes_read::total 28736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 22400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 22400 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 350 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 99 # Number of read requests responded to by this memory +system.physmem.num_reads::total 449 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1992262196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 563525593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2555787789 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1992262196 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1992262196 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1992262196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 563525593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2555787789 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -339,11 +346,17 @@ system.cpu.icache.demand_accesses::total 1899 # nu system.cpu.icache.overall_accesses::cpu.inst 1899 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1899 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230121 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.230121 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.230121 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.230121 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.230121 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.230121 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36004.576659 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36004.576659 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36004.576659 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36004.576659 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -371,11 +384,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 12417500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12417500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 12417500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.186940 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.186940 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.186940 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34978.873239 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34978.873239 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 34978.873239 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 34978.873239 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 62.512522 # Cycle average of tags in use @@ -419,13 +438,21 @@ system.cpu.dcache.demand_accesses::total 2615 # nu system.cpu.dcache.overall_accesses::cpu.data 2615 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2615 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052900 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052900 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.302103 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.302103 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.152581 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.152581 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.152581 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.152581 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36060.240964 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36060.240964 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33504.746835 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33504.746835 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34036.340852 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34036.340852 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -459,13 +486,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 3570000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3570000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 3570000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032505 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032505 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.045889 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.045889 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037859 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.037859 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037859 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.037859 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35676.470588 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35676.470588 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36468.750000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36468.750000 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36060.606061 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36060.606061 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36060.606061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36060.606061 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 201.766772 # Cycle average of tags in use @@ -519,18 +554,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 99 system.cpu.l2cache.overall_accesses::total 454 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985915 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.987685 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985915 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.988987 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985915 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.988987 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34372.857143 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34529.411765 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34392.768080 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34895.833333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34895.833333 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34446.547884 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34446.547884 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -563,18 +606,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3121500 system.cpu.l2cache.overall_mshr_miss_latency::total 14026500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987685 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.988987 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.988987 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31157.142857 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31382.352941 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31185.785536 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31687.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31687.500000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31239.420935 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31239.420935 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |