summaryrefslogtreecommitdiff
path: root/tests/quick/se/00.hello/ref/power/linux/o3-timing
diff options
context:
space:
mode:
authorNilay Vaish <nilay@cs.wisc.edu>2013-01-24 12:29:00 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2013-01-24 12:29:00 -0600
commit9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b (patch)
tree64b85031cb791a21af6059778384d358d992b817 /tests/quick/se/00.hello/ref/power/linux/o3-timing
parentdbeabedaf0f8d9ec0ea3331db2e44b1add53f79f (diff)
downloadgem5-9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b.tar.xz
regressions: update stats due to branch predictor changes
The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
Diffstat (limited to 'tests/quick/se/00.hello/ref/power/linux/o3-timing')
-rw-r--r--tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini37
-rwxr-xr-xtests/quick/se/00.hello/ref/power/linux/o3-timing/simout8
-rw-r--r--tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt27
3 files changed, 40 insertions, 32 deletions
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
index ed3b8ffac..073ffb5b4 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
@@ -31,23 +31,19 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
UnifiedTLB=true
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
@@ -70,23 +66,15 @@ forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -98,7 +86,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -127,6 +114,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -491,7 +496,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/gem5/dist/test-progs/hello/bin/power/linux/hello
+executable=tests/test-progs/hello/bin/power/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
index 302c5d913..09e115be1 100755
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing/simout
+Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:14:12
-gem5 started Jan 4 2013 21:59:04
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 15:33:02
+gem5 started Jan 23 2013 15:33:08
+gem5 executing on ribera.cs.wisc.edu
command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
index 32c8057b9..2fa72cd37 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000014 # Nu
sim_ticks 14065500 # Number of ticks simulated
final_tick 14065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 28037 # Simulator instruction rate (inst/s)
-host_op_rate 28032 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 68062430 # Simulator tick rate (ticks/s)
-host_mem_usage 213288 # Number of bytes of host memory used
-host_seconds 0.21 # Real time elapsed on the host
+host_inst_rate 44313 # Simulator instruction rate (inst/s)
+host_op_rate 44306 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 107578636 # Simulator tick rate (ticks/s)
+host_mem_usage 267272 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
sim_insts 5792 # Number of instructions simulated
sim_ops 5792 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory
@@ -185,6 +185,15 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate 82.74 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 31295.96 # Average gap between requests
+system.cpu.branchPred.lookups 2247 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1810 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 1863 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 602 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 32.313473 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 198 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions.
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
@@ -207,14 +216,6 @@ system.cpu.workload.num_syscalls 9 # Nu
system.cpu.numCycles 28132 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2247 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 1810 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 419 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 1863 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 602 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 198 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 32 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 7398 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 13218 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2247 # Number of branches that fetch encountered