diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-08-15 10:38:05 -0400 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-08-15 10:38:05 -0400 |
| commit | 73e9e923d00c6f5df9e79a6c40ecc159894d2bc5 (patch) | |
| tree | f84188c6697fe79f0521b73d9d38855ce7e04d29 /tests/quick/se/00.hello/ref/power/linux | |
| parent | dd1b346584e520ba970e62aa3bcc7d32828cdeba (diff) | |
| download | gem5-73e9e923d00c6f5df9e79a6c40ecc159894d2bc5.tar.xz | |
stats: Update stats for syscall emulation Linux kernel changes.
Diffstat (limited to 'tests/quick/se/00.hello/ref/power/linux')
6 files changed, 511 insertions, 511 deletions
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini index fe01ee3c1..0b8702da2 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini @@ -513,7 +513,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index 4c16f50ba..4f1d93bdf 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:50:36 -gem5 started Jul 2 2012 11:29:39 +gem5 compiled Aug 13 2012 17:02:09 +gem5 started Aug 13 2012 18:12:24 gem5 executing on zizzer -command line: build/POWER/gem5.fast -d build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing +command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 11812000 because target called exit() +Exiting @ tick 11763500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 0b8cd16ea..a60091c97 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11812000 # Number of ticks simulated -final_tick 11812000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 11763500 # Number of ticks simulated +final_tick 11763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 59914 # Simulator instruction rate (inst/s) -host_op_rate 59903 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 121974515 # Simulator tick rate (ticks/s) -host_mem_usage 216016 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -sim_insts 5800 # Number of instructions simulated -sim_ops 5800 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 22528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 6400 # Number of bytes read from this memory +host_inst_rate 53396 # Simulator instruction rate (inst/s) +host_op_rate 53387 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 108411505 # Simulator tick rate (ticks/s) +host_mem_usage 219412 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host +sim_insts 5792 # Number of instructions simulated +sim_ops 5792 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 22464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory system.physmem.bytes_read::total 28928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 22528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 22528 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 352 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 100 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 22464 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 22464 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 351 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory system.physmem.num_reads::total 452 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1907213004 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 541821876 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2449034880 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1907213004 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1907213004 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1907213004 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 541821876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2449034880 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1909635738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 549496323 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2459132061 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1909635738 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1909635738 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1909635738 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 549496323 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2459132061 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,317 +46,317 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 23625 # number of cpu cycles simulated +system.cpu.numCycles 23528 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2490 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 2041 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 460 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2061 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 629 # Number of BTB hits +system.cpu.BPredUnit.lookups 2457 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 2014 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 452 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2037 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 618 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 162 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 160 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 30 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7441 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14561 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2490 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 791 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2421 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1432 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 932 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 7380 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14306 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2457 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 778 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2377 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1402 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 936 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1897 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 321 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11761 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.238075 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.668941 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1859 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 319 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11638 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.229249 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.662964 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9340 79.42% 79.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 172 1.46% 80.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 167 1.42% 82.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 146 1.24% 83.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 197 1.68% 85.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 155 1.32% 86.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 255 2.17% 88.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 108 0.92% 89.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1221 10.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9261 79.58% 79.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 173 1.49% 81.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 162 1.39% 82.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 137 1.18% 83.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 198 1.70% 85.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 148 1.27% 86.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 250 2.15% 88.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 106 0.91% 89.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1203 10.34% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11761 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.105397 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.616339 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7565 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1069 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2256 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 64 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 807 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 361 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12930 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 452 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 807 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7781 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 440 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 384 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2100 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 249 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12283 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 13 # Number of times rename has blocked due to IQ full +system.cpu.fetch.rateDist::total 11638 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.104429 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.608041 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7505 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1074 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2213 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 62 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 784 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 351 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 161 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12646 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 460 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 784 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7717 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 446 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 386 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2059 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 246 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11999 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 203 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10602 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 20025 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 19970 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 10316 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 19600 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 19545 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 5007 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5595 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 26 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 26 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 552 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2098 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1917 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 63 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 31 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11001 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 65 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9282 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4968 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4343 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11761 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.789219 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.523023 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5318 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 28 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 543 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2051 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1909 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 56 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10820 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 64 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9196 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 160 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4794 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4145 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 48 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 11638 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.790170 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.525459 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8303 70.60% 70.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1127 9.58% 80.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 767 6.52% 86.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 536 4.56% 91.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 478 4.06% 95.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 324 2.75% 98.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 139 1.18% 99.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 49 0.42% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 38 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8215 70.59% 70.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1109 9.53% 80.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 778 6.68% 86.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 515 4.43% 91.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 472 4.06% 95.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 322 2.77% 98.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 140 1.20% 99.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 48 0.41% 99.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 39 0.34% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11761 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11638 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5 2.87% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 78 44.83% 47.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 91 52.30% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4 2.34% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 75 43.86% 46.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 92 53.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5709 61.51% 61.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1861 20.05% 81.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1710 18.42% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5661 61.56% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1833 19.93% 81.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1700 18.49% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9282 # Type of FU issued -system.cpu.iq.rate 0.392889 # Inst issue rate -system.cpu.iq.fu_busy_cnt 174 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018746 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30604 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16005 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8374 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9196 # Type of FU issued +system.cpu.iq.rate 0.390853 # Inst issue rate +system.cpu.iq.fu_busy_cnt 171 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018595 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30299 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 15649 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8318 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9422 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9333 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 70 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1136 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1090 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 871 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 863 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 807 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 227 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11066 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2098 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1917 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 784 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 229 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10884 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 101 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2051 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1909 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 11 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 78 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 309 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 387 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8779 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1716 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 503 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 77 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 302 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 379 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8699 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1698 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 497 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3289 # number of memory reference insts executed -system.cpu.iew.exec_branches 1382 # Number of branches executed -system.cpu.iew.exec_stores 1573 # Number of stores executed -system.cpu.iew.exec_rate 0.371598 # Inst execution rate -system.cpu.iew.wb_sent 8575 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8401 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4358 # num instructions producing a value -system.cpu.iew.wb_consumers 6997 # num instructions consuming a value +system.cpu.iew.exec_refs 3253 # number of memory reference insts executed +system.cpu.iew.exec_branches 1376 # Number of branches executed +system.cpu.iew.exec_stores 1555 # Number of stores executed +system.cpu.iew.exec_rate 0.369730 # Inst execution rate +system.cpu.iew.wb_sent 8502 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8345 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4327 # num instructions producing a value +system.cpu.iew.wb_consumers 6939 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.355598 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.622838 # average fanout of values written-back +system.cpu.iew.wb_rate 0.354684 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.623577 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions -system.cpu.commit.commitCommittedOps 5800 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5275 # The number of squashed insts skipped by commit +system.cpu.commit.commitCommittedInsts 5792 # The number of committed instructions +system.cpu.commit.commitCommittedOps 5792 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 5101 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 301 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10954 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.529487 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.308345 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 292 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 10854 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.533628 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.316329 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8509 77.68% 77.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1052 9.60% 87.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 645 5.89% 93.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 263 2.40% 95.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 183 1.67% 97.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 104 0.95% 98.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 63 0.58% 98.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.37% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94 0.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8424 77.61% 77.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1042 9.60% 87.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 639 5.89% 93.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 261 2.40% 95.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 182 1.68% 97.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 104 0.96% 98.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 67 0.62% 98.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.38% 99.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94 0.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10954 # Number of insts commited each cycle -system.cpu.commit.committedInsts 5800 # Number of instructions committed -system.cpu.commit.committedOps 5800 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 10854 # Number of insts commited each cycle +system.cpu.commit.committedInsts 5792 # Number of instructions committed +system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 2008 # Number of memory references committed -system.cpu.commit.loads 962 # Number of loads committed +system.cpu.commit.refs 2007 # Number of memory references committed +system.cpu.commit.loads 961 # Number of loads committed system.cpu.commit.membars 7 # Number of memory barriers committed -system.cpu.commit.branches 1038 # Number of branches committed +system.cpu.commit.branches 1037 # Number of branches committed system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. -system.cpu.commit.int_insts 5706 # Number of committed integer instructions. +system.cpu.commit.int_insts 5698 # Number of committed integer instructions. system.cpu.commit.function_calls 103 # Number of function calls committed. system.cpu.commit.bw_lim_events 94 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21935 # The number of ROB reads -system.cpu.rob.rob_writes 22958 # The number of ROB writes -system.cpu.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11864 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 5800 # Number of Instructions Simulated -system.cpu.committedOps 5800 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 5800 # Number of Instructions Simulated -system.cpu.cpi 4.073276 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.073276 # CPI: Total CPI of All Threads -system.cpu.ipc 0.245503 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.245503 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13900 # number of integer regfile reads -system.cpu.int_regfile_writes 7266 # number of integer regfile writes +system.cpu.rob.rob_reads 21653 # The number of ROB reads +system.cpu.rob.rob_writes 22571 # The number of ROB writes +system.cpu.timesIdled 234 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11890 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 5792 # Number of Instructions Simulated +system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 5792 # Number of Instructions Simulated +system.cpu.cpi 4.062155 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.062155 # CPI: Total CPI of All Threads +system.cpu.ipc 0.246175 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.246175 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13809 # number of integer regfile reads +system.cpu.int_regfile_writes 7224 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 172.776641 # Cycle average of tags in use -system.cpu.icache.total_refs 1462 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 357 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.095238 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 172.502715 # Cycle average of tags in use +system.cpu.icache.total_refs 1427 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 356 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.008427 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 172.776641 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.084364 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.084364 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1462 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1462 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1462 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1462 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1462 # number of overall hits -system.cpu.icache.overall_hits::total 1462 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 435 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 435 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 435 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 435 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 435 # number of overall misses -system.cpu.icache.overall_misses::total 435 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16386000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16386000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16386000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16386000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16386000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16386000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1897 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1897 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1897 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1897 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1897 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1897 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229309 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.229309 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.229309 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.229309 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.229309 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.229309 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37668.965517 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 37668.965517 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 37668.965517 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 37668.965517 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 37668.965517 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 37668.965517 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 172.502715 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.084230 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.084230 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1427 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1427 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1427 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1427 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1427 # number of overall hits +system.cpu.icache.overall_hits::total 1427 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 432 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 432 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 432 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 432 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 432 # number of overall misses +system.cpu.icache.overall_misses::total 432 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16299000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16299000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16299000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16299000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16299000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16299000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1859 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1859 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1859 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1859 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1859 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1859 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.232383 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.232383 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.232383 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.232383 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.232383 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.232383 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37729.166667 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 37729.166667 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 37729.166667 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 37729.166667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 37729.166667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 37729.166667 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -365,94 +365,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 78 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 78 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 78 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 78 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 78 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 357 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 357 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 357 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 357 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 357 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 357 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13154500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13154500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13154500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13154500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13154500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13154500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188192 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188192 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188192 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.188192 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188192 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.188192 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36847.338936 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36847.338936 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36847.338936 # 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number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 356 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 356 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 356 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13111000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13111000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13111000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13111000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13111000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13111000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191501 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191501 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191501 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.191501 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191501 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.191501 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36828.651685 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36828.651685 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36828.651685 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36828.651685 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36828.651685 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36828.651685 # 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Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.015454 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1480 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1480 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 63.218136 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.015434 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.015434 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1479 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1479 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 717 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 717 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2197 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2197 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2197 # number of overall hits -system.cpu.dcache.overall_hits::total 2197 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 92 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 92 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2196 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2196 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2196 # number of overall hits +system.cpu.dcache.overall_hits::total 2196 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 91 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 91 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 329 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 329 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 421 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 421 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 421 # number of overall misses -system.cpu.dcache.overall_misses::total 421 # number of overall misses +system.cpu.dcache.demand_misses::cpu.data 420 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 420 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 420 # number of overall misses +system.cpu.dcache.overall_misses::total 420 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 3732500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 3732500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12822500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12822500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16555000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16555000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16555000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16555000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1572 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1572 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12824500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12824500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16557000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16557000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16557000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16557000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1570 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1570 # 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number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.057962 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.057962 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.314532 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.314532 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.160810 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.160810 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.160810 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.160810 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40570.652174 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40570.652174 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38974.164134 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38974.164134 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39323.040380 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39323.040380 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39323.040380 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39323.040380 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.160550 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.160550 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.160550 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.160550 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41016.483516 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41016.483516 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1882000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11613500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3824500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15438000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11613500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3824500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15438000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.989059 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.989059 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33106.534091 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35773.584906 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33455.555556 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40031.914894 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40031.914894 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33106.534091 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37775 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34139.380531 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33106.534091 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37775 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34139.380531 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33086.894587 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35972.222222 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33471.604938 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40042.553191 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40042.553191 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33086.894587 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37866.336634 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34154.867257 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33086.894587 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37866.336634 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34154.867257 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini index aaab5c18b..4d595ae50 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini @@ -100,8 +100,8 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] +width=8 +master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout index b409adbd2..0d5c52051 100755 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:59:33 -gem5 started Jun 4 2012 14:44:21 +gem5 compiled Aug 13 2012 17:02:09 +gem5 started Aug 13 2012 18:12:35 gem5 executing on zizzer command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 2900000 because target called exit() +Exiting @ tick 2896000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt index c355893c5..626b229db 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2900000 # Number of ticks simulated -final_tick 2900000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2896000 # Number of ticks simulated +final_tick 2896000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1223636 # Simulator instruction rate (inst/s) -host_op_rate 1219143 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 607261041 # Simulator tick rate (ticks/s) -host_mem_usage 202160 # Number of bytes of host memory used -host_seconds 0.00 # Real time elapsed on the host -sim_insts 5801 # Number of instructions simulated -sim_ops 5801 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 23204 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 3721 # Number of bytes read from this memory -system.physmem.bytes_read::total 26925 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 23204 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 23204 # Number of instructions bytes read from this memory +host_inst_rate 332855 # Simulator instruction rate (inst/s) +host_op_rate 332536 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 166086520 # Simulator tick rate (ticks/s) +host_mem_usage 209936 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +sim_insts 5793 # Number of instructions simulated +sim_ops 5793 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 23172 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 3720 # Number of bytes read from this memory +system.physmem.bytes_read::total 26892 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 23172 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 23172 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 4209 # Number of bytes written to this memory system.physmem.bytes_written::total 4209 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5801 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 962 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6763 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 5793 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 961 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6754 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 1046 # Number of write requests responded to by this memory system.physmem.num_writes::total 1046 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 8001379310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1283103448 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9284482759 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8001379310 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8001379310 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1451379310 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1451379310 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8001379310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2734482759 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10735862069 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 8001381215 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1284530387 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9285911602 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8001381215 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8001381215 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1453383978 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1453383978 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8001381215 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2737914365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10739295580 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -52,26 +52,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 5801 # number of cpu cycles simulated +system.cpu.numCycles 5793 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5801 # Number of instructions committed -system.cpu.committedOps 5801 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 5706 # Number of integer alu accesses +system.cpu.committedInsts 5793 # Number of instructions committed +system.cpu.committedOps 5793 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 5698 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 22 # Number of float alu accesses system.cpu.num_func_calls 200 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 896 # number of instructions that are conditional controls -system.cpu.num_int_insts 5706 # number of integer instructions +system.cpu.num_conditional_control_insts 895 # number of instructions that are conditional controls +system.cpu.num_int_insts 5698 # number of integer instructions system.cpu.num_fp_insts 22 # number of float instructions -system.cpu.num_int_register_reads 9541 # number of times the integer registers were read -system.cpu.num_int_register_writes 5005 # number of times the integer registers were written +system.cpu.num_int_register_reads 9529 # number of times the integer registers were read +system.cpu.num_int_register_writes 4996 # number of times the integer registers were written system.cpu.num_fp_register_reads 20 # number of times the floating registers were read system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2008 # number of memory refs -system.cpu.num_load_insts 962 # Number of load instructions +system.cpu.num_mem_refs 2007 # number of memory refs +system.cpu.num_load_insts 961 # Number of load instructions system.cpu.num_store_insts 1046 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5801 # Number of busy cycles +system.cpu.num_busy_cycles 5793 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles |