all: Update stats for memory per master and total fix.

7 files changed, 101 insertions, 40 deletions

diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
index b22bc0367..928f0469f 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
@@ -475,9 +475,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -508,9 +507,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
index 7aac87cd9..b797dcfe3 100755
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:03:54
-gem5 started May  8 2012 15:36:49
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:59:33
+gem5 started Jun  4 2012 14:44:10
+gem5 executing on zizzer
 command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
index 129f4d9d2..975867801 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds                                  0.000011                       # Nu
 sim_ticks                                    11243500                       # Number of ticks simulated
 final_tick                                   11243500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  73653                       # Simulator instruction rate (inst/s)
-host_op_rate                                    73641                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              142731766                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 211540                       # Number of bytes of host memory used
+host_inst_rate                                  72271                       # Simulator instruction rate (inst/s)
+host_op_rate                                    72256                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              140039967                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 211876                       # Number of bytes of host memory used
 host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        5800                       # Number of instructions simulated
 sim_ops                                          5800                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       28736                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  22400                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                          449                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                     2555787789                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                1992262196                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                    2555787789                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             22400                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              6336                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                28736                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        22400                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           22400                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                350                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                 99                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   449                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1992262196                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            563525593                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              2555787789                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1992262196                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1992262196                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1992262196                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           563525593                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2555787789                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -339,11 +346,17 @@ system.cpu.icache.demand_accesses::total         1899                       # nu
 system.cpu.icache.overall_accesses::cpu.inst         1899                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total         1899                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.230121                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.230121                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.230121                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.230121                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.230121                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.230121                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36004.576659                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 36004.576659                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 36004.576659                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 36004.576659                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 36004.576659                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 36004.576659                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -371,11 +384,17 @@ system.cpu.icache.demand_mshr_miss_latency::total     12417500
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst     12417500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total     12417500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.186940                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.186940                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.186940                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.186940                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.186940                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.186940                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34978.873239                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34978.873239                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34978.873239                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 34978.873239                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34978.873239                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 34978.873239                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 62.512522                       # Cycle average of tags in use
@@ -419,13 +438,21 @@ system.cpu.dcache.demand_accesses::total         2615                       # nu
 system.cpu.dcache.overall_accesses::cpu.data         2615                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total         2615                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.052900                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.052900                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.302103                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.302103                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.152581                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.152581                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.152581                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.152581                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36060.240964                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 36060.240964                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33504.746835                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 33504.746835                       # average WriteReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 34036.340852                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 34036.340852                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 34036.340852                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 34036.340852                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -459,13 +486,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total      3570000
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      3570000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      3570000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032505                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032505                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.045889                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.045889                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.037859                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.037859                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.037859                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.037859                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35676.470588                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35676.470588                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36468.750000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36468.750000                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36060.606061                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 36060.606061                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36060.606061                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 36060.606061                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               201.766772                       # Cycle average of tags in use
@@ -519,18 +554,26 @@ system.cpu.l2cache.overall_accesses::cpu.data           99
 system.cpu.l2cache.overall_accesses::total          454                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.985915                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.987685                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.985915                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.988987                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.985915                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.988987                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34372.857143                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34529.411765                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34392.768080                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34895.833333                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34895.833333                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34372.857143                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34707.070707                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34446.547884                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34372.857143                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34707.070707                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34446.547884                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -563,18 +606,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      3121500
 system.cpu.l2cache.overall_mshr_miss_latency::total     14026500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.985915                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.987685                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.985915                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.988987                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.985915                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.988987                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31157.142857                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31382.352941                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31185.785536                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31687.500000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31687.500000                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31157.142857                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31530.303030                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31239.420935                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31157.142857                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31530.303030                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31239.420935                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
index 0a48b581e..aaab5c18b 100644
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
@@ -95,9 +95,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr
index e45cd058f..7edd901b2 100755
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr
@@ -1,2 +1,3 @@
+warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout
index 4ba999389..b409adbd2 100755
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:03:54
-gem5 started May  8 2012 15:36:50
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:59:33
+gem5 started Jun  4 2012 14:44:21
+gem5 executing on zizzer
 command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
index 87b1b3e66..c355893c5 100644
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
@@ -4,23 +4,35 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2900000                       # Number of ticks simulated
 final_tick                                    2900000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 413372                       # Simulator instruction rate (inst/s)
-host_op_rate                                   412979                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              206267825                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 201744                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                1223636                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1219143                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              607261041                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 202160                       # Number of bytes of host memory used
+host_seconds                                     0.00                       # Real time elapsed on the host
 sim_insts                                        5801                       # Number of instructions simulated
 sim_ops                                          5801                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       26925                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  23204                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                     4209                       # Number of bytes written to this memory
-system.physmem.num_reads                         6763                       # Number of read requests responded to by this memory
-system.physmem.num_writes                        1046                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                     9284482759                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                8001379310                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                    1451379310                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                   10735862069                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             23204                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              3721                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                26925                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        23204                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           23204                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data           4209                       # Number of bytes written to this memory
+system.physmem.bytes_written::total              4209                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               5801                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                962                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  6763                       # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data              1046                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                 1046                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst           8001379310                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1283103448                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              9284482759                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      8001379310                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         8001379310                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1451379310                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1451379310                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          8001379310                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          2734482759                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            10735862069                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses