diff options
| author | Alec Roelke <ar4jc@virginia.edu> | 2017-05-31 18:49:18 -0400 |
|---|---|---|
| committer | Alec Roelke <ar4jc@virginia.edu> | 2017-06-05 19:40:58 +0000 |
| commit | 4966fe4b0f17ba30cba3d3dbae02b6452b87a70a (patch) | |
| tree | 4502bf4aec0d8bec718073e8dec6361ec0952994 /tests/quick/se/00.hello/ref/riscv | |
| parent | c1a7d318f670467612178ae5a7433f4c1f7361fa (diff) | |
| download | gem5-4966fe4b0f17ba30cba3d3dbae02b6452b87a70a.tar.xz | |
tests: Update RISC-V hello test and stats
Update the "Hello, world!" executable for RISC-V to use the latest GNU
Linux toolchain and fix the stats accordingly.
Change-Id: I5ff3d7f4bb41b10170038b8c07492f15bb54a022
Reviewed-on: https://gem5-review.googlesource.com/3560
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/quick/se/00.hello/ref/riscv')
25 files changed, 3281 insertions, 3134 deletions
diff --git a/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.ini index d51a8d121..9e9029829 100644 --- a/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.ini +++ b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.ini @@ -116,6 +116,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system threadPolicy=RoundRobin tracer=system.cpu.tracer @@ -745,7 +746,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -754,14 +755,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello +executable=/home/ar4jc/gem5/tests/testing/../test-progs/hello/bin/riscv/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.json b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.json index 0bb65c740..b6f25339a 100644 --- a/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.json +++ b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.json @@ -297,6 +297,7 @@ "max_loads_all_threads": 0, "executeMemoryIssueLimit": 1, "decodeCycleInput": true, + "syscallRetryLatency": 10000, "max_loads_any_thread": 0, "executeLSQTransfersQueueSize": 2, "p_state_clk_gate_max": 1000000000000, @@ -1058,21 +1059,22 @@ "uid": 100, "pid": 100, "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello", + "cxx_class": "Process", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/hello/bin/riscv/linux/hello", "drivers": [], "system": "system", "gid": 100, "eventq_index": 0, "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", "cwd": "", + "pgid": 100, "simpoint": 0, "euid": 100, + "input": "cin", "path": "system.cpu.workload", - "max_stack_size": 67108864, "name": "workload", "cmd": [ "hello" diff --git a/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simerr b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simerr index 85a6a33ad..c77d2a66d 100755 --- a/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simerr +++ b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simerr @@ -1,4 +1,7 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Unknown operating system; assuming Linux. warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings. + Returning '/home/ar4jc/gem5/tests/test-progs/hello/bin/riscv/linux/hello' +info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simout b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simout index 2251c9b4d..8395537d8 100755 --- a/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simout +++ b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simout @@ -1,15 +1,13 @@ -Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing/simout -Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing/simerr +Redirecting stdout to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/minor-timing/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/minor-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:28 -gem5 executing on zizzer, pid 34056 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/riscv/linux/minor-timing +gem5 compiled May 31 2017 18:33:59 +gem5 started May 31 2017 18:34:12 +gem5 executing on boldrock, pid 15707 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/minor-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/minor-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. Hello world! -Exiting @ tick 14435000 because target called exit() +Exiting @ tick 41515000 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/stats.txt index b9128db03..8966fba51 100644 --- a/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/stats.txt @@ -1,749 +1,769 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 14435000 # Number of ticks simulated -final_tick 14435000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 136295 # Simulator instruction rate (inst/s) -host_op_rate 136181 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1229999304 # Simulator tick rate (ticks/s) -host_mem_usage 249560 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 1597 # Number of instructions simulated -sim_ops 1597 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 9984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2048 # Number of bytes read from this memory -system.physmem.bytes_read::total 12032 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 9984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 9984 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 156 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 32 # Number of read requests responded to by this memory -system.physmem.num_reads::total 188 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 691652234 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 141877381 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 833529616 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 691652234 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 691652234 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 691652234 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 141877381 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 833529616 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 188 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 188 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12032 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12032 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 97 # Per bank write bursts -system.physmem.perBankRdBursts::1 64 # Per bank write bursts -system.physmem.perBankRdBursts::2 18 # Per bank write bursts -system.physmem.perBankRdBursts::3 9 # Per bank write bursts -system.physmem.perBankRdBursts::4 0 # Per bank write bursts -system.physmem.perBankRdBursts::5 0 # Per bank write bursts -system.physmem.perBankRdBursts::6 0 # Per bank write bursts -system.physmem.perBankRdBursts::7 0 # Per bank write bursts -system.physmem.perBankRdBursts::8 0 # Per bank write bursts -system.physmem.perBankRdBursts::9 0 # Per bank write bursts -system.physmem.perBankRdBursts::10 0 # Per bank write bursts -system.physmem.perBankRdBursts::11 0 # Per bank write bursts -system.physmem.perBankRdBursts::12 0 # Per bank write bursts -system.physmem.perBankRdBursts::13 0 # Per bank write bursts -system.physmem.perBankRdBursts::14 0 # Per bank write bursts -system.physmem.perBankRdBursts::15 0 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 14206000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 188 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 13 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 817.230769 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 665.111831 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 349.717542 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1 7.69% 7.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 1 7.69% 15.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1 7.69% 23.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 7.69% 30.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 69.23% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 13 # Bytes accessed per row activation -system.physmem.totQLat 1580250 # Total ticks spent queuing -system.physmem.totMemAccLat 5105250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 940000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8405.59 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27155.59 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 833.53 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 833.53 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.51 # Data bus utilization in percentage -system.physmem.busUtilRead 6.51 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 171 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.96 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 75563.83 # Average gap between requests -system.physmem.pageHitRate 90.96 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 121380 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 49335 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1342320 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2281140 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 17760 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 4279560 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 480 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 8706615 # Total energy per rank (pJ) -system.physmem_0.averagePower 603.160028 # Core power per rank (mW) -system.physmem_0.totalIdleTime 9188750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 18000 # Time in different power states -system.physmem_0.memoryStateTime::REF 260000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 1250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 4776000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 9379750 # Time in different power states -system.physmem_1.actEnergy 0 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 0 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 0 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 112290 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2995200 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 2453280 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 6175410 # Total energy per rank (pJ) -system.physmem_1.averagePower 427.808105 # Core power per rank (mW) -system.physmem_1.totalIdleTime 0 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 7786250 # Time in different power states -system.physmem_1.memoryStateTime::REF 260000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 6388750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 995 # Number of BP lookups -system.cpu.branchPred.condPredicted 543 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 229 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 944 # Number of BTB lookups -system.cpu.branchPred.BTBHits 100 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 10.593220 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 202 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 11 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 191 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 9 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 14435000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 28870 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1597 # Number of instructions committed -system.cpu.committedOps 1597 # Number of ops (including micro ops) committed -system.cpu.discardedOps 744 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 18.077646 # CPI: cycles per instruction -system.cpu.ipc 0.055317 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 9 0.56% 0.56% # Class of committed instruction -system.cpu.op_class_0::IntAlu 1019 63.81% 64.37% # Class of committed instruction -system.cpu.op_class_0::IntMult 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::FloatMult 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 64.37% # Class of committed instruction -system.cpu.op_class_0::MemRead 289 18.10% 82.47% # Class of committed instruction -system.cpu.op_class_0::MemWrite 280 17.53% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 1597 # Class of committed instruction -system.cpu.tickCycles 4106 # Number of cycles that the object actually ticked -system.cpu.idleCycles 24764 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 24.135470 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 645 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 33 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 19.545455 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 24.135470 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.005892 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.005892 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 33 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.008057 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1411 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1411 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 394 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 394 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 251 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 251 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 645 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 645 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 645 # number of overall hits -system.cpu.dcache.overall_hits::total 645 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 16 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 16 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 28 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 28 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 44 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 44 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 44 # number of overall misses -system.cpu.dcache.overall_misses::total 44 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1268000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1268000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2223500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2223500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 3491500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 3491500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 3491500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 3491500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 410 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 410 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 279 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 279 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 689 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 689 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 689 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 689 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.039024 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.100358 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.100358 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.063861 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.063861 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.063861 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.063861 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79250 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 79250 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79410.714286 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 79410.714286 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 79352.272727 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 79352.272727 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 79352.272727 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 79352.272727 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 11 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 11 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 16 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 16 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 17 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 17 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 33 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 33 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 33 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 33 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1252000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1252000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1342000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1342000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2594000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 2594000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2594000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 2594000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.060932 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.060932 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047896 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.047896 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047896 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.047896 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78250 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78250 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78941.176471 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78941.176471 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78606.060606 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78606.060606 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78606.060606 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78606.060606 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 79.926884 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 709 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 157 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.515924 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 79.926884 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.039027 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.039027 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 157 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 49 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.076660 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1889 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1889 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 709 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 709 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 709 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 709 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 709 # number of overall hits -system.cpu.icache.overall_hits::total 709 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 157 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 157 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 157 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 157 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 157 # number of overall misses -system.cpu.icache.overall_misses::total 157 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12560500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12560500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12560500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12560500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12560500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12560500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 866 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 866 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 866 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 866 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 866 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 866 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.181293 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.181293 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.181293 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.181293 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.181293 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.181293 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80003.184713 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 80003.184713 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 80003.184713 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 80003.184713 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 80003.184713 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 80003.184713 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 157 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 157 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 157 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 157 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 157 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 157 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12403500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12403500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12403500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12403500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12403500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12403500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.181293 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.181293 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.181293 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.181293 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.181293 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.181293 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79003.184713 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79003.184713 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79003.184713 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 79003.184713 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79003.184713 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 79003.184713 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 102.489649 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 188 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.010638 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.179084 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 23.310565 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002416 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000711 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003128 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.005737 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 1708 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 1708 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits -system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 17 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 17 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 156 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 156 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 15 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 15 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 156 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 32 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 188 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 156 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 32 # number of overall misses -system.cpu.l2cache.overall_misses::total 188 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1316500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1316500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 12156500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 12156500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1215500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1215500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12156500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2532000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 14688500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12156500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2532000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 14688500 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 17 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 17 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 157 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 157 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 16 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 16 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 157 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 33 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 190 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 157 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 33 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 190 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993631 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993631 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.937500 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.937500 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993631 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.969697 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.989474 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993631 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.969697 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.989474 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77441.176471 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77441.176471 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77926.282051 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77926.282051 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81033.333333 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81033.333333 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77926.282051 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79125 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78130.319149 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77926.282051 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79125 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78130.319149 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 17 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 17 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 156 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 156 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 15 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 15 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 156 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 32 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 156 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 32 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 188 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1146500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1146500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10596500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10596500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1065500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1065500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10596500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2212000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12808500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10596500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2212000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12808500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993631 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993631 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.937500 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.937500 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993631 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.969697 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.989474 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993631 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.969697 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.989474 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67441.176471 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67441.176471 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67926.282051 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67926.282051 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71033.333333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71033.333333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67926.282051 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69125 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68130.319149 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67926.282051 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69125 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68130.319149 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 190 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 173 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 157 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 16 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 314 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 66 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 380 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 12160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 190 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.010526 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.102326 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 188 98.95% 98.95% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2 1.05% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 190 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 95000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 235500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 49500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 188 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 171 # Transaction distribution -system.membus.trans_dist::ReadExReq 17 # Transaction distribution -system.membus.trans_dist::ReadExResp 17 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 171 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 376 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 376 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 12032 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 12032 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 188 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 188 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 188 # Request fanout histogram -system.membus.reqLayer0.occupancy 217500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 991750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.9 # Layer utilization (%) +sim_seconds 0.000042 +sim_ticks 41515000 +final_tick 41515000 +sim_freq 1000000000000 +host_inst_rate 25426 +host_op_rate 25461 +host_tick_rate 189862237 +host_mem_usage 277956 +host_seconds 0.22 +sim_insts 5559 +sim_ops 5567 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 41515000 +system.physmem.bytes_read::cpu.inst 25024 +system.physmem.bytes_read::cpu.data 9536 +system.physmem.bytes_read::total 34560 +system.physmem.bytes_inst_read::cpu.inst 25024 +system.physmem.bytes_inst_read::total 25024 +system.physmem.num_reads::cpu.inst 391 +system.physmem.num_reads::cpu.data 149 +system.physmem.num_reads::total 540 +system.physmem.bw_read::cpu.inst 602770083 +system.physmem.bw_read::cpu.data 229700108 +system.physmem.bw_read::total 832470191 +system.physmem.bw_inst_read::cpu.inst 602770083 +system.physmem.bw_inst_read::total 602770083 +system.physmem.bw_total::cpu.inst 602770083 +system.physmem.bw_total::cpu.data 229700108 +system.physmem.bw_total::total 832470191 +system.physmem.readReqs 540 +system.physmem.writeReqs 0 +system.physmem.readBursts 540 +system.physmem.writeBursts 0 +system.physmem.bytesReadDRAM 34560 +system.physmem.bytesReadWrQ 0 +system.physmem.bytesWritten 0 +system.physmem.bytesReadSys 34560 +system.physmem.bytesWrittenSys 0 +system.physmem.servicedByWrQ 0 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 57 +system.physmem.perBankRdBursts::1 85 +system.physmem.perBankRdBursts::2 52 +system.physmem.perBankRdBursts::3 47 +system.physmem.perBankRdBursts::4 31 +system.physmem.perBankRdBursts::5 36 +system.physmem.perBankRdBursts::6 45 +system.physmem.perBankRdBursts::7 20 +system.physmem.perBankRdBursts::8 32 +system.physmem.perBankRdBursts::9 24 +system.physmem.perBankRdBursts::10 22 +system.physmem.perBankRdBursts::11 18 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0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 540 +system.membus.reqLayer0.occupancy 612000 +system.membus.reqLayer0.utilization 1.5 +system.membus.respLayer1.occupancy 2866750 +system.membus.respLayer1.utilization 6.9 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.ini index 7fd46c549..7db51451f 100644 --- a/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.ini @@ -65,7 +65,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -139,6 +139,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -715,7 +716,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -724,14 +725,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello +executable=/home/ar4jc/gem5/tests/testing/../test-progs/hello/bin/riscv/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.json b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.json index 45f6dace0..b991129d3 100644 --- a/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.json +++ b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.json @@ -311,21 +311,22 @@ "uid": 100, "pid": 100, "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello", + "cxx_class": "Process", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/hello/bin/riscv/linux/hello", "drivers": [], "system": "system", "gid": 100, "eventq_index": 0, "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", "cwd": "", + "pgid": 100, "simpoint": 0, "euid": 100, + "input": "cin", "path": "system.cpu.workload", - "max_stack_size": 67108864, "name": "workload", "cmd": [ "hello" @@ -350,6 +351,7 @@ "decodeToFetchDelay": 1, "renameWidth": 8, "numThreads": 1, + "syscallRetryLatency": 10000, "squashWidth": 8, "function_trace": false, "backComSize": 5, @@ -968,6 +970,7 @@ "switched_out": false, "smtLSQPolicy": "Partitioned", "fetchBufferSize": 64, + "cacheStorePorts": 200, "simpoint_start_insts": [], "max_insts_any_thread": 0, "smtROBThreshold": 100, @@ -1077,7 +1080,6 @@ "issueWidth": 8, "LSQCheckLoads": true, "commitToRenameDelay": 1, - "cachePorts": 200, "system": "system", "checker": null, "numPhysFloatRegs": 256, diff --git a/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simerr index 85a6a33ad..c77d2a66d 100755 --- a/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simerr +++ b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simerr @@ -1,4 +1,7 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Unknown operating system; assuming Linux. warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings. + Returning '/home/ar4jc/gem5/tests/test-progs/hello/bin/riscv/linux/hello' +info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simout index d5153ce3d..f3010c283 100755 --- a/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simout @@ -1,15 +1,13 @@ -Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing/simout -Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing/simerr +Redirecting stdout to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/o3-timing/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:28 -gem5 executing on zizzer, pid 34057 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/riscv/linux/o3-timing +gem5 compiled May 31 2017 18:33:59 +gem5 started May 31 2017 18:34:13 +gem5 executing on boldrock, pid 15720 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. Hello world! -Exiting @ tick 7939500 because target called exit() +Exiting @ tick 21876000 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/stats.txt index c2fce2070..77f414f69 100644 --- a/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/stats.txt @@ -1,1000 +1,1029 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000008 # Number of seconds simulated -sim_ticks 7939500 # Number of ticks simulated -final_tick 7939500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81718 # Simulator instruction rate (inst/s) -host_op_rate 81674 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 408398393 # Simulator tick rate (ticks/s) -host_mem_usage 251348 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 1587 # Number of instructions simulated -sim_ops 1587 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 9600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2048 # Number of bytes read from this memory -system.physmem.bytes_read::total 11648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 9600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 9600 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 150 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 32 # Number of read requests responded to by this memory -system.physmem.num_reads::total 182 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1209144153 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 257950753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1467094905 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1209144153 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1209144153 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1209144153 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 257950753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1467094905 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 184 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 184 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11648 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11776 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 93 # Per bank write bursts -system.physmem.perBankRdBursts::1 62 # Per bank write bursts -system.physmem.perBankRdBursts::2 18 # Per bank write bursts -system.physmem.perBankRdBursts::3 9 # Per bank write bursts -system.physmem.perBankRdBursts::4 0 # Per bank write bursts -system.physmem.perBankRdBursts::5 0 # Per bank write bursts -system.physmem.perBankRdBursts::6 0 # Per bank write bursts -system.physmem.perBankRdBursts::7 0 # Per bank write bursts -system.physmem.perBankRdBursts::8 0 # Per bank write bursts -system.physmem.perBankRdBursts::9 0 # Per bank write bursts -system.physmem.perBankRdBursts::10 0 # Per bank write bursts -system.physmem.perBankRdBursts::11 0 # Per bank write bursts -system.physmem.perBankRdBursts::12 0 # Per bank write bursts -system.physmem.perBankRdBursts::13 0 # Per bank write bursts -system.physmem.perBankRdBursts::14 0 # Per bank write bursts -system.physmem.perBankRdBursts::15 0 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 7854500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 184 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 13 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 896 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 813.228460 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 265.169128 # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 1 7.69% 7.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1 7.69% 15.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 7.69% 23.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 7.69% 30.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 69.23% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 13 # Bytes accessed per row activation -system.physmem.totQLat 1405000 # Total ticks spent queuing -system.physmem.totMemAccLat 4817500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 910000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7635.87 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 4945.65 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26182.07 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1467.09 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1483.22 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.46 # Data bus utilization in percentage -system.physmem.busUtilRead 11.46 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.90 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 169 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.85 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42687.50 # Average gap between requests -system.physmem.pageHitRate 91.85 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 92820 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 49335 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1299480 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1581180 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 10080 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 2075940 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 5723475 # Total energy per rank (pJ) -system.physmem_0.averagePower 711.322044 # Core power per rank (mW) -system.physmem_0.totalIdleTime 4551000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states -system.physmem_0.memoryStateTime::REF 139500 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 3237500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 4551000 # Time in different power states -system.physmem_1.actEnergy 0 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 0 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 0 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 112290 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2989920 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 3716850 # Total energy per rank (pJ) -system.physmem_1.averagePower 462.726424 # Core power per rank (mW) -system.physmem_1.totalIdleTime 0 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 7786250 # Time in different power states -system.physmem_1.memoryStateTime::REF 153250 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 1255 # Number of BP lookups -system.cpu.branchPred.condPredicted 684 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 259 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1188 # Number of BTB lookups -system.cpu.branchPred.BTBHits 302 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 25.420875 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 254 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 24 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 230 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 67 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 9 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 7939500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 15880 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 3023 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 4974 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1255 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 326 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 964 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 540 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 803 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 191 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 4447 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.118507 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.504003 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 3513 79.00% 79.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 134 3.01% 82.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 87 1.96% 83.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 90 2.02% 85.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 45 1.01% 87.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 71 1.60% 88.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 65 1.46% 90.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 65 1.46% 91.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 377 8.48% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 4447 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.079030 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.313224 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 3139 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 350 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 756 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 185 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 287 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 86 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3866 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 255 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 185 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 3237 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 108 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 243 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 673 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3508 # Number of instructions processed by rename -system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full -system.cpu.rename.RenamedOperands 2456 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4500 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4500 # Number of integer rename lookups -system.cpu.rename.CommittedMaps 1077 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1379 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 16 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 16 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 82 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 547 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 471 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 3013 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 17 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2703 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1442 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 770 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 4447 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.607826 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.430977 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 3524 79.24% 79.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 251 5.64% 84.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 182 4.09% 88.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 180 4.05% 93.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 148 3.33% 96.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 66 1.48% 97.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 58 1.30% 99.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 26 0.58% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 12 0.27% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 4447 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4 5.71% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 30 42.86% 48.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 36 51.43% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 9 0.33% 0.33% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1765 65.30% 65.63% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.04% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 511 18.90% 84.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 417 15.43% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2703 # Type of FU issued -system.cpu.iq.rate 0.170214 # Inst issue rate -system.cpu.iq.fu_busy_cnt 70 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025897 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 9944 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4473 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2318 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2764 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 14 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 258 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 192 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 185 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 107 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3030 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 66 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 547 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 471 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 17 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 12 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 187 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 199 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2459 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 471 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 244 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 846 # number of memory reference insts executed -system.cpu.iew.exec_branches 566 # Number of branches executed -system.cpu.iew.exec_stores 375 # Number of stores executed -system.cpu.iew.exec_rate 0.154849 # Inst execution rate -system.cpu.iew.wb_sent 2369 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2318 # cumulative count of insts written-back -system.cpu.iew.wb_producers 798 # num instructions producing a value -system.cpu.iew.wb_consumers 1140 # num instructions consuming a value -system.cpu.iew.wb_rate 0.145970 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.700000 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 1446 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 174 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 4155 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.381949 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.175996 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 3563 85.75% 85.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 208 5.01% 90.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 142 3.42% 94.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86 2.07% 96.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 60 1.44% 97.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 35 0.84% 98.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 26 0.63% 99.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 14 0.34% 99.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 21 0.51% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 4155 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1587 # Number of instructions committed -system.cpu.commit.committedOps 1587 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 568 # Number of memory references committed -system.cpu.commit.loads 289 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 373 # Number of branches committed -system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1587 # Number of committed integer instructions. -system.cpu.commit.function_calls 142 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 1019 64.21% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.21% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 289 18.21% 82.42% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 279 17.58% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1587 # Class of committed instruction -system.cpu.commit.bw_lim_events 21 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 7050 # The number of ROB reads -system.cpu.rob.rob_writes 6361 # The number of ROB writes -system.cpu.timesIdled 96 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11433 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1587 # Number of Instructions Simulated -system.cpu.committedOps 1587 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 10.006301 # CPI: Cycles Per Instruction -system.cpu.cpi_total 10.006301 # CPI: Total CPI of All Threads -system.cpu.ipc 0.099937 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.099937 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3116 # number of integer regfile reads -system.cpu.int_regfile_writes 1668 # number of integer regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 24.179106 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 625 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 33 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 18.939394 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 24.179106 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.005903 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.005903 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 33 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.008057 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1495 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1495 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 431 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 431 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 194 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 194 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 625 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 625 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 625 # number of overall hits -system.cpu.dcache.overall_hits::total 625 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 21 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 21 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 106 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 106 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 106 # number of overall misses -system.cpu.dcache.overall_misses::total 106 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1305000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1305000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6101500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6101500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7406500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7406500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7406500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7406500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 452 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 452 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 279 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 279 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 731 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 731 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 731 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 731 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.046460 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.046460 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.304659 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.304659 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.145007 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.145007 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.145007 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.145007 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62142.857143 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62142.857143 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71782.352941 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 71782.352941 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69872.641509 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69872.641509 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69872.641509 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69872.641509 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 67 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 67 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 72 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 72 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 72 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 16 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 16 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 18 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 18 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 34 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 34 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 34 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 34 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1141000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1141000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1431500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1431500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2572500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 2572500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2572500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 2572500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035398 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035398 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.064516 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.064516 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.046512 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.046512 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046512 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.046512 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71312.500000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71312.500000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79527.777778 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79527.777778 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75661.764706 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75661.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75661.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75661.764706 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 76.387250 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 579 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 151 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.834437 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 76.387250 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.037298 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.037298 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 151 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.073730 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1753 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1753 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 579 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 579 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 579 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 579 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 579 # number of overall hits -system.cpu.icache.overall_hits::total 579 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 222 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 222 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 222 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 222 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 222 # number of overall misses -system.cpu.icache.overall_misses::total 222 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16076000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16076000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16076000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16076000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16076000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16076000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 801 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 801 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 801 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 801 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 801 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 801 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.277154 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.277154 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.277154 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.277154 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.277154 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.277154 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72414.414414 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72414.414414 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72414.414414 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72414.414414 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72414.414414 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72414.414414 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 447 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 89.400000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 153 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 153 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 153 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 153 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 153 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 153 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11858500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11858500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11858500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11858500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11858500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11858500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191011 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191011 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191011 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.191011 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191011 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.191011 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77506.535948 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77506.535948 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77506.535948 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 77506.535948 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77506.535948 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 77506.535948 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 99.069725 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 182 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.010989 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 75.716364 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 23.353361 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002311 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000713 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003023 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 182 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.005554 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 1678 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 1678 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits -system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 18 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 18 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 152 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 152 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 15 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 15 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 152 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 33 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 185 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 152 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 33 # number of overall misses -system.cpu.l2cache.overall_misses::total 185 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1404500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1404500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11620000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 11620000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1106000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1106000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11620000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2510500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 14130500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11620000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2510500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 14130500 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 18 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 18 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 153 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 153 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 16 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 16 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 153 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 34 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 187 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 153 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 34 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 187 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993464 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993464 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.937500 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.937500 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993464 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.970588 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.989305 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993464 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.970588 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.989305 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78027.777778 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78027.777778 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76447.368421 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76447.368421 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73733.333333 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73733.333333 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76447.368421 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76075.757576 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76381.081081 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76447.368421 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76075.757576 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76381.081081 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 18 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 18 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 152 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 152 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 15 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 15 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 152 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 33 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 185 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 152 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 33 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 185 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1224500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1224500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10120000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10120000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 966000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 966000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2190500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12310500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2190500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12310500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993464 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993464 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.937500 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.937500 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993464 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.970588 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.989305 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993464 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.970588 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.989305 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68027.777778 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68027.777778 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66578.947368 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66578.947368 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64400 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64400 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66578.947368 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66378.787879 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66543.243243 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66578.947368 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66378.787879 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66543.243243 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 187 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 166 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 18 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 18 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 153 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 16 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 304 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 67 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 371 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 11776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 187 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.010695 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103139 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 185 98.93% 98.93% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2 1.07% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 187 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 93500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 226500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 49500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 184 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 164 # Transaction distribution -system.membus.trans_dist::ReadExReq 18 # Transaction distribution -system.membus.trans_dist::ReadExResp 18 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 166 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 366 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 366 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 11648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 11648 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 184 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 184 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 184 # Request fanout histogram -system.membus.reqLayer0.occupancy 228500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 948750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.9 # Layer utilization (%) +sim_seconds 0.000022 +sim_ticks 21876000 +final_tick 21876000 +sim_freq 1000000000000 +host_inst_rate 17054 +host_op_rate 17078 +host_tick_rate 67215440 +host_mem_usage 279228 +host_seconds 0.33 +sim_insts 5550 +sim_ops 5558 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 21876000 +system.physmem.bytes_read::cpu.inst 25344 +system.physmem.bytes_read::cpu.data 9856 +system.physmem.bytes_read::total 35200 +system.physmem.bytes_inst_read::cpu.inst 25344 +system.physmem.bytes_inst_read::total 25344 +system.physmem.num_reads::cpu.inst 396 +system.physmem.num_reads::cpu.data 154 +system.physmem.num_reads::total 550 +system.physmem.bw_read::cpu.inst 1158529896 +system.physmem.bw_read::cpu.data 450539404 +system.physmem.bw_read::total 1609069300 +system.physmem.bw_inst_read::cpu.inst 1158529896 +system.physmem.bw_inst_read::total 1158529896 +system.physmem.bw_total::cpu.inst 1158529896 +system.physmem.bw_total::cpu.data 450539404 +system.physmem.bw_total::total 1609069300 +system.physmem.readReqs 550 +system.physmem.writeReqs 0 +system.physmem.readBursts 550 +system.physmem.writeBursts 0 +system.physmem.bytesReadDRAM 35200 +system.physmem.bytesReadWrQ 0 +system.physmem.bytesWritten 0 +system.physmem.bytesReadSys 35200 +system.physmem.bytesWrittenSys 0 +system.physmem.servicedByWrQ 0 +system.physmem.mergedWrBursts 0 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73261.964736 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78559.210526 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78559.210526 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73261.964736 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75819.354839 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73980.072464 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73261.964736 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75819.354839 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73980.072464 +system.cpu.toL2Bus.snoop_filter.tot_requests 554 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21876000 +system.cpu.toL2Bus.trans_dist::ReadResp 473 +system.cpu.toL2Bus.trans_dist::ReadExReq 79 +system.cpu.toL2Bus.trans_dist::ReadExResp 79 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 399 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 76 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 797 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309 +system.cpu.toL2Bus.pkt_count::total 1106 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 25472 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9856 +system.cpu.toL2Bus.pkt_size::total 35328 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 554 +system.cpu.toL2Bus.snoop_fanout::mean 0.003610 +system.cpu.toL2Bus.snoop_fanout::stdev 0.060030 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 552 99.64% 99.64% +system.cpu.toL2Bus.snoop_fanout::1 2 0.36% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 554 +system.cpu.toL2Bus.reqLayer0.occupancy 277000 +system.cpu.toL2Bus.reqLayer0.utilization 1.3 +system.cpu.toL2Bus.respLayer0.occupancy 597000 +system.cpu.toL2Bus.respLayer0.utilization 2.7 +system.cpu.toL2Bus.respLayer1.occupancy 231000 +system.cpu.toL2Bus.respLayer1.utilization 1.1 +system.membus.snoop_filter.tot_requests 550 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 21876000 +system.membus.trans_dist::ReadResp 471 +system.membus.trans_dist::ReadExReq 79 +system.membus.trans_dist::ReadExResp 79 +system.membus.trans_dist::ReadSharedReq 471 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1100 +system.membus.pkt_count::total 1100 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 35200 +system.membus.pkt_size::total 35200 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 550 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 550 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 550 +system.membus.reqLayer0.occupancy 681000 +system.membus.reqLayer0.utilization 3.1 +system.membus.respLayer1.occupancy 2898500 +system.membus.respLayer1.utilization 13.2 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.ini index 76abe1457..17c63eb76 100644 --- a/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.ini @@ -88,6 +88,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -118,7 +119,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -127,14 +128,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello +executable=/home/ar4jc/gem5/tests/testing/../test-progs/hello/bin/riscv/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.json b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.json index 663d5cd98..e5010bfd2 100644 --- a/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.json +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.json @@ -192,6 +192,7 @@ }, "p_state_clk_gate_bins": 20, "p_state_clk_gate_min": 1000, + "syscallRetryLatency": 10000, "interrupts": [ { "eventq_index": 0, @@ -216,21 +217,22 @@ "uid": 100, "pid": 100, "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello", + "cxx_class": "Process", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/hello/bin/riscv/linux/hello", "drivers": [], "system": "system", "gid": 100, "eventq_index": 0, "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", "cwd": "", + "pgid": 100, "simpoint": 0, "euid": 100, + "input": "cin", "path": "system.cpu.workload", - "max_stack_size": 67108864, "name": "workload", "cmd": [ "hello" diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simerr index fd133b12b..5df892149 100755 --- a/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simerr @@ -1,3 +1,6 @@ -warn: Unknown operating system; assuming Linux. warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings. + Returning '/home/ar4jc/gem5/tests/test-progs/hello/bin/riscv/linux/hello' +info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simout index 0253c62ea..17a216564 100755 --- a/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simout @@ -1,15 +1,13 @@ -Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-atomic/simout -Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-atomic/simerr +Redirecting stdout to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-atomic/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:29 -gem5 executing on zizzer, pid 34058 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-atomic +gem5 compiled May 31 2017 18:33:59 +gem5 started May 31 2017 18:34:14 +gem5 executing on boldrock, pid 15724 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. Hello world! -Exiting @ tick 798000 because target called exit() +Exiting @ tick 2783000 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/stats.txt index 48d9a0fbb..1a0fce77a 100644 --- a/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/stats.txt @@ -1,153 +1,156 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 798000 # Number of ticks simulated -final_tick 798000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49942 # Simulator instruction rate (inst/s) -host_op_rate 49911 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25081647 # Simulator tick rate (ticks/s) -host_mem_usage 221640 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -sim_insts 1587 # Number of instructions simulated -sim_ops 1587 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 798000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 6388 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1816 # Number of bytes read from this memory -system.physmem.bytes_read::total 8204 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 6388 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6388 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 1750 # Number of bytes written to this memory -system.physmem.bytes_written::total 1750 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1597 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1886 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 279 # Number of write requests responded to by this memory -system.physmem.num_writes::total 279 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 8005012531 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2275689223 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10280701754 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8005012531 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8005012531 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 2192982456 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2192982456 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8005012531 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4468671679 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12473684211 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 798000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 9 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 798000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1597 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1587 # Number of instructions committed -system.cpu.committedOps 1587 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1588 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 142 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 231 # number of instructions that are conditional controls -system.cpu.num_int_insts 1588 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 2062 # number of times the integer registers were read -system.cpu.num_int_register_writes 1077 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 569 # number of memory refs -system.cpu.num_load_insts 289 # Number of load instructions -system.cpu.num_store_insts 280 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1597 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 373 # Number of branches fetched -system.cpu.op_class::No_OpClass 9 0.56% 0.56% # Class of executed instruction -system.cpu.op_class::IntAlu 1019 63.81% 64.37% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::MemRead 289 18.10% 82.47% # Class of executed instruction -system.cpu.op_class::MemWrite 280 17.53% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1597 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 798000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 1886 # Transaction distribution -system.membus.trans_dist::ReadResp 1886 # Transaction distribution -system.membus.trans_dist::WriteReq 279 # Transaction distribution -system.membus.trans_dist::WriteResp 279 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3194 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1136 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4330 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6388 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3566 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 9954 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2165 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2165 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2165 # Request fanout histogram +sim_seconds 0.000003 +sim_ticks 2783000 +final_tick 2783000 +sim_freq 1000000000000 +host_inst_rate 86590 +host_op_rate 86699 +host_tick_rate 43405073 +host_mem_usage 264628 +host_seconds 0.06 +sim_insts 5550 +sim_ops 5558 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 2783000 +system.physmem.bytes_read::cpu.inst 22236 +system.physmem.bytes_read::cpu.data 7346 +system.physmem.bytes_read::total 29582 +system.physmem.bytes_inst_read::cpu.inst 22236 +system.physmem.bytes_inst_read::total 22236 +system.physmem.bytes_written::cpu.data 8138 +system.physmem.bytes_written::total 8138 +system.physmem.num_reads::cpu.inst 5559 +system.physmem.num_reads::cpu.data 1101 +system.physmem.num_reads::total 6660 +system.physmem.num_writes::cpu.data 1097 +system.physmem.num_writes::total 1097 +system.physmem.bw_read::cpu.inst 7989938915 +system.physmem.bw_read::cpu.data 2639597557 +system.physmem.bw_read::total 10629536471 +system.physmem.bw_inst_read::cpu.inst 7989938915 +system.physmem.bw_inst_read::total 7989938915 +system.physmem.bw_write::cpu.data 2924182537 +system.physmem.bw_write::total 2924182537 +system.physmem.bw_total::cpu.inst 7989938915 +system.physmem.bw_total::cpu.data 5563780093 +system.physmem.bw_total::total 13553719008 +system.pwrStateResidencyTicks::UNDEFINED 2783000 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 9 +system.cpu.pwrStateResidencyTicks::ON 2783000 +system.cpu.numCycles 5567 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5550 +system.cpu.committedOps 5558 +system.cpu.num_int_alu_accesses 5557 +system.cpu.num_fp_alu_accesses 12 +system.cpu.num_func_calls 291 +system.cpu.num_conditional_control_insts 914 +system.cpu.num_int_insts 5557 +system.cpu.num_fp_insts 12 +system.cpu.num_int_register_reads 7540 +system.cpu.num_int_register_writes 3562 +system.cpu.num_fp_register_reads 12 +system.cpu.num_fp_register_writes 0 +system.cpu.num_mem_refs 2198 +system.cpu.num_load_insts 1101 +system.cpu.num_store_insts 1097 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 5567 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1205 +system.cpu.op_class::No_OpClass 10 0.18% 0.18% +system.cpu.op_class::IntAlu 3353 60.23% 60.41% +system.cpu.op_class::IntMult 2 0.04% 60.45% +system.cpu.op_class::IntDiv 4 0.07% 60.52% +system.cpu.op_class::FloatAdd 0 0.00% 60.52% +system.cpu.op_class::FloatCmp 0 0.00% 60.52% +system.cpu.op_class::FloatCvt 0 0.00% 60.52% +system.cpu.op_class::FloatMult 0 0.00% 60.52% +system.cpu.op_class::FloatMultAcc 0 0.00% 60.52% +system.cpu.op_class::FloatDiv 0 0.00% 60.52% +system.cpu.op_class::FloatMisc 0 0.00% 60.52% +system.cpu.op_class::FloatSqrt 0 0.00% 60.52% +system.cpu.op_class::SimdAdd 0 0.00% 60.52% +system.cpu.op_class::SimdAddAcc 0 0.00% 60.52% +system.cpu.op_class::SimdAlu 0 0.00% 60.52% +system.cpu.op_class::SimdCmp 0 0.00% 60.52% +system.cpu.op_class::SimdCvt 0 0.00% 60.52% +system.cpu.op_class::SimdMisc 0 0.00% 60.52% +system.cpu.op_class::SimdMult 0 0.00% 60.52% +system.cpu.op_class::SimdMultAcc 0 0.00% 60.52% +system.cpu.op_class::SimdShift 0 0.00% 60.52% +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.52% +system.cpu.op_class::SimdSqrt 0 0.00% 60.52% +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.52% +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.52% +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.52% +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.52% +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.52% +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.52% +system.cpu.op_class::SimdFloatMult 0 0.00% 60.52% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.52% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.52% +system.cpu.op_class::MemRead 1101 19.78% 80.29% +system.cpu.op_class::MemWrite 1085 19.49% 99.78% +system.cpu.op_class::FloatMemRead 0 0.00% 99.78% +system.cpu.op_class::FloatMemWrite 12 0.22% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 5567 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 2783000 +system.membus.trans_dist::ReadReq 6652 +system.membus.trans_dist::ReadResp 6660 +system.membus.trans_dist::WriteReq 1089 +system.membus.trans_dist::WriteResp 1089 +system.membus.trans_dist::LoadLockedReq 8 +system.membus.trans_dist::StoreCondReq 8 +system.membus.trans_dist::StoreCondResp 8 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11118 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4396 +system.membus.pkt_count::total 15514 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 22236 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 15484 +system.membus.pkt_size::total 37720 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 7757 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 7757 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 7757 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.ini index 9d9106168..b0e4765ad 100644 --- a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.ini @@ -85,6 +85,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -122,7 +123,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -131,14 +132,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello +executable=/home/ar4jc/gem5/tests/testing/../test-progs/hello/bin/riscv/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -297,6 +299,7 @@ type=RubyDirectoryMemory eventq_index=0 numa_high_bit=5 size=268435456 +system=system version=0 [system.ruby.dir_cntrl0.dmaRequestToDir] diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.json b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.json index 331c89064..8542eb386 100644 --- a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.json +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.json @@ -1487,6 +1487,7 @@ "p_state_clk_gate_bins": 20, "directory": { "name": "directory", + "system": "system", "version": 0, "eventq_index": 0, "cxx_class": "DirectoryMemory", @@ -1548,6 +1549,7 @@ }, "p_state_clk_gate_bins": 20, "p_state_clk_gate_min": 1, + "syscallRetryLatency": 10000, "interrupts": [ { "eventq_index": 0, @@ -1572,21 +1574,22 @@ "uid": 100, "pid": 100, "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello", + "cxx_class": "Process", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/hello/bin/riscv/linux/hello", "drivers": [], "system": "system", "gid": 100, "eventq_index": 0, "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", "cwd": "", + "pgid": 100, "simpoint": 0, "euid": 100, + "input": "cin", "path": "system.cpu.workload", - "max_stack_size": 67108864, "name": "workload", "cmd": [ "hello" diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simerr index 63b14556f..fc05b7c0f 100755 --- a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simerr @@ -4,8 +4,13 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Unknown operating system; assuming Linux. warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! +warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings. + Returning '/home/ar4jc/gem5/tests/test-progs/hello/bin/riscv/linux/hello' +info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simout index a4d87ef7e..454318786 100755 --- a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simout @@ -1,15 +1,13 @@ -Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby/simout -Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby/simerr +Redirecting stdout to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing-ruby/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing-ruby/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:29 -gem5 executing on zizzer, pid 34060 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-timing-ruby +gem5 compiled May 31 2017 18:33:59 +gem5 started May 31 2017 18:34:14 +gem5 executing on boldrock, pid 15732 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. Hello world! -Exiting @ tick 27947 because target called exit() +Exiting @ tick 99780 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/stats.txt index f5db85554..5b9765473 100644 --- a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/stats.txt @@ -1,612 +1,652 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 27947 # Number of ticks simulated -final_tick 27947 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 89967 # Simulator instruction rate (inst/s) -host_op_rate 89916 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1582597 # Simulator tick rate (ticks/s) -host_mem_usage 409032 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 1587 # Number of instructions simulated -sim_ops 1587 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 28032 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 28032 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 27776 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 27776 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 438 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 438 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 434 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 434 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 1003041471 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 1003041471 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 993881275 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 993881275 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1996922747 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1996922747 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 438 # Number of read requests accepted -system.mem_ctrls.writeReqs 434 # Number of write requests accepted -system.mem_ctrls.readBursts 438 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 434 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 15616 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 12416 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 14912 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 28032 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 27776 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 194 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 183 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 102 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 69 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 43 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 30 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 100 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 62 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 41 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 30 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 27875 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 438 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 434 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 244 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 12 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 14 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 15 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 15 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 16 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 14 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 14 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 14 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 14 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 14 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 14 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 14 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 14 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 14 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 14 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 14 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 35 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 835.657143 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 690.201292 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 331.080756 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 2 5.71% 5.71% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 2 5.71% 11.43% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 1 2.86% 14.29% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 1 2.86% 17.14% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 1 2.86% 20.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 3 8.57% 28.57% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 25 71.43% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 35 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 14 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 17.285714 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 16.736288 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 5.580579 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 1 7.14% 7.14% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 4 28.57% 35.71% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 7 50.00% 85.71% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 1 7.14% 92.86% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::36-37 1 7.14% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 14 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 14 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.642857 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.611629 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.081818 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 10 71.43% 71.43% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 3 21.43% 92.86% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 1 7.14% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 14 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 2979 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 7615 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 1220 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 12.21 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 31.21 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 558.77 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 533.58 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 1003.04 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 993.88 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 8.53 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.37 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 4.17 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 24.44 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 212 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 228 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 86.89 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 90.84 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 31.97 # Average gap between requests -system.mem_ctrls.pageHitRate 88.89 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 264180 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 135240 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 2787456 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 1946016 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 4405872 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 40704 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 8149176 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 118272 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 19690836 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 704.577808 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 18179 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 22 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 780 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 308 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 8966 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 17871 # Time in different power states -system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 224352 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 3002880 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 2889984 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 2906160 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 10252656 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 366.860701 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 7526 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 526 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 12109 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 7526 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 9 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 27947 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 27947 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1587 # Number of instructions committed -system.cpu.committedOps 1587 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1588 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 142 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 231 # number of instructions that are conditional controls -system.cpu.num_int_insts 1588 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 2062 # number of times the integer registers were read -system.cpu.num_int_register_writes 1077 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 569 # number of memory refs -system.cpu.num_load_insts 289 # Number of load instructions -system.cpu.num_store_insts 280 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 27947 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 373 # Number of branches fetched -system.cpu.op_class::No_OpClass 9 0.56% 0.56% # Class of executed instruction -system.cpu.op_class::IntAlu 1019 63.81% 64.37% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::MemRead 289 18.10% 82.47% # Class of executed instruction -system.cpu.op_class::MemWrite 280 17.53% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1597 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 872 # delay histogram for all message -system.ruby.delayHist | 872 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 872 # delay histogram for all message +sim_seconds 0.000100 +sim_ticks 99780 +final_tick 99780 +sim_freq 1000000000 +host_inst_rate 16142 +host_op_rate 16165 +host_tick_rate 290191 +host_mem_usage 441524 +host_seconds 0.34 +sim_insts 5550 +sim_ops 5558 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1 +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 99780 +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 94784 +system.mem_ctrls.bytes_read::total 94784 +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 94528 +system.mem_ctrls.bytes_written::total 94528 +system.mem_ctrls.num_reads::ruby.dir_cntrl0 1481 +system.mem_ctrls.num_reads::total 1481 +system.mem_ctrls.num_writes::ruby.dir_cntrl0 1477 +system.mem_ctrls.num_writes::total 1477 +system.mem_ctrls.bw_read::ruby.dir_cntrl0 949929846 +system.mem_ctrls.bw_read::total 949929846 +system.mem_ctrls.bw_write::ruby.dir_cntrl0 947364201 +system.mem_ctrls.bw_write::total 947364201 +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1897294047 +system.mem_ctrls.bw_total::total 1897294047 +system.mem_ctrls.readReqs 1481 +system.mem_ctrls.writeReqs 1477 +system.mem_ctrls.readBursts 1481 +system.mem_ctrls.writeBursts 1477 +system.mem_ctrls.bytesReadDRAM 53056 +system.mem_ctrls.bytesReadWrQ 41728 +system.mem_ctrls.bytesWritten 53760 +system.mem_ctrls.bytesReadSys 94784 +system.mem_ctrls.bytesWrittenSys 94528 +system.mem_ctrls.servicedByWrQ 652 +system.mem_ctrls.mergedWrBursts 618 +system.mem_ctrls.neitherReadNorWriteReqs 0 +system.mem_ctrls.perBankRdBursts::0 66 +system.mem_ctrls.perBankRdBursts::1 132 +system.mem_ctrls.perBankRdBursts::2 108 +system.mem_ctrls.perBankRdBursts::3 130 +system.mem_ctrls.perBankRdBursts::4 52 +system.mem_ctrls.perBankRdBursts::5 42 +system.mem_ctrls.perBankRdBursts::6 42 +system.mem_ctrls.perBankRdBursts::7 14 +system.mem_ctrls.perBankRdBursts::8 89 +system.mem_ctrls.perBankRdBursts::9 41 +system.mem_ctrls.perBankRdBursts::10 34 +system.mem_ctrls.perBankRdBursts::11 13 +system.mem_ctrls.perBankRdBursts::12 46 +system.mem_ctrls.perBankRdBursts::13 3 +system.mem_ctrls.perBankRdBursts::14 8 +system.mem_ctrls.perBankRdBursts::15 9 +system.mem_ctrls.perBankWrBursts::0 64 +system.mem_ctrls.perBankWrBursts::1 142 +system.mem_ctrls.perBankWrBursts::2 106 +system.mem_ctrls.perBankWrBursts::3 136 +system.mem_ctrls.perBankWrBursts::4 53 +system.mem_ctrls.perBankWrBursts::5 44 +system.mem_ctrls.perBankWrBursts::6 38 +system.mem_ctrls.perBankWrBursts::7 14 +system.mem_ctrls.perBankWrBursts::8 91 +system.mem_ctrls.perBankWrBursts::9 41 +system.mem_ctrls.perBankWrBursts::10 34 +system.mem_ctrls.perBankWrBursts::11 11 +system.mem_ctrls.perBankWrBursts::12 47 +system.mem_ctrls.perBankWrBursts::13 3 +system.mem_ctrls.perBankWrBursts::14 7 +system.mem_ctrls.perBankWrBursts::15 9 +system.mem_ctrls.numRdRetry 0 +system.mem_ctrls.numWrRetry 0 +system.mem_ctrls.totGap 99716 +system.mem_ctrls.readPktSize::0 0 +system.mem_ctrls.readPktSize::1 0 +system.mem_ctrls.readPktSize::2 0 +system.mem_ctrls.readPktSize::3 0 +system.mem_ctrls.readPktSize::4 0 +system.mem_ctrls.readPktSize::5 0 +system.mem_ctrls.readPktSize::6 1481 +system.mem_ctrls.writePktSize::0 0 +system.mem_ctrls.writePktSize::1 0 +system.mem_ctrls.writePktSize::2 0 +system.mem_ctrls.writePktSize::3 0 +system.mem_ctrls.writePktSize::4 0 +system.mem_ctrls.writePktSize::5 0 +system.mem_ctrls.writePktSize::6 1477 +system.mem_ctrls.rdQLenPdf::0 829 +system.mem_ctrls.rdQLenPdf::1 0 +system.mem_ctrls.rdQLenPdf::2 0 +system.mem_ctrls.rdQLenPdf::3 0 +system.mem_ctrls.rdQLenPdf::4 0 +system.mem_ctrls.rdQLenPdf::5 0 +system.mem_ctrls.rdQLenPdf::6 0 +system.mem_ctrls.rdQLenPdf::7 0 +system.mem_ctrls.rdQLenPdf::8 0 +system.mem_ctrls.rdQLenPdf::9 0 +system.mem_ctrls.rdQLenPdf::10 0 +system.mem_ctrls.rdQLenPdf::11 0 +system.mem_ctrls.rdQLenPdf::12 0 +system.mem_ctrls.rdQLenPdf::13 0 +system.mem_ctrls.rdQLenPdf::14 0 +system.mem_ctrls.rdQLenPdf::15 0 +system.mem_ctrls.rdQLenPdf::16 0 +system.mem_ctrls.rdQLenPdf::17 0 +system.mem_ctrls.rdQLenPdf::18 0 +system.mem_ctrls.rdQLenPdf::19 0 +system.mem_ctrls.rdQLenPdf::20 0 +system.mem_ctrls.rdQLenPdf::21 0 +system.mem_ctrls.rdQLenPdf::22 0 +system.mem_ctrls.rdQLenPdf::23 0 +system.mem_ctrls.rdQLenPdf::24 0 +system.mem_ctrls.rdQLenPdf::25 0 +system.mem_ctrls.rdQLenPdf::26 0 +system.mem_ctrls.rdQLenPdf::27 0 +system.mem_ctrls.rdQLenPdf::28 0 +system.mem_ctrls.rdQLenPdf::29 0 +system.mem_ctrls.rdQLenPdf::30 0 +system.mem_ctrls.rdQLenPdf::31 0 +system.mem_ctrls.wrQLenPdf::0 1 +system.mem_ctrls.wrQLenPdf::1 1 +system.mem_ctrls.wrQLenPdf::2 1 +system.mem_ctrls.wrQLenPdf::3 1 +system.mem_ctrls.wrQLenPdf::4 1 +system.mem_ctrls.wrQLenPdf::5 1 +system.mem_ctrls.wrQLenPdf::6 1 +system.mem_ctrls.wrQLenPdf::7 1 +system.mem_ctrls.wrQLenPdf::8 1 +system.mem_ctrls.wrQLenPdf::9 1 +system.mem_ctrls.wrQLenPdf::10 1 +system.mem_ctrls.wrQLenPdf::11 1 +system.mem_ctrls.wrQLenPdf::12 1 +system.mem_ctrls.wrQLenPdf::13 1 +system.mem_ctrls.wrQLenPdf::14 1 +system.mem_ctrls.wrQLenPdf::15 9 +system.mem_ctrls.wrQLenPdf::16 9 +system.mem_ctrls.wrQLenPdf::17 45 +system.mem_ctrls.wrQLenPdf::18 55 +system.mem_ctrls.wrQLenPdf::19 53 +system.mem_ctrls.wrQLenPdf::20 54 +system.mem_ctrls.wrQLenPdf::21 57 +system.mem_ctrls.wrQLenPdf::22 51 +system.mem_ctrls.wrQLenPdf::23 51 +system.mem_ctrls.wrQLenPdf::24 51 +system.mem_ctrls.wrQLenPdf::25 51 +system.mem_ctrls.wrQLenPdf::26 51 +system.mem_ctrls.wrQLenPdf::27 51 +system.mem_ctrls.wrQLenPdf::28 51 +system.mem_ctrls.wrQLenPdf::29 51 +system.mem_ctrls.wrQLenPdf::30 51 +system.mem_ctrls.wrQLenPdf::31 51 +system.mem_ctrls.wrQLenPdf::32 51 +system.mem_ctrls.wrQLenPdf::33 1 +system.mem_ctrls.wrQLenPdf::34 0 +system.mem_ctrls.wrQLenPdf::35 0 +system.mem_ctrls.wrQLenPdf::36 0 +system.mem_ctrls.wrQLenPdf::37 0 +system.mem_ctrls.wrQLenPdf::38 0 +system.mem_ctrls.wrQLenPdf::39 0 +system.mem_ctrls.wrQLenPdf::40 0 +system.mem_ctrls.wrQLenPdf::41 0 +system.mem_ctrls.wrQLenPdf::42 0 +system.mem_ctrls.wrQLenPdf::43 0 +system.mem_ctrls.wrQLenPdf::44 0 +system.mem_ctrls.wrQLenPdf::45 0 +system.mem_ctrls.wrQLenPdf::46 0 +system.mem_ctrls.wrQLenPdf::47 0 +system.mem_ctrls.wrQLenPdf::48 0 +system.mem_ctrls.wrQLenPdf::49 0 +system.mem_ctrls.wrQLenPdf::50 0 +system.mem_ctrls.wrQLenPdf::51 0 +system.mem_ctrls.wrQLenPdf::52 0 +system.mem_ctrls.wrQLenPdf::53 0 +system.mem_ctrls.wrQLenPdf::54 0 +system.mem_ctrls.wrQLenPdf::55 0 +system.mem_ctrls.wrQLenPdf::56 0 +system.mem_ctrls.wrQLenPdf::57 0 +system.mem_ctrls.wrQLenPdf::58 0 +system.mem_ctrls.wrQLenPdf::59 0 +system.mem_ctrls.wrQLenPdf::60 0 +system.mem_ctrls.wrQLenPdf::61 0 +system.mem_ctrls.wrQLenPdf::62 0 +system.mem_ctrls.wrQLenPdf::63 0 +system.mem_ctrls.bytesPerActivate::samples 272 +system.mem_ctrls.bytesPerActivate::mean 387.764706 +system.mem_ctrls.bytesPerActivate::gmean 254.750753 +system.mem_ctrls.bytesPerActivate::stdev 333.100037 +system.mem_ctrls.bytesPerActivate::0-127 58 21.32% 21.32% +system.mem_ctrls.bytesPerActivate::128-255 65 23.90% 45.22% +system.mem_ctrls.bytesPerActivate::256-383 37 13.60% 58.82% +system.mem_ctrls.bytesPerActivate::384-511 29 10.66% 69.49% +system.mem_ctrls.bytesPerActivate::512-639 16 5.88% 75.37% +system.mem_ctrls.bytesPerActivate::640-767 14 5.15% 80.51% +system.mem_ctrls.bytesPerActivate::768-895 8 2.94% 83.46% +system.mem_ctrls.bytesPerActivate::896-1023 9 3.31% 86.76% +system.mem_ctrls.bytesPerActivate::1024-1151 36 13.24% 100.00% +system.mem_ctrls.bytesPerActivate::total 272 +system.mem_ctrls.rdPerTurnAround::samples 51 +system.mem_ctrls.rdPerTurnAround::mean 16.196078 +system.mem_ctrls.rdPerTurnAround::gmean 16.040148 +system.mem_ctrls.rdPerTurnAround::stdev 2.785818 +system.mem_ctrls.rdPerTurnAround::14-15 22 43.14% 43.14% +system.mem_ctrls.rdPerTurnAround::16-17 24 47.06% 90.20% +system.mem_ctrls.rdPerTurnAround::18-19 3 5.88% 96.08% +system.mem_ctrls.rdPerTurnAround::20-21 1 1.96% 98.04% +system.mem_ctrls.rdPerTurnAround::34-35 1 1.96% 100.00% +system.mem_ctrls.rdPerTurnAround::total 51 +system.mem_ctrls.wrPerTurnAround::samples 51 +system.mem_ctrls.wrPerTurnAround::mean 16.470588 +system.mem_ctrls.wrPerTurnAround::gmean 16.444515 +system.mem_ctrls.wrPerTurnAround::stdev 0.966498 +system.mem_ctrls.wrPerTurnAround::16 40 78.43% 78.43% +system.mem_ctrls.wrPerTurnAround::17 2 3.92% 82.35% +system.mem_ctrls.wrPerTurnAround::18 5 9.80% 92.16% +system.mem_ctrls.wrPerTurnAround::19 4 7.84% 100.00% +system.mem_ctrls.wrPerTurnAround::total 51 +system.mem_ctrls.totQLat 14330 +system.mem_ctrls.totMemAccLat 30081 +system.mem_ctrls.totBusLat 4145 +system.mem_ctrls.avgQLat 17.29 +system.mem_ctrls.avgBusLat 5.00 +system.mem_ctrls.avgMemAccLat 36.29 +system.mem_ctrls.avgRdBW 531.73 +system.mem_ctrls.avgWrBW 538.79 +system.mem_ctrls.avgRdBWSys 949.93 +system.mem_ctrls.avgWrBWSys 947.36 +system.mem_ctrls.peakBW 12800.00 +system.mem_ctrls.busUtil 8.36 +system.mem_ctrls.busUtilRead 4.15 +system.mem_ctrls.busUtilWrite 4.21 +system.mem_ctrls.avgRdQLen 1.00 +system.mem_ctrls.avgWrQLen 25.90 +system.mem_ctrls.readRowHits 615 +system.mem_ctrls.writeRowHits 776 +system.mem_ctrls.readRowHitRate 74.19 +system.mem_ctrls.writeRowHitRate 90.34 +system.mem_ctrls.avgGap 33.71 +system.mem_ctrls.pageHitRate 82.41 +system.mem_ctrls_0.actEnergy 1428000 +system.mem_ctrls_0.preEnergy 757344 +system.mem_ctrls_0.readEnergy 6694464 +system.mem_ctrls_0.writeEnergy 4986144 +system.mem_ctrls_0.refreshEnergy 7375680.000000 +system.mem_ctrls_0.actBackEnergy 13031112 +system.mem_ctrls_0.preBackEnergy 158208 +system.mem_ctrls_0.actPowerDownEnergy 30190392 +system.mem_ctrls_0.prePowerDownEnergy 1760256 +system.mem_ctrls_0.selfRefreshEnergy 0 +system.mem_ctrls_0.totalEnergy 66381600 +system.mem_ctrls_0.averagePower 665.279615 +system.mem_ctrls_0.totalIdleTime 70610 +system.mem_ctrls_0.memoryStateTime::IDLE 58 +system.mem_ctrls_0.memoryStateTime::REF 3120 +system.mem_ctrls_0.memoryStateTime::SREF 0 +system.mem_ctrls_0.memoryStateTime::PRE_PDN 4584 +system.mem_ctrls_0.memoryStateTime::ACT 25811 +system.mem_ctrls_0.memoryStateTime::ACT_PDN 66207 +system.mem_ctrls_1.actEnergy 556920 +system.mem_ctrls_1.preEnergy 293664 +system.mem_ctrls_1.readEnergy 2776032 +system.mem_ctrls_1.writeEnergy 2029536 +system.mem_ctrls_1.refreshEnergy 7375680.000000 +system.mem_ctrls_1.actBackEnergy 10879248 +system.mem_ctrls_1.preBackEnergy 520320 +system.mem_ctrls_1.actPowerDownEnergy 23776752 +system.mem_ctrls_1.prePowerDownEnergy 8611200 +system.mem_ctrls_1.selfRefreshEnergy 0 +system.mem_ctrls_1.totalEnergy 56819352 +system.mem_ctrls_1.averagePower 569.446302 +system.mem_ctrls_1.totalIdleTime 74538 +system.mem_ctrls_1.memoryStateTime::IDLE 1005 +system.mem_ctrls_1.memoryStateTime::REF 3120 +system.mem_ctrls_1.memoryStateTime::SREF 0 +system.mem_ctrls_1.memoryStateTime::PRE_PDN 22425 +system.mem_ctrls_1.memoryStateTime::ACT 21088 +system.mem_ctrls_1.memoryStateTime::ACT_PDN 52142 +system.pwrStateResidencyTicks::UNDEFINED 99780 +system.cpu.clk_domain.clock 1 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 9 +system.cpu.pwrStateResidencyTicks::ON 99780 +system.cpu.numCycles 99780 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5550 +system.cpu.committedOps 5558 +system.cpu.num_int_alu_accesses 5557 +system.cpu.num_fp_alu_accesses 12 +system.cpu.num_func_calls 291 +system.cpu.num_conditional_control_insts 914 +system.cpu.num_int_insts 5557 +system.cpu.num_fp_insts 12 +system.cpu.num_int_register_reads 7540 +system.cpu.num_int_register_writes 3562 +system.cpu.num_fp_register_reads 12 +system.cpu.num_fp_register_writes 0 +system.cpu.num_mem_refs 2198 +system.cpu.num_load_insts 1101 +system.cpu.num_store_insts 1097 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 99780 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1205 +system.cpu.op_class::No_OpClass 10 0.18% 0.18% +system.cpu.op_class::IntAlu 3353 60.23% 60.41% +system.cpu.op_class::IntMult 2 0.04% 60.45% +system.cpu.op_class::IntDiv 4 0.07% 60.52% +system.cpu.op_class::FloatAdd 0 0.00% 60.52% +system.cpu.op_class::FloatCmp 0 0.00% 60.52% +system.cpu.op_class::FloatCvt 0 0.00% 60.52% +system.cpu.op_class::FloatMult 0 0.00% 60.52% +system.cpu.op_class::FloatMultAcc 0 0.00% 60.52% +system.cpu.op_class::FloatDiv 0 0.00% 60.52% +system.cpu.op_class::FloatMisc 0 0.00% 60.52% +system.cpu.op_class::FloatSqrt 0 0.00% 60.52% +system.cpu.op_class::SimdAdd 0 0.00% 60.52% +system.cpu.op_class::SimdAddAcc 0 0.00% 60.52% +system.cpu.op_class::SimdAlu 0 0.00% 60.52% +system.cpu.op_class::SimdCmp 0 0.00% 60.52% +system.cpu.op_class::SimdCvt 0 0.00% 60.52% +system.cpu.op_class::SimdMisc 0 0.00% 60.52% +system.cpu.op_class::SimdMult 0 0.00% 60.52% +system.cpu.op_class::SimdMultAcc 0 0.00% 60.52% +system.cpu.op_class::SimdShift 0 0.00% 60.52% +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.52% +system.cpu.op_class::SimdSqrt 0 0.00% 60.52% +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.52% +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.52% +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.52% +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.52% +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.52% +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.52% +system.cpu.op_class::SimdFloatMult 0 0.00% 60.52% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.52% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.52% +system.cpu.op_class::MemRead 1101 19.78% 80.29% +system.cpu.op_class::MemWrite 1085 19.49% 99.78% +system.cpu.op_class::FloatMemRead 0 0.00% 99.78% +system.cpu.op_class::FloatMemWrite 12 0.22% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 5567 +system.ruby.clk_domain.clock 1 +system.ruby.pwrStateResidencyTicks::UNDEFINED 99780 +system.ruby.delayHist::bucket_size 1 +system.ruby.delayHist::max_bucket 9 +system.ruby.delayHist::samples 2958 +system.ruby.delayHist | 2958 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayHist::total 2958 system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 2166 +system.ruby.outstanding_req_hist_seqr::samples 7758 system.ruby.outstanding_req_hist_seqr::mean 1 system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 2166 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 2166 -system.ruby.latency_hist_seqr::bucket_size 32 -system.ruby.latency_hist_seqr::max_bucket 319 -system.ruby.latency_hist_seqr::samples 2165 -system.ruby.latency_hist_seqr::mean 11.908545 -system.ruby.latency_hist_seqr::gmean 2.205817 -system.ruby.latency_hist_seqr::stdev 24.908130 -system.ruby.latency_hist_seqr | 1727 79.77% 79.77% | 202 9.33% 89.10% | 224 10.35% 99.45% | 2 0.09% 99.54% | 2 0.09% 99.63% | 7 0.32% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 1 0.05% 100.00% -system.ruby.latency_hist_seqr::total 2165 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 7758 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 7758 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 7757 +system.ruby.latency_hist_seqr::mean 11.863220 +system.ruby.latency_hist_seqr::gmean 2.122296 +system.ruby.latency_hist_seqr::stdev 26.774000 +system.ruby.latency_hist_seqr | 6955 89.66% 89.66% | 754 9.72% 99.38% | 36 0.46% 99.85% | 2 0.03% 99.87% | 7 0.09% 99.96% | 3 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 7757 system.ruby.hit_latency_hist_seqr::bucket_size 1 system.ruby.hit_latency_hist_seqr::max_bucket 9 -system.ruby.hit_latency_hist_seqr::samples 1727 +system.ruby.hit_latency_hist_seqr::samples 6276 system.ruby.hit_latency_hist_seqr::mean 1 system.ruby.hit_latency_hist_seqr::gmean 1 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 1727 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 1727 -system.ruby.miss_latency_hist_seqr::bucket_size 32 -system.ruby.miss_latency_hist_seqr::max_bucket 319 -system.ruby.miss_latency_hist_seqr::samples 438 -system.ruby.miss_latency_hist_seqr::mean 54.920091 -system.ruby.miss_latency_hist_seqr::gmean 49.915756 -system.ruby.miss_latency_hist_seqr::stdev 27.345330 -system.ruby.miss_latency_hist_seqr | 0 0.00% 0.00% | 202 46.12% 46.12% | 224 51.14% 97.26% | 2 0.46% 97.72% | 2 0.46% 98.17% | 7 1.60% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 1 0.23% 100.00% -system.ruby.miss_latency_hist_seqr::total 438 -system.ruby.Directory.incomplete_times_seqr 437 -system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.015529 # Average number of messages in buffer -system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.986546 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.031201 # Average number of messages in buffer -system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.686704 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.015672 # Average number of messages in buffer -system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.997531 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.031201 # Average number of messages in buffer -system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.997567 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.cacheMemory.demand_hits 1727 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 438 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 2165 # Number of cache demand accesses -system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.015529 # Average number of messages in buffer -system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.904322 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.077501 # Average number of messages in buffer -system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999964 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.062402 # Average number of messages in buffer -system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999785 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.015672 # Average number of messages in buffer -system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.981215 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.015529 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers03.avg_stall_time 5.918205 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.015672 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers04.avg_stall_time 5.984113 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.093316 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers07.avg_stall_time 6.689566 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 7.800479 -system.ruby.network.routers0.msg_count.Control::2 438 -system.ruby.network.routers0.msg_count.Data::2 434 -system.ruby.network.routers0.msg_count.Response_Data::4 438 -system.ruby.network.routers0.msg_count.Writeback_Control::3 434 -system.ruby.network.routers0.msg_bytes.Control::2 3504 -system.ruby.network.routers0.msg_bytes.Data::2 31248 -system.ruby.network.routers0.msg_bytes.Response_Data::4 31536 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 3472 -system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.031201 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers02.avg_stall_time 10.687419 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.015529 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers06.avg_stall_time 1.973021 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.015672 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers07.avg_stall_time 1.994991 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 7.800479 -system.ruby.network.routers1.msg_count.Control::2 438 -system.ruby.network.routers1.msg_count.Data::2 434 -system.ruby.network.routers1.msg_count.Response_Data::4 438 -system.ruby.network.routers1.msg_count.Writeback_Control::3 434 -system.ruby.network.routers1.msg_bytes.Control::2 3504 -system.ruby.network.routers1.msg_bytes.Data::2 31248 -system.ruby.network.routers1.msg_bytes.Response_Data::4 31536 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 3472 -system.ruby.network.int_link_buffers02.avg_buf_msgs 0.031201 # Average number of messages in buffer -system.ruby.network.int_link_buffers02.avg_stall_time 7.689137 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers08.avg_buf_msgs 0.015529 # Average number of messages in buffer -system.ruby.network.int_link_buffers08.avg_stall_time 2.959425 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers09.avg_buf_msgs 0.015672 # Average number of messages in buffer -system.ruby.network.int_link_buffers09.avg_stall_time 2.992379 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers13.avg_buf_msgs 0.015529 # Average number of messages in buffer -system.ruby.network.int_link_buffers13.avg_stall_time 4.932017 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers14.avg_buf_msgs 0.015672 # Average number of messages in buffer -system.ruby.network.int_link_buffers14.avg_stall_time 4.986940 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers17.avg_buf_msgs 0.031201 # Average number of messages in buffer -system.ruby.network.int_link_buffers17.avg_stall_time 9.688064 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.015529 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers03.avg_stall_time 3.945756 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.015672 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers04.avg_stall_time 3.989695 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.031201 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers07.avg_stall_time 8.688636 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 7.800479 -system.ruby.network.routers2.msg_count.Control::2 438 -system.ruby.network.routers2.msg_count.Data::2 434 -system.ruby.network.routers2.msg_count.Response_Data::4 438 -system.ruby.network.routers2.msg_count.Writeback_Control::3 434 -system.ruby.network.routers2.msg_bytes.Control::2 3504 -system.ruby.network.routers2.msg_bytes.Data::2 31248 -system.ruby.network.routers2.msg_bytes.Response_Data::4 31536 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 3472 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Control 1314 -system.ruby.network.msg_count.Data 1302 -system.ruby.network.msg_count.Response_Data 1314 -system.ruby.network.msg_count.Writeback_Control 1302 -system.ruby.network.msg_byte.Control 10512 -system.ruby.network.msg_byte.Data 93744 -system.ruby.network.msg_byte.Response_Data 94608 -system.ruby.network.msg_byte.Writeback_Control 10416 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 7.829105 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 438 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 434 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 31536 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 3472 -system.ruby.network.routers0.throttle1.link_utilization 7.771854 -system.ruby.network.routers0.throttle1.msg_count.Control::2 438 -system.ruby.network.routers0.throttle1.msg_count.Data::2 434 -system.ruby.network.routers0.throttle1.msg_bytes.Control::2 3504 -system.ruby.network.routers0.throttle1.msg_bytes.Data::2 31248 -system.ruby.network.routers1.throttle0.link_utilization 7.771854 -system.ruby.network.routers1.throttle0.msg_count.Control::2 438 -system.ruby.network.routers1.throttle0.msg_count.Data::2 434 -system.ruby.network.routers1.throttle0.msg_bytes.Control::2 3504 -system.ruby.network.routers1.throttle0.msg_bytes.Data::2 31248 -system.ruby.network.routers1.throttle1.link_utilization 7.829105 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 438 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 434 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 31536 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 3472 -system.ruby.network.routers2.throttle0.link_utilization 7.829105 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 438 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 434 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 31536 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 3472 -system.ruby.network.routers2.throttle1.link_utilization 7.771854 -system.ruby.network.routers2.throttle1.msg_count.Control::2 438 -system.ruby.network.routers2.throttle1.msg_count.Data::2 434 -system.ruby.network.routers2.throttle1.msg_bytes.Control::2 3504 -system.ruby.network.routers2.throttle1.msg_bytes.Data::2 31248 -system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 438 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 438 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 438 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 434 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 434 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 434 # delay histogram for vnet_2 -system.ruby.LD.latency_hist_seqr::bucket_size 32 -system.ruby.LD.latency_hist_seqr::max_bucket 319 -system.ruby.LD.latency_hist_seqr::samples 289 -system.ruby.LD.latency_hist_seqr::mean 23.332180 -system.ruby.LD.latency_hist_seqr::gmean 5.457216 -system.ruby.LD.latency_hist_seqr::stdev 32.553168 -system.ruby.LD.latency_hist_seqr | 161 55.71% 55.71% | 72 24.91% 80.62% | 54 18.69% 99.31% | 0 0.00% 99.31% | 0 0.00% 99.31% | 1 0.35% 99.65% | 0 0.00% 99.65% | 0 0.00% 99.65% | 0 0.00% 99.65% | 1 0.35% 100.00% -system.ruby.LD.latency_hist_seqr::total 289 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6276 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 6276 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 1481 +system.ruby.miss_latency_hist_seqr::mean 57.898042 +system.ruby.miss_latency_hist_seqr::gmean 51.487789 +system.ruby.miss_latency_hist_seqr::stdev 33.698741 +system.ruby.miss_latency_hist_seqr | 679 45.85% 45.85% | 754 50.91% 96.76% | 36 2.43% 99.19% | 2 0.14% 99.32% | 7 0.47% 99.80% | 3 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 1481 +system.ruby.Directory.incomplete_times_seqr 1480 +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.014802 +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.996613 +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.029645 +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.749411 +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.014843 +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999308 +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029645 +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999319 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 99780 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 6276 +system.ruby.l1_cntrl0.cacheMemory.demand_misses 1481 +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7757 +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.014802 +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.975867 +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.077750 +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999990 +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.059290 +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999940 +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.014843 +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.994738 +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 99780 +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 99780 +system.ruby.memctrl_clk_domain.clock 3 +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.014802 +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.979375 +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.014843 +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.995550 +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.088855 +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.750213 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 99780 +system.ruby.network.routers0.percent_links_utilized 7.410553 +system.ruby.network.routers0.msg_count.Control::2 1481 +system.ruby.network.routers0.msg_count.Data::2 1477 +system.ruby.network.routers0.msg_count.Response_Data::4 1481 +system.ruby.network.routers0.msg_count.Writeback_Control::3 1477 +system.ruby.network.routers0.msg_bytes.Control::2 11848 +system.ruby.network.routers0.msg_bytes.Data::2 106344 +system.ruby.network.routers0.msg_bytes.Response_Data::4 106632 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11816 +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.029645 +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.749612 +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.014802 +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.993205 +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.014843 +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998597 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 99780 +system.ruby.network.routers1.percent_links_utilized 7.411305 +system.ruby.network.routers1.msg_count.Control::2 1481 +system.ruby.network.routers1.msg_count.Data::2 1477 +system.ruby.network.routers1.msg_count.Response_Data::4 1481 +system.ruby.network.routers1.msg_count.Writeback_Control::3 1477 +system.ruby.network.routers1.msg_bytes.Control::2 11848 +system.ruby.network.routers1.msg_bytes.Data::2 106344 +system.ruby.network.routers1.msg_bytes.Response_Data::4 106632 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11816 +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.029645 +system.ruby.network.int_link_buffers02.avg_stall_time 7.750093 +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.014802 +system.ruby.network.int_link_buffers08.avg_stall_time 2.989778 +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.014843 +system.ruby.network.int_link_buffers09.avg_stall_time 2.997865 +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.014802 +system.ruby.network.int_link_buffers13.avg_stall_time 4.982862 +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.014843 +system.ruby.network.int_link_buffers14.avg_stall_time 4.996342 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+system.ruby.delayVCHist.vnet_1 | 1481 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayVCHist.vnet_1::total 1481 +system.ruby.delayVCHist.vnet_2::bucket_size 1 +system.ruby.delayVCHist.vnet_2::max_bucket 9 +system.ruby.delayVCHist.vnet_2::samples 1477 +system.ruby.delayVCHist.vnet_2 | 1477 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayVCHist.vnet_2::total 1477 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 +system.ruby.LD.latency_hist_seqr::samples 1093 +system.ruby.LD.latency_hist_seqr::mean 26.049405 +system.ruby.LD.latency_hist_seqr::gmean 6.258510 +system.ruby.LD.latency_hist_seqr::stdev 34.957029 +system.ruby.LD.latency_hist_seqr | 871 79.69% 79.69% | 205 18.76% 98.44% | 14 1.28% 99.73% | 0 0.00% 99.73% | 2 0.18% 99.91% | 1 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 1093 system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 -system.ruby.LD.hit_latency_hist_seqr::samples 161 +system.ruby.LD.hit_latency_hist_seqr::samples 573 system.ruby.LD.hit_latency_hist_seqr::mean 1 system.ruby.LD.hit_latency_hist_seqr::gmean 1 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 161 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 161 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 32 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 319 -system.ruby.LD.miss_latency_hist_seqr::samples 128 -system.ruby.LD.miss_latency_hist_seqr::mean 51.421875 -system.ruby.LD.miss_latency_hist_seqr::gmean 46.125665 -system.ruby.LD.miss_latency_hist_seqr::stdev 31.235103 -system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 72 56.25% 56.25% | 54 42.19% 98.44% | 0 0.00% 98.44% | 0 0.00% 98.44% | 1 0.78% 99.22% | 0 0.00% 99.22% | 0 0.00% 99.22% | 0 0.00% 99.22% | 1 0.78% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 128 -system.ruby.ST.latency_hist_seqr::bucket_size 16 -system.ruby.ST.latency_hist_seqr::max_bucket 159 -system.ruby.ST.latency_hist_seqr::samples 279 -system.ruby.ST.latency_hist_seqr::mean 13.150538 -system.ruby.ST.latency_hist_seqr::gmean 2.682693 -system.ruby.ST.latency_hist_seqr::stdev 23.311750 -system.ruby.ST.latency_hist_seqr | 206 73.84% 73.84% | 0 0.00% 73.84% | 45 16.13% 89.96% | 2 0.72% 90.68% | 22 7.89% 98.57% | 2 0.72% 99.28% | 0 0.00% 99.28% | 1 0.36% 99.64% | 1 0.36% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist_seqr::total 279 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 573 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 573 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 +system.ruby.LD.miss_latency_hist_seqr::samples 520 +system.ruby.LD.miss_latency_hist_seqr::mean 53.651923 +system.ruby.LD.miss_latency_hist_seqr::gmean 47.219430 +system.ruby.LD.miss_latency_hist_seqr::stdev 33.391702 +system.ruby.LD.miss_latency_hist_seqr | 298 57.31% 57.31% | 205 39.42% 96.73% | 14 2.69% 99.42% | 0 0.00% 99.42% | 2 0.38% 99.81% | 1 0.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 520 +system.ruby.ST.latency_hist_seqr::bucket_size 32 +system.ruby.ST.latency_hist_seqr::max_bucket 319 +system.ruby.ST.latency_hist_seqr::samples 1089 +system.ruby.ST.latency_hist_seqr::mean 16.130395 +system.ruby.ST.latency_hist_seqr::gmean 3.002028 +system.ruby.ST.latency_hist_seqr::stdev 30.407669 +system.ruby.ST.latency_hist_seqr | 779 71.53% 71.53% | 172 15.79% 87.33% | 127 11.66% 98.99% | 0 0.00% 98.99% | 4 0.37% 99.36% | 4 0.37% 99.72% | 0 0.00% 99.72% | 0 0.00% 99.72% | 1 0.09% 99.82% | 2 0.18% 100.00% +system.ruby.ST.latency_hist_seqr::total 1089 system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 -system.ruby.ST.hit_latency_hist_seqr::samples 206 +system.ruby.ST.hit_latency_hist_seqr::samples 779 system.ruby.ST.hit_latency_hist_seqr::mean 1 system.ruby.ST.hit_latency_hist_seqr::gmean 1 -system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 206 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 206 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 16 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 159 -system.ruby.ST.miss_latency_hist_seqr::samples 73 -system.ruby.ST.miss_latency_hist_seqr::mean 47.438356 -system.ruby.ST.miss_latency_hist_seqr::gmean 43.447321 -system.ruby.ST.miss_latency_hist_seqr::stdev 21.997466 -system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 45 61.64% 61.64% | 2 2.74% 64.38% | 22 30.14% 94.52% | 2 2.74% 97.26% | 0 0.00% 97.26% | 1 1.37% 98.63% | 1 1.37% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 73 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 32 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 319 -system.ruby.IFETCH.latency_hist_seqr::samples 1597 -system.ruby.IFETCH.latency_hist_seqr::mean 9.624296 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.809372 -system.ruby.IFETCH.latency_hist_seqr::stdev 22.939232 -system.ruby.IFETCH.latency_hist_seqr | 1360 85.16% 85.16% | 83 5.20% 90.36% | 146 9.14% 99.50% | 1 0.06% 99.56% | 1 0.06% 99.62% | 6 0.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 1597 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 779 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 779 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 32 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 319 +system.ruby.ST.miss_latency_hist_seqr::samples 310 +system.ruby.ST.miss_latency_hist_seqr::mean 54.151613 +system.ruby.ST.miss_latency_hist_seqr::gmean 47.545777 +system.ruby.ST.miss_latency_hist_seqr::stdev 35.045873 +system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 172 55.48% 55.48% | 127 40.97% 96.45% | 0 0.00% 96.45% | 4 1.29% 97.74% | 4 1.29% 99.03% | 0 0.00% 99.03% | 0 0.00% 99.03% | 1 0.32% 99.35% | 2 0.65% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 310 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 5559 +system.ruby.IFETCH.latency_hist_seqr::mean 8.228638 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.602822 +system.ruby.IFETCH.latency_hist_seqr::stdev 22.809585 +system.ruby.IFETCH.latency_hist_seqr | 5120 92.10% 92.10% | 419 7.54% 99.64% | 14 0.25% 99.89% | 2 0.04% 99.93% | 2 0.04% 99.96% | 2 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 5559 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 1360 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 4911 system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 1360 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 1360 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 237 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 59.113924 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 54.365760 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 25.891554 -system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 83 35.02% 35.02% | 146 61.60% 96.62% | 1 0.42% 97.05% | 1 0.42% 97.47% | 6 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 237 -system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 32 -system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 319 -system.ruby.Directory.miss_mach_latency_hist_seqr::samples 438 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 54.920091 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 49.915756 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 27.345330 -system.ruby.Directory.miss_mach_latency_hist_seqr | 0 0.00% 0.00% | 202 46.12% 46.12% | 224 51.14% 97.26% | 2 0.46% 97.72% | 2 0.46% 98.17% | 7 1.60% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 1 0.23% 100.00% -system.ruby.Directory.miss_mach_latency_hist_seqr::total 438 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 4911 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 4911 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 648 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 63.012346 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 57.233342 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 32.663142 +system.ruby.IFETCH.miss_latency_hist_seqr | 209 32.25% 32.25% | 419 64.66% 96.91% | 14 2.16% 99.07% | 2 0.31% 99.38% | 2 0.31% 99.69% | 2 0.31% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 648 +system.ruby.Load_Linked.latency_hist_seqr::bucket_size 16 +system.ruby.Load_Linked.latency_hist_seqr::max_bucket 159 +system.ruby.Load_Linked.latency_hist_seqr::samples 8 +system.ruby.Load_Linked.latency_hist_seqr::mean 29.250000 +system.ruby.Load_Linked.latency_hist_seqr::gmean 5.055151 +system.ruby.Load_Linked.latency_hist_seqr::stdev 39.934768 +system.ruby.Load_Linked.latency_hist_seqr | 5 62.50% 62.50% | 0 0.00% 62.50% | 0 0.00% 62.50% | 0 0.00% 62.50% | 2 25.00% 87.50% | 1 12.50% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Load_Linked.latency_hist_seqr::total 8 +system.ruby.Load_Linked.hit_latency_hist_seqr::bucket_size 1 +system.ruby.Load_Linked.hit_latency_hist_seqr::max_bucket 9 +system.ruby.Load_Linked.hit_latency_hist_seqr::samples 5 +system.ruby.Load_Linked.hit_latency_hist_seqr::mean 1 +system.ruby.Load_Linked.hit_latency_hist_seqr::gmean 1 +system.ruby.Load_Linked.hit_latency_hist_seqr | 0 0.00% 0.00% | 5 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Load_Linked.hit_latency_hist_seqr::total 5 +system.ruby.Load_Linked.miss_latency_hist_seqr::bucket_size 16 +system.ruby.Load_Linked.miss_latency_hist_seqr::max_bucket 159 +system.ruby.Load_Linked.miss_latency_hist_seqr::samples 3 +system.ruby.Load_Linked.miss_latency_hist_seqr::mean 76.333333 +system.ruby.Load_Linked.miss_latency_hist_seqr::gmean 75.270431 +system.ruby.Load_Linked.miss_latency_hist_seqr::stdev 16.165808 +system.ruby.Load_Linked.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Load_Linked.miss_latency_hist_seqr::total 3 +system.ruby.Store_Conditional.latency_hist_seqr::bucket_size 1 +system.ruby.Store_Conditional.latency_hist_seqr::max_bucket 9 +system.ruby.Store_Conditional.latency_hist_seqr::samples 8 +system.ruby.Store_Conditional.latency_hist_seqr::mean 1 +system.ruby.Store_Conditional.latency_hist_seqr::gmean 1 +system.ruby.Store_Conditional.latency_hist_seqr | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Store_Conditional.latency_hist_seqr::total 8 +system.ruby.Store_Conditional.hit_latency_hist_seqr::bucket_size 1 +system.ruby.Store_Conditional.hit_latency_hist_seqr::max_bucket 9 +system.ruby.Store_Conditional.hit_latency_hist_seqr::samples 8 +system.ruby.Store_Conditional.hit_latency_hist_seqr::mean 1 +system.ruby.Store_Conditional.hit_latency_hist_seqr::gmean 1 +system.ruby.Store_Conditional.hit_latency_hist_seqr | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Store_Conditional.hit_latency_hist_seqr::total 8 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1481 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 57.898042 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 51.487789 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 33.698741 +system.ruby.Directory.miss_mach_latency_hist_seqr | 679 45.85% 45.85% | 754 50.91% 96.76% | 36 2.43% 99.19% | 2 0.14% 99.32% | 7 0.47% 99.80% | 3 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 1481 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 @@ -633,53 +673,61 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 128 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 51.421875 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 46.125665 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 31.235103 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 72 56.25% 56.25% | 54 42.19% 98.44% | 0 0.00% 98.44% | 0 0.00% 98.44% | 1 0.78% 99.22% | 0 0.00% 99.22% | 0 0.00% 99.22% | 0 0.00% 99.22% | 1 0.78% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 128 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 73 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 47.438356 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 43.447321 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 21.997466 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 45 61.64% 61.64% | 2 2.74% 64.38% | 22 30.14% 94.52% | 2 2.74% 97.26% | 0 0.00% 97.26% | 1 1.37% 98.63% | 1 1.37% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 73 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 237 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 59.113924 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 54.365760 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 25.891554 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 83 35.02% 35.02% | 146 61.60% 96.62% | 1 0.42% 97.05% | 1 0.42% 97.47% | 6 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 237 -system.ruby.Directory_Controller.GETX 438 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 434 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 438 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 434 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 438 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 434 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 438 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 434 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 289 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 1597 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 279 0.00% 0.00% -system.ruby.L1Cache_Controller.Data 438 0.00% 0.00% -system.ruby.L1Cache_Controller.Replacement 434 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 434 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 128 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 237 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 73 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 161 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 1360 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 206 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Replacement 434 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack 434 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data 365 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data 73 0.00% 0.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 520 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 53.651923 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 47.219430 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 33.391702 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 298 57.31% 57.31% | 205 39.42% 96.73% | 14 2.69% 99.42% | 0 0.00% 99.42% | 2 0.38% 99.81% | 1 0.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 520 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 310 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 54.151613 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 47.545777 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 35.045873 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 172 55.48% 55.48% | 127 40.97% 96.45% | 0 0.00% 96.45% | 4 1.29% 97.74% | 4 1.29% 99.03% | 0 0.00% 99.03% | 0 0.00% 99.03% | 1 0.32% 99.35% | 2 0.65% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 310 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 648 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 63.012346 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 57.233342 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 32.663142 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 209 32.25% 32.25% | 419 64.66% 96.91% | 14 2.16% 99.07% | 2 0.31% 99.38% | 2 0.31% 99.69% | 2 0.31% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 648 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::samples 3 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::mean 76.333333 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::gmean 75.270431 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::stdev 16.165808 +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Load_Linked.Directory.miss_type_mach_latency_hist_seqr::total 3 +system.ruby.Directory_Controller.GETX 1481 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 1477 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1481 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 1477 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 1481 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 1477 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 1481 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 1477 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 1093 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 5559 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 1105 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 1481 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 1477 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 1477 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 520 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 648 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 313 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 573 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 4911 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 792 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 1477 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 1477 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 1168 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 313 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.ini index 95b43cc99..e756a5000 100644 --- a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.ini @@ -85,6 +85,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -287,7 +288,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -296,14 +297,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello +executable=/home/ar4jc/gem5/tests/testing/../test-progs/hello/bin/riscv/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.json b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.json index 0e161c12e..7df7ef6e7 100644 --- a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.json +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.json @@ -292,6 +292,7 @@ }, "p_state_clk_gate_bins": 20, "p_state_clk_gate_min": 1000, + "syscallRetryLatency": 10000, "interrupts": [ { "eventq_index": 0, @@ -376,21 +377,22 @@ "uid": 100, "pid": 100, "kvmInSE": false, - "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello", + "cxx_class": "Process", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/hello/bin/riscv/linux/hello", "drivers": [], "system": "system", "gid": 100, "eventq_index": 0, "env": [], - "input": "cin", - "ppid": 99, - "type": "LiveProcess", + "maxStackSize": 67108864, + "ppid": 0, + "type": "Process", "cwd": "", + "pgid": 100, "simpoint": 0, "euid": 100, + "input": "cin", "path": "system.cpu.workload", - "max_stack_size": 67108864, "name": "workload", "cmd": [ "hello" diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simerr index fd133b12b..5df892149 100755 --- a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simerr +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simerr @@ -1,3 +1,6 @@ -warn: Unknown operating system; assuming Linux. warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... +warn: readlink() called on '/proc/self/exe' may yield unexpected results in various settings. + Returning '/home/ar4jc/gem5/tests/test-progs/hello/bin/riscv/linux/hello' +info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simout index b34519614..385bb2b92 100755 --- a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simout @@ -1,15 +1,13 @@ -Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing/simout -Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing/simerr +Redirecting stdout to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:29 -gem5 executing on zizzer, pid 34059 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-timing +gem5 compiled May 31 2017 18:33:59 +gem5 started May 31 2017 18:34:14 +gem5 executing on boldrock, pid 15728 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. Hello world! -Exiting @ tick 11602500 because target called exit() +Exiting @ tick 34045500 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/stats.txt index 3950ac70e..cd7d81716 100644 --- a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/stats.txt @@ -1,511 +1,529 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11602500 # Number of ticks simulated -final_tick 11602500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36172 # Simulator instruction rate (inst/s) -host_op_rate 36155 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 264212858 # Simulator tick rate (ticks/s) -host_mem_usage 230876 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -sim_insts 1587 # Number of instructions simulated -sim_ops 1587 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 7808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1920 # Number of bytes read from this memory -system.physmem.bytes_read::total 9728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 7808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7808 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 122 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 30 # Number of read requests responded to by this memory -system.physmem.num_reads::total 152 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 672958414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 165481577 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 838439991 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 672958414 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 672958414 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 672958414 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 165481577 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 838439991 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 9 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 11602500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 23205 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1587 # Number of instructions committed -system.cpu.committedOps 1587 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1588 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 142 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 231 # number of instructions that are conditional controls -system.cpu.num_int_insts 1588 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 2062 # number of times the integer registers were read -system.cpu.num_int_register_writes 1077 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 569 # number of memory refs -system.cpu.num_load_insts 289 # Number of load instructions -system.cpu.num_store_insts 280 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 23205 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 373 # Number of branches fetched -system.cpu.op_class::No_OpClass 9 0.56% 0.56% # Class of executed instruction -system.cpu.op_class::IntAlu 1019 63.81% 64.37% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.37% # Class of executed instruction -system.cpu.op_class::MemRead 289 18.10% 82.47% # Class of executed instruction -system.cpu.op_class::MemWrite 280 17.53% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1597 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 22.779229 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 537 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 31 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.322581 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 22.779229 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.005561 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.005561 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 31 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.007568 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1167 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1167 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 276 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 276 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 261 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 261 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 537 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 537 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 537 # number of overall hits -system.cpu.dcache.overall_hits::total 537 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 13 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 13 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 18 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 18 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 31 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 31 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 31 # number of overall misses -system.cpu.dcache.overall_misses::total 31 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 770000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 770000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1134000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1134000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1904000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1904000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1904000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1904000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 289 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 289 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 279 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 279 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 568 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 568 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 568 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 568 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.044983 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.044983 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.064516 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.064516 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.054577 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.054577 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.054577 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.054577 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59230.769231 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59230.769231 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61419.354839 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61419.354839 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61419.354839 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61419.354839 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 13 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 13 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 18 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 18 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 31 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 31 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 31 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 31 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 757000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 757000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1116000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1116000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1873000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 1873000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1873000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 1873000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044983 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044983 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.064516 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.064516 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054577 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.054577 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054577 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.054577 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58230.769231 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58230.769231 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60419.354839 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 60419.354839 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60419.354839 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 60419.354839 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 56.912998 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1476 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 122 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12.098361 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 56.912998 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.027790 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.027790 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 122 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.059570 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 3318 # Number of tag accesses -system.cpu.icache.tags.data_accesses 3318 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1476 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1476 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1476 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1476 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1476 # number of overall hits -system.cpu.icache.overall_hits::total 1476 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 122 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 122 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 122 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 122 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 122 # number of overall misses -system.cpu.icache.overall_misses::total 122 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 7686500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 7686500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 7686500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 7686500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 7686500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 7686500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1598 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1598 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1598 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1598 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1598 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1598 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.076345 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.076345 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.076345 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.076345 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.076345 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.076345 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63004.098361 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63004.098361 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63004.098361 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63004.098361 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63004.098361 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63004.098361 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 122 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 122 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 122 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 122 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 122 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 122 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7564500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 7564500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7564500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 7564500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7564500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 7564500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076345 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076345 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076345 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.076345 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076345 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.076345 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62004.098361 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62004.098361 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62004.098361 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 62004.098361 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62004.098361 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 62004.098361 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 78.991344 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 152 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.006579 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 57.023406 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 21.967939 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001740 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000670 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.002411 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 152 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.004639 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 1376 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 1376 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits -system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 18 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 18 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 122 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 122 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 12 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 122 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 30 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 152 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 122 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 30 # number of overall misses -system.cpu.l2cache.overall_misses::total 152 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1089000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1089000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 7381500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 7381500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 726000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 726000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 7381500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1815000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9196500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 7381500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1815000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9196500 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 18 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 18 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 122 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 122 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 13 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 13 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 122 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 31 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 153 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 122 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 31 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 153 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.923077 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.923077 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.967742 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.993464 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.967742 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.993464 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60504.098361 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60504.098361 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60504.098361 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60503.289474 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60504.098361 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60503.289474 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 18 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 18 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 122 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 122 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 122 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 30 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 152 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 122 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 30 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 152 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 909000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 909000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 6161500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 6161500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 606000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 606000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6161500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1515000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7676500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6161500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1515000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 7676500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.923077 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.923077 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.967742 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.993464 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.967742 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.993464 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50504.098361 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50504.098361 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50504.098361 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50503.289474 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50504.098361 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50503.289474 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 153 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 135 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 18 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 18 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 122 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 13 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 244 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 306 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 9792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 153 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.006536 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.080845 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 152 99.35% 99.35% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.65% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 153 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 76500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 183000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 46500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 152 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 134 # Transaction distribution -system.membus.trans_dist::ReadExReq 18 # Transaction distribution -system.membus.trans_dist::ReadExResp 18 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 134 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 304 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 304 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 9728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 9728 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 152 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 152 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 152 # Request fanout histogram -system.membus.reqLayer0.occupancy 152500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 760000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.6 # Layer utilization (%) +sim_seconds 0.000034 +sim_ticks 34045500 +final_tick 34045500 +sim_freq 1000000000000 +host_inst_rate 83295 +host_op_rate 83403 +host_tick_rate 510821707 +host_mem_usage 275396 +host_seconds 0.07 +sim_insts 5550 +sim_ops 5558 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 34045500 +system.physmem.bytes_read::cpu.inst 17856 +system.physmem.bytes_read::cpu.data 9280 +system.physmem.bytes_read::total 27136 +system.physmem.bytes_inst_read::cpu.inst 17856 +system.physmem.bytes_inst_read::total 17856 +system.physmem.num_reads::cpu.inst 279 +system.physmem.num_reads::cpu.data 145 +system.physmem.num_reads::total 424 +system.physmem.bw_read::cpu.inst 524474600 +system.physmem.bw_read::cpu.data 272576405 +system.physmem.bw_read::total 797051005 +system.physmem.bw_inst_read::cpu.inst 524474600 +system.physmem.bw_inst_read::total 524474600 +system.physmem.bw_total::cpu.inst 524474600 +system.physmem.bw_total::cpu.data 272576405 +system.physmem.bw_total::total 797051005 +system.pwrStateResidencyTicks::UNDEFINED 34045500 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 9 +system.cpu.pwrStateResidencyTicks::ON 34045500 +system.cpu.numCycles 68091 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5550 +system.cpu.committedOps 5558 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+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.792115 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.792115 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.792115 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.179245 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.792115 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.179245 +system.cpu.toL2Bus.snoop_filter.tot_requests 424 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 34045500 +system.cpu.toL2Bus.trans_dist::ReadResp 342 +system.cpu.toL2Bus.trans_dist::ReadExReq 82 +system.cpu.toL2Bus.trans_dist::ReadExResp 82 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 279 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 63 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 290 +system.cpu.toL2Bus.pkt_count::total 848 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9280 +system.cpu.toL2Bus.pkt_size::total 27136 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 424 +system.cpu.toL2Bus.snoop_fanout::mean 0 +system.cpu.toL2Bus.snoop_fanout::stdev 0 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 424 100.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 0 +system.cpu.toL2Bus.snoop_fanout::total 424 +system.cpu.toL2Bus.reqLayer0.occupancy 212000 +system.cpu.toL2Bus.reqLayer0.utilization 0.6 +system.cpu.toL2Bus.respLayer0.occupancy 418500 +system.cpu.toL2Bus.respLayer0.utilization 1.2 +system.cpu.toL2Bus.respLayer1.occupancy 217500 +system.cpu.toL2Bus.respLayer1.utilization 0.6 +system.membus.snoop_filter.tot_requests 424 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 34045500 +system.membus.trans_dist::ReadResp 342 +system.membus.trans_dist::ReadExReq 82 +system.membus.trans_dist::ReadExResp 82 +system.membus.trans_dist::ReadSharedReq 342 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 848 +system.membus.pkt_count::total 848 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27136 +system.membus.pkt_size::total 27136 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 424 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 424 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 424 +system.membus.reqLayer0.occupancy 424500 +system.membus.reqLayer0.utilization 1.2 +system.membus.respLayer1.occupancy 2120000 +system.membus.respLayer1.utilization 6.2 ---------- End Simulation Statistics ---------- |