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authorNilay Vaish <nilay@cs.wisc.edu>2013-06-10 06:46:20 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2013-06-10 06:46:20 -0500
commit247e4e9ab41bafcfcbde725bb40e6a7b5628f1de (patch)
treeb4312f540772ef437b5b962cc1fff4bb54d90ce4 /tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
parentd32ee94231251b8d07bb811142f6759f8655962b (diff)
downloadgem5-247e4e9ab41bafcfcbde725bb40e6a7b5628f1de.tar.xz
stats: updates due to changes to ruby
Ruby's controller statistics have been mostly moved to stats.txt now. Plus stats.txt for solaris/t1000-simple-atomic and arm/20.parser are also being updated.
Diffstat (limited to 'tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt')
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt49
1 files changed, 44 insertions, 5 deletions
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
index 1ca0b6acd..87117a3bf 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
@@ -4,16 +4,31 @@ sim_seconds 0.000108 # Nu
sim_ticks 107952 # Number of ticks simulated
final_tick 107952 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 36056 # Simulator instruction rate (inst/s)
-host_op_rate 36051 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 730482 # Simulator tick rate (ticks/s)
-host_mem_usage 160860 # Number of bytes of host memory used
-host_seconds 0.15 # Real time elapsed on the host
+host_inst_rate 37306 # Simulator instruction rate (inst/s)
+host_op_rate 37301 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 755806 # Simulator tick rate (ticks/s)
+host_mem_usage 148468 # Number of bytes of host memory used
+host_seconds 0.14 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses
+system.ruby.dir_cntrl0.memBuffer.memReq 2574 # Total number of memory requests
+system.ruby.dir_cntrl0.memBuffer.memRead 1289 # Number of memory reads
+system.ruby.dir_cntrl0.memBuffer.memWrite 1285 # Number of memory writes
+system.ruby.dir_cntrl0.memBuffer.memRefresh 750 # Number of memory refreshes
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles 1871 # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.memBankQ 2 # Delay behind the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.totalStalls 1873 # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.727661 # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy 758 # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy 992 # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 52 # memory stalls due to read write turnaround
+system.ruby.dir_cntrl0.memBuffer.memArbWait 69 # memory stalls due to arbitration
+system.ruby.dir_cntrl0.memBuffer.memBankCount | 166 6.45% 6.45% | 40 1.55% 8.00% | 36 1.40% 9.40% | 48 1.86% 11.27% | 109 4.23% 15.50% | 42 1.63% 17.13% | 63 2.45% 19.58% | 241 9.36% 28.94% | 50 1.94% 30.89% | 34 1.32% 32.21% | 16 0.62% 32.83% | 26 1.01% 33.84% | 60 2.33% 36.17% | 64 2.49% 38.66% | 38 1.48% 40.13% | 46 1.79% 41.92% | 30 1.17% 43.08% | 88 3.42% 46.50% | 202 7.85% 54.35% | 144 5.59% 59.95% | 40 1.55% 61.50% | 58 2.25% 63.75% | 22 0.85% 64.61% | 20 0.78% 65.38% | 60 2.33% 67.72% | 120 4.66% 72.38% | 136 5.28% 77.66% | 125 4.86% 82.52% | 84 3.26% 85.78% | 134 5.21% 90.99% | 166 6.45% 97.44% | 66 2.56% 100.00% # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memBankCount::total 2574 # Number of accesses per bank
+
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 107952 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
@@ -37,5 +52,29 @@ system.cpu.num_idle_cycles 0 # Nu
system.cpu.num_busy_cycles 107952 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.ruby.l1_cntrl0.Load 715 0.00% 0.00%
+system.ruby.l1_cntrl0.Ifetch 5370 0.00% 0.00%
+system.ruby.l1_cntrl0.Store 673 0.00% 0.00%
+system.ruby.l1_cntrl0.Data 1289 0.00% 0.00%
+system.ruby.l1_cntrl0.Replacement 1285 0.00% 0.00%
+system.ruby.l1_cntrl0.Writeback_Ack 1285 0.00% 0.00%
+system.ruby.l1_cntrl0.I.Load 395 0.00% 0.00%
+system.ruby.l1_cntrl0.I.Ifetch 715 0.00% 0.00%
+system.ruby.l1_cntrl0.I.Store 179 0.00% 0.00%
+system.ruby.l1_cntrl0.M.Load 320 0.00% 0.00%
+system.ruby.l1_cntrl0.M.Ifetch 4655 0.00% 0.00%
+system.ruby.l1_cntrl0.M.Store 494 0.00% 0.00%
+system.ruby.l1_cntrl0.M.Replacement 1285 0.00% 0.00%
+system.ruby.l1_cntrl0.MI.Writeback_Ack 1285 0.00% 0.00%
+system.ruby.l1_cntrl0.IS.Data 1110 0.00% 0.00%
+system.ruby.l1_cntrl0.IM.Data 179 0.00% 0.00%
+system.ruby.dir_cntrl0.GETX 1289 0.00% 0.00%
+system.ruby.dir_cntrl0.PUTX 1285 0.00% 0.00%
+system.ruby.dir_cntrl0.Memory_Data 1289 0.00% 0.00%
+system.ruby.dir_cntrl0.Memory_Ack 1285 0.00% 0.00%
+system.ruby.dir_cntrl0.I.GETX 1289 0.00% 0.00%
+system.ruby.dir_cntrl0.M.PUTX 1285 0.00% 0.00%
+system.ruby.dir_cntrl0.IM.Memory_Data 1289 0.00% 0.00%
+system.ruby.dir_cntrl0.MI.Memory_Ack 1285 0.00% 0.00%
---------- End Simulation Statistics ----------