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authorAli Saidi <Ali.Saidi@ARM.com>2014-01-24 15:29:33 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2014-01-24 15:29:33 -0600
commitf3585c841e964c98911784a187fc4f081a02a0a6 (patch)
tree2a5a3edeaeb0ffe37ca3a04b884f8f66c7538bbf /tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby
parentcfc4a999828a5b51f4c514e3a7c47b4eebc450b9 (diff)
downloadgem5-f3585c841e964c98911784a187fc4f081a02a0a6.tar.xz
stats: update stats for cache occupancy and clock domain changes
Diffstat (limited to 'tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby')
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini51
-rwxr-xr-xtests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr1
-rwxr-xr-xtests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout8
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt15
4 files changed, 52 insertions, 23 deletions
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
index 0e46b888b..cb65490fc 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
@@ -1,7 +1,9 @@
[root]
type=Root
children=system
+eventq_index=0
full_system=false
+sim_quantum=0
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
@@ -12,6 +14,7 @@ children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -33,6 +36,7 @@ system_port=system.sys_port_proxy.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1
+eventq_index=0
voltage_domain=system.voltage_domain
[system.cpu]
@@ -45,6 +49,7 @@ do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
+eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
@@ -68,24 +73,30 @@ icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
[system.cpu.clk_domain]
type=SrcClockDomain
clock=1
+eventq_index=0
voltage_domain=system.voltage_domain
[system.cpu.dtb]
type=SparcTLB
+eventq_index=0
size=64
[system.cpu.interrupts]
type=SparcInterrupts
+eventq_index=0
[system.cpu.isa]
type=SparcISA
+eventq_index=0
[system.cpu.itb]
type=SparcTLB
+eventq_index=0
size=64
[system.cpu.tracer]
type=ExeTracer
+eventq_index=0
[system.cpu.workload]
type=LiveProcess
@@ -95,7 +106,8 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
+eventq_index=0
+executable=/dist/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -111,6 +123,7 @@ type=SimpleMemory
bandwidth=0.000000
clk_domain=system.clk_domain
conf_table_reported=true
+eventq_index=0
in_addr_map=true
latency=30
latency_var=0
@@ -119,18 +132,22 @@ range=0:134217727
[system.ruby]
type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network profiler
+children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
+eventq_index=0
+hot_lines=false
mem_size=268435456
no_mem_vec=false
+num_of_sequencers=1
random_seed=1234
randomization=false
-stats_filename=ruby.stats
[system.ruby.clk_domain]
type=SrcClockDomain
clock=1
+eventq_index=0
voltage_domain=system.voltage_domain
[system.ruby.dir_cntrl0]
@@ -138,9 +155,10 @@ type=Directory_Controller
children=directory memBuffer
buffer_size=0
clk_domain=system.ruby.clk_domain
-cntrl_id=1
+cluster_id=0
directory=system.ruby.dir_cntrl0.directory
directory_latency=12
+eventq_index=0
memBuffer=system.ruby.dir_cntrl0.memBuffer
number_of_TBEs=256
peer=Null
@@ -151,6 +169,7 @@ version=0
[system.ruby.dir_cntrl0.directory]
type=RubyDirectoryMemory
+eventq_index=0
map_levels=4
numa_high_bit=5
size=268435456
@@ -167,6 +186,7 @@ basic_bus_busy_time=2
clk_domain=system.ruby.memctrl_clk_domain
dimm_bit_0=12
dimms_per_channel=2
+eventq_index=0
mem_ctl_latency=12
mem_fixed_delay=0
mem_random_arbitrate=0
@@ -186,7 +206,8 @@ buffer_size=0
cacheMemory=system.ruby.l1_cntrl0.cacheMemory
cache_response_latency=12
clk_domain=system.ruby.clk_domain
-cntrl_id=0
+cluster_id=0
+eventq_index=0
issue_latency=2
number_of_TBEs=256
peer=Null
@@ -202,6 +223,7 @@ type=RubyCache
assoc=2
dataAccessLatency=1
dataArrayBanks=1
+eventq_index=0
is_icache=false
latency=3
replacement_policy=PSEUDO_LRU
@@ -217,6 +239,7 @@ access_phys_mem=false
clk_domain=system.ruby.clk_domain
dcache=system.ruby.l1_cntrl0.cacheMemory
deadlock_threshold=500000
+eventq_index=0
icache=system.ruby.l1_cntrl0.cacheMemory
max_outstanding_requests=16
ruby_system=system.ruby
@@ -232,6 +255,7 @@ slave=system.cpu.icache_port system.cpu.dcache_port
type=DerivedClockDomain
clk_divider=3
clk_domain=system.ruby.clk_domain
+eventq_index=0
[system.ruby.network]
type=SimpleNetwork
@@ -241,6 +265,7 @@ buffer_size=0
clk_domain=system.ruby.clk_domain
control_msg_size=8
endpoint_bandwidth=1000
+eventq_index=0
ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
number_of_virtual_networks=10
@@ -251,6 +276,7 @@ topology=Crossbar
[system.ruby.network.ext_links0]
type=SimpleExtLink
bandwidth_factor=16
+eventq_index=0
ext_node=system.ruby.l1_cntrl0
int_node=system.ruby.network.routers0
latency=1
@@ -260,6 +286,7 @@ weight=1
[system.ruby.network.ext_links1]
type=SimpleExtLink
bandwidth_factor=16
+eventq_index=0
ext_node=system.ruby.dir_cntrl0
int_node=system.ruby.network.routers1
latency=1
@@ -269,6 +296,7 @@ weight=1
[system.ruby.network.int_links0]
type=SimpleIntLink
bandwidth_factor=16
+eventq_index=0
latency=1
link_id=2
node_a=system.ruby.network.routers0
@@ -278,6 +306,7 @@ weight=1
[system.ruby.network.int_links1]
type=SimpleIntLink
bandwidth_factor=16
+eventq_index=0
latency=1
link_id=3
node_a=system.ruby.network.routers1
@@ -287,32 +316,29 @@ weight=1
[system.ruby.network.routers0]
type=Switch
clk_domain=system.ruby.clk_domain
+eventq_index=0
router_id=0
virt_nets=10
[system.ruby.network.routers1]
type=Switch
clk_domain=system.ruby.clk_domain
+eventq_index=0
router_id=1
virt_nets=10
[system.ruby.network.routers2]
type=Switch
clk_domain=system.ruby.clk_domain
+eventq_index=0
router_id=2
virt_nets=10
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=1
-ruby_system=system.ruby
-
[system.sys_port_proxy]
type=RubyPortProxy
access_phys_mem=true
clk_domain=system.clk_domain
+eventq_index=0
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
@@ -324,5 +350,6 @@ slave=system.system_port
[system.voltage_domain]
type=VoltageDomain
+eventq_index=0
voltage=1.000000
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
index bbc0c797e..86244d4bf 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
@@ -3,4 +3,3 @@ warn: rounding error > tolerance
warn: rounding error > tolerance
0.072760 rounded to 0
warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
index fe6ceebff..a7fbcbb0c 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 22 2013 06:07:13
-gem5 started Sep 22 2013 06:10:00
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:04:27
+gem5 started Jan 22 2014 17:29:33
+gem5 executing on u200540-lin
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
index d8d5f48fa..ff67fbecb 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
@@ -4,13 +4,16 @@ sim_seconds 0.000108 # Nu
sim_ticks 107952 # Number of ticks simulated
final_tick 107952 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 352 # Simulator instruction rate (inst/s)
-host_op_rate 352 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 7141 # Simulator tick rate (ticks/s)
-host_mem_usage 177732 # Number of bytes of host memory used
-host_seconds 15.12 # Real time elapsed on the host
+host_inst_rate 32230 # Simulator instruction rate (inst/s)
+host_op_rate 32227 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 653032 # Simulator tick rate (ticks/s)
+host_mem_usage 134144 # Number of bytes of host memory used
+host_seconds 0.17 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1 # Clock period in ticks
+system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 2574 # delay histogram for all message
@@ -47,6 +50,7 @@ system.ruby.miss_latency_hist::stdev 6.536157
system.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 306 23.74% 23.74% | 913 70.83% 94.57% | 68 5.28% 99.84% | 1 0.08% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist::total 1289
system.ruby.Directory.incomplete_times 1288
+system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses
@@ -99,6 +103,7 @@ system.ruby.network.msg_byte.Control 30936
system.ruby.network.msg_byte.Data 277560
system.ruby.network.msg_byte.Response_Data 278424
system.ruby.network.msg_byte.Writeback_Control 30840
+system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 107952 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started