Stats: Update stats for new default L1-to-L2 bus clock and width

This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.

1 files changed, 60 insertions, 60 deletions

diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
index 3eb56a69e..37ab13bca 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000030                       # Number of seconds simulated
-sim_ticks                                    29527000                       # Number of ticks simulated
-final_tick                                   29527000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000028                       # Number of seconds simulated
+sim_ticks                                    27800000                       # Number of ticks simulated
+final_tick                                   27800000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  69145                       # Simulator instruction rate (inst/s)
-host_op_rate                                    69130                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              383102769                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 229488                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
+host_inst_rate                                 251441                       # Simulator instruction rate (inst/s)
+host_op_rate                                   251244                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1310200039                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220428                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5327                       # Number of instructions simulated
 sim_ops                                          5327                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             16320                       # Number of bytes read from this memory
@@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total           16320                       # Nu
 system.physmem.num_reads::cpu.inst                255                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                134                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   389                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            552714465                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            290446032                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               843160497                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       552714465                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          552714465                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           552714465                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           290446032                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              843160497                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            587050360                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            308489209                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               895539568                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       587050360                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          587050360                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           587050360                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           308489209                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              895539568                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.numCycles                            59054                       # number of cpu cycles simulated
+system.cpu.numCycles                            55600                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        5327                       # Number of instructions committed
@@ -47,18 +47,18 @@ system.cpu.num_mem_refs                          1401                       # nu
 system.cpu.num_load_insts                         723                       # Number of load instructions
 system.cpu.num_store_insts                        678                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      59054                       # Number of busy cycles
+system.cpu.num_busy_cycles                      55600                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                117.127109                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                117.043638                       # Cycle average of tags in use
 system.cpu.icache.total_refs                     5114                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    257                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  19.898833                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     117.127109                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.057191                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.057191                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     117.043638                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.057150                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.057150                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst         5114                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            5114                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          5114                       # number of demand (read+write) hits
@@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst          257                       # n
 system.cpu.icache.demand_misses::total            257                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          257                       # number of overall misses
 system.cpu.icache.overall_misses::total           257                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     14308000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     14308000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     14308000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     14308000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     14308000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     14308000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     14051000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     14051000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     14051000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     14051000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     14051000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     14051000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         5371                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         5371                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         5371                       # number of demand (read+write) accesses
@@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.047850
 system.cpu.icache.demand_miss_rate::total     0.047850                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.047850                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.047850                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55673.151751                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 55673.151751                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 55673.151751                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 55673.151751                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 55673.151751                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 55673.151751                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54673.151751                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 54673.151751                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 54673.151751                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 54673.151751                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 54673.151751                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 54673.151751                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751
 system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 82.138993                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                 82.118455                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                     1253                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    135                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                   9.281481                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      82.138993                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.020053                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.020053                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data      82.118455                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.020048                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.020048                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data          661                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total             661                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          592                       # number of WriteReq hits
@@ -153,14 +153,14 @@ system.cpu.dcache.demand_misses::cpu.data          135                       # n
 system.cpu.dcache.demand_misses::total            135                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          135                       # number of overall misses
 system.cpu.dcache.overall_misses::total           135                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      2982000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      2982000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      4536000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      4536000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data      7518000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total      7518000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data      7518000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total      7518000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      2928000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      2928000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      4455000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      4455000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data      7383000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      7383000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      7383000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      7383000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data          715                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total          715                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          673                       # number of WriteReq accesses(hits+misses)
@@ -177,14 +177,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.097262
 system.cpu.dcache.demand_miss_rate::total     0.097262                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.097262                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.097262                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55222.222222                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 55222.222222                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total        56000                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 55688.888889                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 55688.888889                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 55688.888889                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 55688.888889                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        55000                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total        55000                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 54688.888889                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 54688.888889                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -227,16 +227,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               142.279716                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               142.183999                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       3                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   308                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.009740                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    116.596239                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     25.683477                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.003558                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.000784                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.004342                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    116.519250                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     25.664749                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.003556                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.000783                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.004339                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              3                       # number of ReadReq hits