summaryrefslogtreecommitdiff
path: root/tests/quick/se/00.hello/ref/sparc/linux/simple-timing
diff options
context:
space:
mode:
authorAndreas Hansson <andreas.hansson@arm.com>2013-08-19 03:52:36 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2013-08-19 03:52:36 -0400
commitb63631536d974f31cf99ee280271dc0f7b4c746f (patch)
treeff83820d8dd75de8238e4b7ddaf3b91e4cf8374f /tests/quick/se/00.hello/ref/sparc/linux/simple-timing
parent646c4a23ca44aab5468c896034288151c89be782 (diff)
downloadgem5-b63631536d974f31cf99ee280271dc0f7b4c746f.tar.xz
stats: Cumulative stats update
This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
Diffstat (limited to 'tests/quick/se/00.hello/ref/sparc/linux/simple-timing')
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt82
1 files changed, 41 insertions, 41 deletions
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
index c4b2117ab..b76f909df 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -4,10 +4,10 @@ sim_seconds 0.000028 # Nu
sim_ticks 27800000 # Number of ticks simulated
final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 413138 # Simulator instruction rate (inst/s)
-host_op_rate 412367 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2148212772 # Simulator tick rate (ticks/s)
-host_mem_usage 231400 # Number of bytes of host memory used
+host_inst_rate 441877 # Simulator instruction rate (inst/s)
+host_op_rate 441389 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2300957264 # Simulator tick rate (ticks/s)
+host_mem_usage 230904 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
@@ -32,10 +32,10 @@ system.membus.trans_dist::ReadReq 308 # Tr
system.membus.trans_dist::ReadResp 308 # Transaction distribution
system.membus.trans_dist::ReadExReq 81 # Transaction distribution
system.membus.trans_dist::ReadExResp 81 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side 778 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count 778 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 24896 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size 24896 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 24896 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 389000 # Layer occupancy (ticks)
@@ -65,15 +65,15 @@ system.cpu.num_idle_cycles 0 # Nu
system.cpu.num_busy_cycles 55600 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 117.043638 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.057150 # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements 0 # number of replacements
+system.cpu.icache.tags.tagsinuse 117.043638 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.057150 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits
@@ -143,17 +143,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 142.183999 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.replacements 0 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 142.183999 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003556 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.004339 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.004339 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
@@ -271,15 +271,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 82.118455 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.020048 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 0 # number of replacements
+system.cpu.dcache.tags.tagsinuse 82.118455 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.020048 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits
@@ -374,12 +374,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq 311 # Tr
system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 514 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 270 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count 784 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 16448 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8640 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size 25088 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 514 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 784 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16448 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 25088 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks)