all: Update stats for memory per master and total fix.

3 files changed, 70 insertions, 21 deletions

diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
index 958c9bb97..232d3350e 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -143,9 +143,8 @@ cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
 [system.cpu.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -176,9 +175,8 @@ system=system
 uid=100
 
 [system.membus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
index 702411d18..e4af58bc7 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:05:42
-gem5 started May  8 2012 15:36:55
-gem5 executing on piton
+gem5 compiled Jun  4 2012 12:01:47
+gem5 started Jun  4 2012 14:44:42
+gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
index d2987c02e..3580b75db 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -4,22 +4,29 @@ sim_seconds                                  0.000028                       # Nu
 sim_ticks                                    28206000                       # Number of ticks simulated
 final_tick                                   28206000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 240215                       # Simulator instruction rate (inst/s)
-host_op_rate                                   240049                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1267195715                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 220748                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                 427855                       # Simulator instruction rate (inst/s)
+host_op_rate                                   427237                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2253599179                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 221156                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5340                       # Number of instructions simulated
 sim_ops                                          5340                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                       24896                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                  16320                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                        0                       # Number of bytes written to this memory
-system.physmem.num_reads                          389                       # Number of read requests responded to by this memory
-system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                      882649082                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                 578600298                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total                     882649082                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst             16320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              8576                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                24896                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        16320                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           16320                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                255                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                134                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                   389                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst            578600298                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            304048784                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               882649082                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       578600298                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          578600298                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           578600298                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           304048784                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              882649082                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                            56412                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -77,11 +84,17 @@ system.cpu.icache.demand_accesses::total         5384                       # nu
 system.cpu.icache.overall_accesses::cpu.inst         5384                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total         5384                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.047734                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.047734                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.047734                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.047734                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.047734                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.047734                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55673.151751                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55673.151751                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 55673.151751                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55673.151751                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 55673.151751                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55673.151751                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -103,11 +116,17 @@ system.cpu.icache.demand_mshr_miss_latency::total     13537000
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst     13537000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total     13537000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.047734                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.047734                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.047734                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.047734                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.047734                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.047734                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52673.151751                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52673.151751                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52673.151751                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 82.065697                       # Cycle average of tags in use
@@ -151,13 +170,21 @@ system.cpu.dcache.demand_accesses::total         1389                       # nu
 system.cpu.dcache.overall_accesses::cpu.data         1389                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total         1389                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.075419                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.075419                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.120357                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.120357                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.097192                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.097192                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.097192                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.097192                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55222.222222                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55222.222222                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total        56000                       # average WriteReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 55688.888889                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 55688.888889                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 55688.888889                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 55688.888889                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -183,13 +210,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total      7113000
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7113000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      7113000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075419                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.075419                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.120357                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.120357                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.097192                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.097192                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.097192                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.097192                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52222.222222                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        53000                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               142.102892                       # Cycle average of tags in use
@@ -246,18 +281,26 @@ system.cpu.l2cache.overall_accesses::cpu.data          135
 system.cpu.l2cache.overall_accesses::total          392                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.992218                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.981481                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.990354                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst     0.992218                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.992593                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.992347                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.992218                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.992593                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.992347                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -290,18 +333,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5360000
 system.cpu.l2cache.overall_mshr_miss_latency::total     15560000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.992218                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.981481                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.990354                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.992218                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.992593                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.992347                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.992218                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.992593                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.992347                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------