diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
| commit | 8b4b1dcb86b0799a8c32056427581a8b6249a3bf (patch) | |
| tree | 96016b415513dc6c2c29877e1a76220e0edae629 /tests/quick/se/00.hello/ref/sparc/linux | |
| parent | a00383a40aeb8347af7e05f3966ab141484921a5 (diff) | |
| download | gem5-8b4b1dcb86b0799a8c32056427581a8b6249a3bf.tar.xz | |
stats: Update stats for DRAM changes
This patch updates the stats to reflect the changes to the DRAM
controller.
Diffstat (limited to 'tests/quick/se/00.hello/ref/sparc/linux')
| -rw-r--r-- | tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt | 429 |
1 files changed, 226 insertions, 203 deletions
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 005c21949..ca26bca81 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20892500 # Number of ticks simulated -final_tick 20892500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20970500 # Number of ticks simulated +final_tick 20970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24019 # Simulator instruction rate (inst/s) -host_op_rate 24017 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 94189663 # Simulator tick rate (ticks/s) -host_mem_usage 236900 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host +host_inst_rate 71497 # Simulator instruction rate (inst/s) +host_op_rate 71482 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 281347268 # Simulator tick rate (ticks/s) +host_mem_usage 269780 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 18496 # Nu system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 885293766 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 410482230 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1295775996 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 885293766 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 885293766 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 885293766 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 410482230 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1295775996 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 882000906 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 408955437 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1290956343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 882000906 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 882000906 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 882000906 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 408955437 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1290956343 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 423 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 423 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20823000 # Total gap between requests +system.physmem.totGap 20901000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -154,53 +154,76 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 80 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 298.400000 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.623207 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 338.187934 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 31 38.75% 38.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 11 13.75% 52.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 4 5.00% 57.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 6 7.50% 65.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 1 1.25% 66.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 6 7.50% 73.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 4 5.00% 78.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 3 3.75% 82.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 6 7.50% 90.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 2 2.50% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 1.25% 93.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 1 1.25% 95.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 1 1.25% 96.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 1 1.25% 97.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 1 1.25% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 1 1.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 80 # Bytes accessed per row activation -system.physmem.totQLat 3229250 # Total ticks spent queuing -system.physmem.totMemAccLat 11834250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 48 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 337.333333 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 221.579222 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 300.401245 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13 27.08% 27.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9 18.75% 45.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6 12.50% 58.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7 14.58% 72.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 6 12.50% 85.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 4.17% 89.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 10.42% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 48 # Bytes accessed per row activation +system.physmem.totQLat 3113750 # Total ticks spent queuing +system.physmem.totMemAccLat 11732500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2115000 # Total ticks spent in databus transfers -system.physmem.totBankLat 6490000 # Total ticks spent accessing banks -system.physmem.avgQLat 7634.16 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 15342.79 # Average bank access latency per DRAM burst +system.physmem.totBankLat 6503750 # Total ticks spent accessing banks +system.physmem.avgQLat 7361.11 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 15375.30 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27976.95 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1295.78 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27736.41 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1290.96 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1295.78 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1290.96 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.12 # Data bus utilization in percentage -system.physmem.busUtilRead 10.12 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.09 # Data bus utilization in percentage +system.physmem.busUtilRead 10.09 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.57 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 343 # Number of row buffer hits during reads +system.physmem.readRowHits 339 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.09 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.14 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 49226.95 # Average gap between requests -system.physmem.pageHitRate 81.09 # Row buffer hit rate, read and write combined +system.physmem.avgGap 49411.35 # Average gap between requests +system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 1295775996 # Throughput (bytes/s) +system.membus.throughput 1290956343 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 342 # Transaction distribution system.membus.trans_dist::ReadResp 342 # Transaction distribution system.membus.trans_dist::ReadExReq 81 # Transaction distribution @@ -211,10 +234,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 27072 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 27072 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 502000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 501500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3930250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 18.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 3929500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 18.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 1636 # Number of BP lookups system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted @@ -226,7 +249,7 @@ system.cpu.branchPred.BTBHitPct 43.484736 # BT system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 41786 # number of cpu cycles simulated +system.cpu.numCycles 41942 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True). @@ -248,12 +271,12 @@ system.cpu.execution_unit.executions 3957 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9664 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9659 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 428 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35541 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6245 # Number of cycles cpu stages are processed. -system.cpu.activity 14.945197 # Percentage of cycles cpu is active +system.cpu.timesIdled 424 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35694 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6248 # Number of cycles cpu stages are processed. +system.cpu.activity 14.896762 # Percentage of cycles cpu is active system.cpu.comLoads 715 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1115 # Number of Branches instructions committed @@ -265,39 +288,39 @@ system.cpu.committedInsts 5327 # Nu system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) -system.cpu.cpi 7.844190 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 7.873475 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 7.844190 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127483 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 7.873475 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127009 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.127483 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 37146 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.127009 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 37302 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.104198 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 38591 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3195 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.646102 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 38753 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.258412 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 40811 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.333317 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 38629 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 11.062896 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 38748 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3194 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 7.615278 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 38908 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 3034 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 7.233799 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 40966 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 976 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 2.327023 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 38785 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.555162 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 7.527061 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 142.907558 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 142.644710 # Cycle average of tags in use system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.065292 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 142.907558 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.069779 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.069779 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 142.644710 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.069651 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.069651 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.142090 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 2807 # Number of tag accesses system.cpu.icache.tags.data_accesses 2807 # Number of data accesses @@ -313,12 +336,12 @@ system.cpu.icache.demand_misses::cpu.inst 366 # n system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses system.cpu.icache.overall_misses::total 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25613500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25613500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25613500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25613500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25613500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25613500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25482750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25482750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25482750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25482750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25482750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25482750 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses @@ -331,12 +354,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.290938 system.cpu.icache.demand_miss_rate::total 0.290938 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.290938 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.290938 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69982.240437 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69982.240437 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69982.240437 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69982.240437 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69982.240437 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69982.240437 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69625 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69625 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69625 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69625 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69625 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69625 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -357,26 +380,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20868000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20868000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20868000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20868000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20868000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20868000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20711750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20711750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20711750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20711750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20711750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20711750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71711.340206 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71711.340206 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71711.340206 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71711.340206 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71711.340206 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71711.340206 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71174.398625 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71174.398625 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71174.398625 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71174.398625 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71174.398625 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71174.398625 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1304965897 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 1300112062 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution @@ -391,21 +414,21 @@ system.cpu.toL2Bus.data_through_bus 27264 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 486500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 485750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 217250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 216250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 169.400750 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 169.087834 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.324573 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 27.076177 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004343 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000826 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005170 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.075458 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 27.012376 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004336 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005160 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 342 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id @@ -432,17 +455,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20549500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3769000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24318500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6227750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6227750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20549500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9996750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30546250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20549500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9996750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30546250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20393250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4031000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24424250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6031750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6031750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20393250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10062750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30456000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20393250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10062750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30456000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -465,17 +488,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71105.536332 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71113.207547 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71106.725146 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76885.802469 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76885.802469 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71105.536332 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74602.611940 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72213.356974 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71105.536332 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74602.611940 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72213.356974 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70564.878893 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76056.603774 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71415.935673 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74466.049383 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74466.049383 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70564.878893 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75095.149254 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70564.878893 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75095.149254 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -495,17 +518,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16936000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3114000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20050000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5232250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5232250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16936000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8346250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25282250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16936000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8346250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25282250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16781250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3376000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20157250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5037250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5037250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16781250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8413250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25194500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16781250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8413250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25194500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -517,27 +540,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58602.076125 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58754.716981 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58625.730994 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64595.679012 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64595.679012 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58602.076125 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62285.447761 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59768.912530 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58602.076125 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62285.447761 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59768.912530 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58066.608997 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63698.113208 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58939.327485 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62188.271605 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62188.271605 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58066.608997 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62785.447761 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59561.465721 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58066.608997 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62785.447761 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59561.465721 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 85.407936 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 85.369033 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 85.407936 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020852 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020852 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 85.369033 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020842 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020842 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id @@ -560,14 +583,14 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4332750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4332750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 29231250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 29231250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33564000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33564000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33564000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33564000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4594750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4594750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 29091500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 29091500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33686250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33686250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33686250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33686250 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -584,19 +607,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71028.688525 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71028.688525 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70777.845036 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70777.845036 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70810.126582 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70810.126582 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 70810.126582 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 70810.126582 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 792 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75323.770492 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75323.770492 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70439.467312 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70439.467312 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71068.037975 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71068.037975 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71068.037975 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71068.037975 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.548387 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.387097 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -616,14 +639,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3835500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3835500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6311250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6311250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10146750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10146750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10146750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10146750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4097500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4097500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6115250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6115250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10212750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10212750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10212750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10212750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -632,14 +655,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71027.777778 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71027.777778 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77916.666667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77916.666667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75161.111111 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75161.111111 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75161.111111 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75161.111111 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75879.629630 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75879.629630 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75496.913580 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75496.913580 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75650 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75650 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75650 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75650 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |