diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-30 09:35:32 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-30 09:35:32 -0400 |
| commit | 10b70d54529f0a44dc088c9271d9ecf3a8ffe68a (patch) | |
| tree | 482dff6407c0b1c8cf1711f33d8ecad6acbf6c7f /tests/quick/se/00.hello/ref/sparc/linux | |
| parent | 9cbe1cb653428a2298644579ddf82c46272683d4 (diff) | |
| download | gem5-10b70d54529f0a44dc088c9271d9ecf3a8ffe68a.tar.xz | |
stats: Update stats for unified cache configuration
This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.
Diffstat (limited to 'tests/quick/se/00.hello/ref/sparc/linux')
| -rw-r--r-- | tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt | 508 |
1 files changed, 254 insertions, 254 deletions
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 8df237734..0f666ffe1 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 17991500 # Number of ticks simulated -final_tick 17991500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000016 # Number of seconds simulated +sim_ticks 16282500 # Number of ticks simulated +final_tick 16282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 44971 # Simulator instruction rate (inst/s) -host_op_rate 44961 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 151823718 # Simulator tick rate (ticks/s) -host_mem_usage 222708 # Number of bytes of host memory used +host_inst_rate 46082 # Simulator instruction rate (inst/s) +host_op_rate 46072 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 140796560 # Simulator tick rate (ticks/s) +host_mem_usage 222960 # Number of bytes of host memory used host_seconds 0.12 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 18496 # Nu system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1028041019 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 476669538 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1504710558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1028041019 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1028041019 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1028041019 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 476669538 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1504710558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1135943498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 526700445 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1662643943 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1135943498 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1135943498 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1135943498 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 526700445 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1662643943 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 423 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 17940000 # Total gap between requests +system.physmem.totGap 16231000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 281 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 254 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,48 +164,48 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1964422 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11356422 # Sum of mem lat for all requests +system.physmem.totQLat 2301921 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11301921 # Sum of mem lat for all requests system.physmem.totBusLat 1692000 # Total cycles spent in databus access -system.physmem.totBankLat 7700000 # Total cycles spent in bank access -system.physmem.avgQLat 4644.02 # Average queueing delay per request -system.physmem.avgBankLat 18203.31 # Average bank access latency per request +system.physmem.totBankLat 7308000 # Total cycles spent in bank access +system.physmem.avgQLat 5441.89 # Average queueing delay per request +system.physmem.avgBankLat 17276.60 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26847.33 # Average memory access latency -system.physmem.avgRdBW 1504.71 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26718.49 # Average memory access latency +system.physmem.avgRdBW 1662.64 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1504.71 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1662.64 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.40 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.63 # Average read queue length over time +system.physmem.busUtil 10.39 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.69 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 336 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 79.43 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42411.35 # Average gap between requests +system.physmem.avgGap 38371.16 # Average gap between requests system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 35984 # number of cpu cycles simulated +system.cpu.numCycles 32566 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 1634 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 1036 # Number of conditional branches predicted +system.cpu.branch_predictor.lookups 1630 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 1034 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 901 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1169 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 438 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 1165 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 436 # Number of BTB hits system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 37.467921 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 505 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 1129 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5626 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 37.424893 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 503 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 1127 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5631 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9614 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9619 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1682 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 1675 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 1483 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 334 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 504 # Number of Branches Incorrectly Predicted As Not Taken). @@ -216,12 +216,12 @@ system.cpu.execution_unit.executions 3966 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9941 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9640 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 470 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29760 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6224 # Number of cycles cpu stages are processed. -system.cpu.activity 17.296576 # Percentage of cycles cpu is active +system.cpu.timesIdled 478 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 26364 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6202 # Number of cycles cpu stages are processed. +system.cpu.activity 19.044402 # Percentage of cycles cpu is active system.cpu.comLoads 715 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1115 # Number of Branches instructions committed @@ -233,144 +233,144 @@ system.cpu.committedInsts 5327 # Nu system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) -system.cpu.cpi 6.755022 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.113385 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.755022 # CPI: Total CPI of All Threads -system.cpu.ipc 0.148038 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.113385 # CPI: Total CPI of All Threads +system.cpu.ipc 0.163576 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.148038 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 31416 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4568 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 12.694531 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 32782 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3202 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 8.898399 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 32940 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 3044 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 8.459315 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 35002 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 982 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.728991 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 32815 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 3169 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 8.806692 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.163576 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 28007 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4559 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 13.999263 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 29377 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3189 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 9.792422 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 29532 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 3034 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 9.316465 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 31591 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 2.993920 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29408 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 3158 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 9.697230 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 138.057869 # Cycle average of tags in use -system.cpu.icache.total_refs 829 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 143.411463 # Cycle average of tags in use +system.cpu.icache.total_refs 814 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2.848797 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2.797251 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 138.057869 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.067411 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.067411 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 829 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 829 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 829 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 829 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 829 # number of overall hits -system.cpu.icache.overall_hits::total 829 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 348 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 348 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 348 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 348 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 348 # number of overall misses -system.cpu.icache.overall_misses::total 348 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18017500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18017500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18017500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18017500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18017500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18017500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1177 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1177 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1177 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1177 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1177 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1177 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.295667 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.295667 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.295667 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.295667 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.295667 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.295667 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51774.425287 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 51774.425287 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 51774.425287 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 51774.425287 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 51774.425287 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 51774.425287 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 143.411463 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.070025 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.070025 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 814 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 814 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 814 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 814 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 814 # number of overall hits +system.cpu.icache.overall_hits::total 814 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses +system.cpu.icache.overall_misses::total 364 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18418500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18418500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18418500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18418500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18418500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18418500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1178 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1178 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1178 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1178 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1178 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1178 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.308998 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.308998 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.308998 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.308998 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.308998 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.308998 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50600.274725 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 50600.274725 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 50600.274725 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 50600.274725 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 50600.274725 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 50600.274725 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 148 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 49.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 57 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 57 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 57 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 57 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15219500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15219500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15219500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15219500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15219500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15219500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247239 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.247239 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247239 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.247239 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247239 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.247239 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52300.687285 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52300.687285 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52300.687285 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52300.687285 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52300.687285 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52300.687285 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15194000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15194000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15194000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15194000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15194000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15194000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.247029 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.247029 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.247029 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52213.058419 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52213.058419 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52213.058419 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52213.058419 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52213.058419 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52213.058419 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 83.298060 # Cycle average of tags in use -system.cpu.dcache.total_refs 1045 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 85.214129 # Cycle average of tags in use +system.cpu.dcache.total_refs 914 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 7.740741 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 6.770370 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 83.298060 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020336 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020336 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 85.214129 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020804 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020804 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 391 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 391 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1045 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1045 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1045 # number of overall hits -system.cpu.dcache.overall_hits::total 1045 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 260 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 914 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 914 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 914 # number of overall hits +system.cpu.dcache.overall_hits::total 914 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 282 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 282 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 343 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 343 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 343 # number of overall misses -system.cpu.dcache.overall_misses::total 343 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3323500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3323500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13337500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13337500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16661000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16661000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16661000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16661000 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 413 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 413 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses +system.cpu.dcache.overall_misses::total 474 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3347500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3347500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19185000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19185000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22532500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22532500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22532500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22532500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -381,36 +381,36 @@ system.cpu.dcache.overall_accesses::cpu.data 1388 system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085315 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.085315 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.419019 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.419019 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.247118 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.247118 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.247118 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.247118 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54483.606557 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54483.606557 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47296.099291 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47296.099291 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48574.344023 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48574.344023 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 48574.344023 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 48574.344023 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3752 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 83.377778 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.613670 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.613670 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54877.049180 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54877.049180 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46452.784504 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46452.784504 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47536.919831 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47536.919831 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47536.919831 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47536.919831 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 405 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.656250 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 201 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 201 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 208 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 208 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 208 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 208 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 332 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 332 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses @@ -419,14 +419,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3959500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3959500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6874500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6874500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6874500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6874500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2939000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2939000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4153500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4153500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7092500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7092500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7092500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7092500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -435,26 +435,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53981.481481 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53981.481481 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48882.716049 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48882.716049 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50922.222222 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 50922.222222 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50922.222222 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 50922.222222 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54425.925926 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54425.925926 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51277.777778 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51277.777778 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52537.037037 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52537.037037 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52537.037037 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52537.037037 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 163.809669 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 169.991473 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 137.551022 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 26.258647 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004198 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000801 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004999 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 142.874602 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 27.116871 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004360 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000828 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005188 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -475,17 +475,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14901000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2848500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17749500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3876000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3876000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14901000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6724500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21625500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14901000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6724500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21625500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14875500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2872500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17748000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4070000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4070000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14875500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6942500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21818000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14875500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6942500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21818000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -508,17 +508,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51560.553633 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53745.283019 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51899.122807 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47851.851852 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47851.851852 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51560.553633 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50182.835821 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51124.113475 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51560.553633 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50182.835821 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51124.113475 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51472.318339 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54198.113208 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51894.736842 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50246.913580 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50246.913580 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51472.318339 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51809.701493 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51579.196217 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51472.318339 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51809.701493 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51579.196217 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,17 +538,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11259441 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2182574 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13442015 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2846130 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2846130 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11259441 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5028704 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16288145 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11259441 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5028704 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16288145 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11235436 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2207572 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13443008 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3066568 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3066568 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11235436 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5274140 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16509576 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11235436 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5274140 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16509576 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -560,17 +560,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38960.003460 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41180.641509 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39304.137427 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35137.407407 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35137.407407 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38960.003460 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37527.641791 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38506.252955 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38960.003460 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37527.641791 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38506.252955 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38876.941176 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41652.301887 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39307.040936 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37858.864198 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37858.864198 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38876.941176 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39359.253731 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39029.730496 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38876.941176 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39359.253731 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39029.730496 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |