diff options
| author | Nathan Binkert <nate@binkert.org> | 2012-05-09 11:52:14 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2012-05-09 11:52:14 -0700 |
| commit | 4a644767c58754339965cecc5d85853255652a30 (patch) | |
| tree | e435caa3b1ba7f5e395c58ca0fdfdfa91804d2dd /tests/quick/se/00.hello/ref/sparc | |
| parent | 55411f7f713a42f67552a9621051fae8f7869648 (diff) | |
| download | gem5-4a644767c58754339965cecc5d85853255652a30.tar.xz | |
stats: update stats for no_value -> nan
Lots of accumulated older changes too.
Diffstat (limited to 'tests/quick/se/00.hello/ref/sparc')
13 files changed, 136 insertions, 127 deletions
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini index eed996339..61b03b911 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU @@ -41,7 +40,6 @@ choiceCtrBits=2 choicePredictorSize=8192 clock=500 cpu_id=0 -dataMemPort=dcache_port defer_registration=false div16Latency=1 div16RepeatRate=1 @@ -56,7 +54,6 @@ do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 -fetchMemPort=icache_port functionTrace=false functionTraceStart=0 function_trace=false @@ -94,7 +91,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -115,7 +112,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=SparcTLB @@ -123,7 +120,7 @@ size=64 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -144,7 +141,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=SparcInterrupts @@ -155,7 +152,7 @@ size=64 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -175,8 +172,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -186,7 +183,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -218,15 +216,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout index cf9740828..19ecb4795 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 12 2012 17:18:12 -gem5 started Feb 12 2012 18:17:30 -gem5 executing on zizzer -command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing +gem5 compiled May 8 2012 15:05:42 +gem5 started May 8 2012 15:36:55 +gem5 executing on piton +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello World!Exiting @ tick 18196500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 440f0bc0a..5aea2d352 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000018 # Nu sim_ticks 18196500 # Number of ticks simulated final_tick 18196500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90140 # Simulator instruction rate (inst/s) -host_op_rate 90112 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 306976844 # Simulator tick rate (ticks/s) -host_mem_usage 211148 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 72963 # Simulator instruction rate (inst/s) +host_op_rate 72948 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 248531385 # Simulator tick rate (ticks/s) +host_mem_usage 221204 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated sim_ops 5340 # Number of ops (including micro ops) simulated system.physmem.bytes_read 27072 # Number of bytes read from this memory @@ -24,30 +24,6 @@ system.cpu.workload.num_syscalls 11 # Nu system.cpu.numCycles 36394 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9708 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 421 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30167 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6227 # Number of cycles cpu stages are processed. -system.cpu.activity 17.109963 # Percentage of cycles cpu is active -system.cpu.comLoads 716 # Number of Load instructions committed -system.cpu.comStores 673 # Number of Store instructions committed -system.cpu.comBranches 1116 # Number of Branches instructions committed -system.cpu.comNops 173 # Number of Nop instructions committed -system.cpu.comNonSpec 106 # Number of Non-Speculative instructions committed -system.cpu.comInts 2537 # Number of Integer instructions committed -system.cpu.comFloats 0 # Number of Floating Point instructions committed -system.cpu.committedInsts 5340 # Number of Instructions committed (Per-Thread) -system.cpu.committedOps 5340 # Number of Ops committed (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) -system.cpu.committedInsts_total 5340 # Number of Instructions committed (Total) -system.cpu.cpi 6.815356 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 6.815356 # CPI: Total CPI of All Threads -system.cpu.ipc 0.146727 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.146727 # IPC: Total IPC of All Threads system.cpu.branch_predictor.lookups 1617 # Number of BP lookups system.cpu.branch_predictor.condPredicted 1022 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 899 # Number of conditional branches incorrect @@ -74,6 +50,30 @@ system.cpu.execution_unit.mispredictPct 74.910394 # Pe system.cpu.execution_unit.executions 3979 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed +system.cpu.contextSwitches 1 # Number of context switches +system.cpu.threadCycles 9708 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode +system.cpu.timesIdled 421 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 30167 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6227 # Number of cycles cpu stages are processed. +system.cpu.activity 17.109963 # Percentage of cycles cpu is active +system.cpu.comLoads 716 # Number of Load instructions committed +system.cpu.comStores 673 # Number of Store instructions committed +system.cpu.comBranches 1116 # Number of Branches instructions committed +system.cpu.comNops 173 # Number of Nop instructions committed +system.cpu.comNonSpec 106 # Number of Non-Speculative instructions committed +system.cpu.comInts 2537 # Number of Integer instructions committed +system.cpu.comFloats 0 # Number of Floating Point instructions committed +system.cpu.committedInsts 5340 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 5340 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 5340 # Number of Instructions committed (Total) +system.cpu.cpi 6.815356 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.smt_cpi nan # CPI: Total SMT-CPI +system.cpu.cpi_total 6.815356 # CPI: Total CPI of All Threads +system.cpu.ipc 0.146727 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.smt_ipc nan # IPC: Total SMT-IPC +system.cpu.ipc_total 0.146727 # IPC: Total IPC of All Threads system.cpu.stage0.idleCycles 31821 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4573 # Number of cycles 1+ instructions are processed. system.cpu.stage0.utilization 12.565258 # Percentage of cycles stage was utilized (processing insts). @@ -132,7 +132,7 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 106000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 35333.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -214,7 +214,7 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 2259500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 50211.111111 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -322,8 +322,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 289 # number of ReadReq MSHR misses diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini index 328fede16..3550cbb34 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU @@ -39,6 +38,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -57,8 +57,8 @@ system=system tracer=system.cpu.tracer width=1 workload=system.cpu.workload -dcache_port=system.membus.port[3] -icache_port=system.membus.port[2] +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] [system.cpu.dtb] type=SparcTLB @@ -101,15 +101,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +master=system.physmem.port[0] +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout index 51b7334cc..467d94a16 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:33 -gem5 started Feb 11 2012 13:55:13 -gem5 executing on zizzer -command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-atomic +gem5 compiled May 8 2012 15:05:42 +gem5 started May 8 2012 15:36:55 +gem5 executing on piton +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello World!Exiting @ tick 2701000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt index 12998e98f..a0bb29684 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000003 # Nu sim_ticks 2701000 # Number of ticks simulated final_tick 2701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 963329 # Simulator instruction rate (inst/s) -host_op_rate 960313 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 484321069 # Simulator tick rate (ticks/s) -host_mem_usage 201636 # Number of bytes of host memory used +host_inst_rate 660534 # Simulator instruction rate (inst/s) +host_op_rate 659359 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 332979355 # Simulator tick rate (ticks/s) +host_mem_usage 211860 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated sim_ops 5340 # Number of ops (including micro ops) simulated diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini index bca11e4c0..7c9c9a36b 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.sys_port_proxy.port[0] +system_port=system.sys_port_proxy.slave[0] [system.cpu] type=TimingSimpleCPU @@ -54,8 +53,8 @@ progress_interval=0 system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.l1_cntrl0.sequencer.port[1] -icache_port=system.l1_cntrl0.sequencer.port[0] +dcache_port=system.l1_cntrl0.sequencer.slave[1] +icache_port=system.l1_cntrl0.sequencer.slave[0] [system.cpu.dtb] type=SparcTLB @@ -165,23 +164,25 @@ dcache=system.l1_cntrl0.cacheMemory deadlock_threshold=500000 icache=system.l1_cntrl0.cacheMemory max_outstanding_requests=16 -physmem=system.physmem ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system using_network_tester=false using_ruby_tester=false version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port +slave=system.cpu.icache_port system.cpu.dcache_port [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30 latency_var=0 null=false range=0:134217727 zero=false -port=system.l1_cntrl0.sequencer.physMemPort system.sys_port_proxy.physMemPort [system.ruby] type=RubySystem @@ -272,11 +273,12 @@ ruby_system=system.ruby [system.sys_port_proxy] type=RubyPortProxy access_phys_mem=true -physmem=system.physmem ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system using_network_tester=false using_ruby_tester=false version=0 -physMemPort=system.physmem.port[1] -port=system.system_port +slave=system.system_port diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats index d48e9e1d8..5940396eb 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jan/23/2012 04:24:20 +Real time: May/08/2012 15:36:55 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.26 -Virtual_time_in_minutes: 0.00433333 -Virtual_time_in_hours: 7.22222e-05 -Virtual_time_in_days: 3.00926e-06 +Virtual_time_in_seconds: 0.28 +Virtual_time_in_minutes: 0.00466667 +Virtual_time_in_hours: 7.77778e-05 +Virtual_time_in_days: 3.24074e-06 Ruby_current_time: 253364 Ruby_start_time: 0 Ruby_cycles: 253364 -mbytes_resident: 45.418 -mbytes_total: 219.465 -resident_ratio: 0.206949 +mbytes_resident: 48.3438 +mbytes_total: 226.668 +resident_ratio: 0.21328 ruby_cycles_executed: [ 253365 ] @@ -122,10 +122,10 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12012 -page_faults: 1 +page_reclaims: 12864 +page_faults: 0 swaps: 0 -block_inputs: 152 +block_inputs: 0 block_outputs: 88 Network Stats diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout index f70d252d3..dd8a0a7b3 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:33 -gem5 started Feb 11 2012 13:55:24 -gem5 executing on zizzer -command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing-ruby +gem5 compiled May 8 2012 15:05:42 +gem5 started May 8 2012 15:36:55 +gem5 executing on piton +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello World!Exiting @ tick 253364 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index a13bd4161..362724c03 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000253 # Nu sim_ticks 253364 # Number of ticks simulated final_tick 253364 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 70723 # Simulator instruction rate (inst/s) -host_op_rate 70707 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3354080 # Simulator tick rate (ticks/s) -host_mem_usage 222404 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 60301 # Simulator instruction rate (inst/s) +host_op_rate 60291 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2860139 # Simulator tick rate (ticks/s) +host_mem_usage 232112 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated sim_ops 5340 # Number of ops (including micro ops) simulated system.physmem.bytes_read 26135 # Number of bytes read from this memory diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini index a61827466..958c9bb97 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -16,7 +16,6 @@ load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 -physmem=system.physmem readfile= symbolfile= work_begin_ckpt_count=0 @@ -26,7 +25,7 @@ work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1 -system_port=system.membus.port[0] +system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU @@ -59,7 +58,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -80,7 +79,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.port[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=SparcTLB @@ -88,7 +87,7 @@ size=64 [system.cpu.icache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -109,7 +108,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.port[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=SparcInterrupts @@ -120,7 +119,7 @@ size=64 [system.cpu.l2cache] type=BaseCache -addr_range=0:18446744073709551615 +addr_ranges=0:18446744073709551615 assoc=2 block_size=64 forward_snoops=true @@ -140,8 +139,8 @@ tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] -mem_side=system.membus.port[2] +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=Bus @@ -151,7 +150,8 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer @@ -183,15 +183,18 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +master=system.physmem.port[0] +slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=PhysicalMemory +type=SimpleMemory +conf_table_reported=false file= +in_addr_map=true latency=30000 latency_var=0 null=false range=0:134217727 zero=false -port=system.membus.port[1] +port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout index 5f1c3c546..702411d18 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:33 -gem5 started Feb 11 2012 13:55:23 -gem5 executing on zizzer -command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing +gem5 compiled May 8 2012 15:05:42 +gem5 started May 8 2012 15:36:55 +gem5 executing on piton +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello World!Exiting @ tick 28206000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index e8bbbf4c9..d2987c02e 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 28206000 # Number of ticks simulated final_tick 28206000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 534426 # Simulator instruction rate (inst/s) -host_op_rate 533460 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2812998715 # Simulator tick rate (ticks/s) -host_mem_usage 210748 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 240215 # Simulator instruction rate (inst/s) +host_op_rate 240049 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1267195715 # Simulator tick rate (ticks/s) +host_mem_usage 220748 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated sim_ops 5340 # Number of ops (including micro ops) simulated system.physmem.bytes_read 24896 # Number of bytes read from this memory @@ -86,8 +86,8 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_misses::cpu.inst 257 # number of ReadReq MSHR misses @@ -162,8 +162,8 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses @@ -262,8 +262,8 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 255 # number of ReadReq MSHR misses |