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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-05-21 11:32:57 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-05-21 11:32:57 -0500 |
| commit | 5b49c3d255eb82089496f8a77d6ab50004b5a2c2 (patch) | |
| tree | c27568e48e0c39d9943830a870dbf234273c5b7d /tests/quick/se/00.hello/ref/sparc | |
| parent | 4ef466cc8a6890a63f504cec02a65ed3f6386e12 (diff) | |
| download | gem5-5b49c3d255eb82089496f8a77d6ab50004b5a2c2.tar.xz | |
stats: updates statistics for ruby regressions
Diffstat (limited to 'tests/quick/se/00.hello/ref/sparc')
| -rw-r--r-- | tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats | 13 | ||||
| -rw-r--r-- | tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt | 19 |
2 files changed, 8 insertions, 24 deletions
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats index da8bc363f..97d6545aa 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats @@ -133,19 +133,6 @@ links_utilized_percent_switch_2: 5.96098 outgoing_messages_switch_2_link_1_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.l1_cntrl0.cacheMemory - system.ruby.l1_cntrl0.cacheMemory_total_misses: 1289 - system.ruby.l1_cntrl0.cacheMemory_total_demand_misses: 1289 - system.ruby.l1_cntrl0.cacheMemory_total_prefetches: 0 - system.ruby.l1_cntrl0.cacheMemory_total_sw_prefetches: 0 - system.ruby.l1_cntrl0.cacheMemory_total_hw_prefetches: 0 - - system.ruby.l1_cntrl0.cacheMemory_request_type_LD: 30.6439% - system.ruby.l1_cntrl0.cacheMemory_request_type_ST: 13.8867% - system.ruby.l1_cntrl0.cacheMemory_request_type_IFETCH: 55.4694% - - system.ruby.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 1289 100% - --- L1Cache --- - Event Counts - Load [715 ] 715 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index b4c8f8286..1ca0b6acd 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -4,19 +4,16 @@ sim_seconds 0.000108 # Nu sim_ticks 107952 # Number of ticks simulated final_tick 107952 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 19134 # Simulator instruction rate (inst/s) -host_op_rate 19132 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 387691 # Simulator tick rate (ticks/s) -host_mem_usage 158116 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host +host_inst_rate 36056 # Simulator instruction rate (inst/s) +host_op_rate 36051 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 730482 # Simulator tick rate (ticks/s) +host_mem_usage 160860 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated -system.ruby.l1_cntrl0.cacheMemory.num_data_array_reads 0 # number of data array reads -system.ruby.l1_cntrl0.cacheMemory.num_data_array_writes 0 # number of data array writes -system.ruby.l1_cntrl0.cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.ruby.l1_cntrl0.cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.ruby.l1_cntrl0.cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.ruby.l1_cntrl0.cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 107952 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started |