diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-01-20 08:12:02 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-01-20 08:12:02 -0500 |
| commit | de162ad96886cc78bd9c0fdb3417f8d8047f643b (patch) | |
| tree | da6e05cf52b09dbb2953cb9a2d01468253eb4c9c /tests/quick/se/00.hello/ref/sparc | |
| parent | 6096e2f9c11afbb57b78f985f8b8fe7e059821b0 (diff) | |
| download | gem5-de162ad96886cc78bd9c0fdb3417f8d8047f643b.tar.xz | |
tests: Remove deprecated InOrderCPU tests
This patch removes the three MIPS and SPARC regressions that use the
deprecated InOrderCPU.
This is the first step in completely removing the code from the tree,
avoiding confusion, and focusing all development efforts on the
MinorCPU. Brave new world.
Diffstat (limited to 'tests/quick/se/00.hello/ref/sparc')
4 files changed, 0 insertions, 1102 deletions
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini deleted file mode 100644 index a3c44273d..000000000 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini +++ /dev/null @@ -1,381 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -eventq_index=0 -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=InOrderCPU -children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -activity=0 -branchPred=system.cpu.branchPred -cachePorts=2 -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -div16Latency=1 -div16RepeatRate=1 -div24Latency=1 -div24RepeatRate=1 -div32Latency=1 -div32RepeatRate=1 -div8Latency=1 -div8RepeatRate=1 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fetchBuffSize=4 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -memBlockSize=64 -multLatency=1 -multRepeatRate=1 -numThreads=1 -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -stageTracing=false -stageWidth=4 -switched_out=false -system=system -threadModel=SMT -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=BranchPredictor -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -predType=tournament - -[system.cpu.dcache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=2 -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=SparcTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=2 -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=SparcInterrupts -eventq_index=0 - -[system.cpu.isa] -type=SparcISA -eventq_index=0 - -[system.cpu.itb] -type=SparcTLB -eventq_index=0 -size=64 - -[system.cpu.l2cache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=20 -is_top_level=false -max_miss_count=0 -mshrs=20 -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=20 -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -clk_domain=system.cpu_clk_domain -eventq_index=0 -header_cycles=1 -snoop_filter=Null -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/sparc/linux/hello -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -eventq_index=0 -header_cycles=1 -snoop_filter=Null -system=system -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=DRAMCtrl -IDD0=0.075000 -IDD02=0.000000 -IDD2N=0.050000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.000000 -IDD2P12=0.000000 -IDD3N=0.057000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.000000 -IDD3P12=0.000000 -IDD4R=0.187000 -IDD4R2=0.000000 -IDD4W=0.165000 -IDD4W2=0.000000 -IDD5=0.220000 -IDD52=0.000000 -IDD6=0.000000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaChCo -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -device_bus_width=8 -device_rowbuffer_size=1024 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -page_policy=open_adaptive -range=0:134217727 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=0 -tXPDLL=0 -tXS=0 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simerr b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simerr deleted file mode 100755 index 1a4f96712..000000000 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simerr +++ /dev/null @@ -1 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout deleted file mode 100755 index bce99f509..000000000 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout +++ /dev/null @@ -1,10 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 22 2014 17:04:27 -gem5 started Jan 22 2014 17:29:22 -gem5 executing on u200540-lin -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 20892500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt deleted file mode 100644 index 33e0e9c43..000000000 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ /dev/null @@ -1,710 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20927500 # Number of ticks simulated -final_tick 20927500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 82286 # Simulator instruction rate (inst/s) -host_op_rate 82268 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 323129777 # Simulator tick rate (ticks/s) -host_mem_usage 289972 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -sim_insts 5327 # Number of instructions simulated -sim_ops 5327 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory -system.physmem.bytes_read::total 27072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 18496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 18496 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory -system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 883813164 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 409795723 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1293608888 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 883813164 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 883813164 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 883813164 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 409795723 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1293608888 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 423 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 423 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 27072 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 27072 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24 # Per bank write bursts -system.physmem.perBankRdBursts::1 7 # Per bank write bursts -system.physmem.perBankRdBursts::2 1 # Per bank write bursts -system.physmem.perBankRdBursts::3 8 # Per bank write bursts -system.physmem.perBankRdBursts::4 0 # Per bank write bursts -system.physmem.perBankRdBursts::5 78 # Per bank write bursts -system.physmem.perBankRdBursts::6 80 # Per bank write bursts -system.physmem.perBankRdBursts::7 62 # Per bank write bursts -system.physmem.perBankRdBursts::8 35 # Per bank write bursts -system.physmem.perBankRdBursts::9 18 # Per bank write bursts -system.physmem.perBankRdBursts::10 10 # Per bank write bursts -system.physmem.perBankRdBursts::11 52 # Per bank write bursts -system.physmem.perBankRdBursts::12 12 # Per bank write bursts -system.physmem.perBankRdBursts::13 21 # Per bank write bursts -system.physmem.perBankRdBursts::14 7 # Per bank write bursts -system.physmem.perBankRdBursts::15 8 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20858000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 423 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 74 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 323.459459 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 226.188766 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 265.234411 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 17 22.97% 22.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 21.62% 44.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11 14.86% 59.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 13 17.57% 77.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 8 10.81% 87.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4 5.41% 93.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 6.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 74 # Bytes accessed per row activation -system.physmem.totQLat 3885750 # Total ticks spent queuing -system.physmem.totMemAccLat 11817000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2115000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9186.17 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27936.17 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1293.61 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1293.61 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.11 # Data bus utilization in percentage -system.physmem.busUtilRead 10.11 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 339 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.14 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 49309.69 # Average gap between requests -system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1497600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10702035 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 111750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 13784220 # Total energy per rank (pJ) -system.physmem_0.averagePower 870.628138 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 116500 # Time in different power states -system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15209750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 196560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 107250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1107600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10576350 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 222000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13226880 # Total energy per rank (pJ) -system.physmem_1.averagePower 835.425865 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 328000 # Time in different power states -system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14998250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1636 # Number of BP lookups -system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1343 # Number of BTB lookups -system.cpu.branchPred.BTBHits 584 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 43.484736 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 41856 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 985 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5611 # Number of Reads from Int. Register File -system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9599 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File -system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1718 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 1472 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 376 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 458 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 834 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 281 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 74.798206 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 3957 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed -system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9651 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 424 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35611 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6245 # Number of cycles cpu stages are processed. -system.cpu.activity 14.920203 # Percentage of cycles cpu is active -system.cpu.comLoads 715 # Number of Load instructions committed -system.cpu.comStores 673 # Number of Store instructions committed -system.cpu.comBranches 1115 # Number of Branches instructions committed -system.cpu.comNops 173 # Number of Nop instructions committed -system.cpu.comNonSpec 106 # Number of Non-Speculative instructions committed -system.cpu.comInts 2526 # Number of Integer instructions committed -system.cpu.comFloats 0 # Number of Floating Point instructions committed -system.cpu.committedInsts 5327 # Number of Instructions committed (Per-Thread) -system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) -system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) -system.cpu.cpi 7.857331 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 7.857331 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127270 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.127270 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 37216 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.085627 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 38661 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3195 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.633314 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 38823 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.246273 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 40881 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.329415 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 38699 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.542527 # Percentage of cycles stage was utilized (processing insts). -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 85.369863 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 85.369863 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020842 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020842 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 260 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 914 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 914 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 914 # number of overall hits -system.cpu.dcache.overall_hits::total 914 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 413 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 413 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses -system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4588750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4588750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 28972250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 28972250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33561000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33561000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33561000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33561000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085315 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.085315 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.613670 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.613670 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75225.409836 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75225.409836 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70150.726392 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70150.726392 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70803.797468 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70803.797468 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 70803.797468 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 70803.797468 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.387097 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 332 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 332 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4091500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4091500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6091750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6091750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10183250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10183250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10183250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10183250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75768.518519 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75768.518519 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75206.790123 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75206.790123 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75431.481481 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75431.481481 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75431.481481 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75431.481481 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 142.708262 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.065292 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 142.708262 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.069682 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.069682 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.142090 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2807 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2807 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 892 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 892 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 892 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 892 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 892 # number of overall hits -system.cpu.icache.overall_hits::total 892 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses -system.cpu.icache.overall_misses::total 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25412000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25412000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25412000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25412000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25412000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25412000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1258 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1258 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1258 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.290938 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.290938 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.290938 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.290938 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.290938 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.290938 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69431.693989 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69431.693989 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69431.693989 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69431.693989 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69431.693989 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69431.693989 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 75 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 75 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 75 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 75 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20639500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20639500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20639500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20639500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20639500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20639500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70926.116838 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70926.116838 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70926.116838 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70926.116838 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70926.116838 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70926.116838 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 169.161112 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 342 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.008772 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.138007 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 27.023105 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004338 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000825 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005162 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 342 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010437 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3831 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3831 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits -system.cpu.l2cache.overall_hits::total 3 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 289 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 342 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 289 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 423 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses -system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20321000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4025000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24346000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6008250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6008250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20321000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10033250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30354250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20321000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10033250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30354250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 426 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 426 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993127 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981481 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.991304 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993127 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.992958 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70314.878893 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75943.396226 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71187.134503 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74175.925926 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74175.925926 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70314.878893 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74875 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71759.456265 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70314.878893 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74875 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71759.456265 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 289 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 342 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 289 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 423 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16706500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3370000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20076500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5013250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5013250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16706500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8383250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25089750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16706500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8383250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25089750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57807.958478 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63584.905660 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58703.216374 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61891.975309 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61891.975309 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57807.958478 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62561.567164 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59313.829787 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57807.958478 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62561.567164 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59313.829787 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 852 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 27264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 426 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 426 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 426 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 486500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 216750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 342 # Transaction distribution -system.membus.trans_dist::ReadResp 342 # Transaction distribution -system.membus.trans_dist::ReadExReq 81 # Transaction distribution -system.membus.trans_dist::ReadExResp 81 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 846 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 846 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 27072 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 423 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 423 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 423 # Request fanout histogram -system.membus.reqLayer0.occupancy 501500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3931250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 18.8 # Layer utilization (%) - ----------- End Simulation Statistics ---------- |