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author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-06-10 06:46:20 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-06-10 06:46:20 -0500 |
commit | 247e4e9ab41bafcfcbde725bb40e6a7b5628f1de (patch) | |
tree | b4312f540772ef437b5b962cc1fff4bb54d90ce4 /tests/quick/se/00.hello/ref/sparc | |
parent | d32ee94231251b8d07bb811142f6759f8655962b (diff) | |
download | gem5-247e4e9ab41bafcfcbde725bb40e6a7b5628f1de.tar.xz |
stats: updates due to changes to ruby
Ruby's controller statistics have been mostly moved to stats.txt now.
Plus stats.txt for solaris/t1000-simple-atomic and arm/20.parser are
also being updated.
Diffstat (limited to 'tests/quick/se/00.hello/ref/sparc')
-rw-r--r-- | tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats | 151 | ||||
-rw-r--r-- | tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt | 49 |
2 files changed, 55 insertions, 145 deletions
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats index 97d6545aa..0cadf0143 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats @@ -1,4 +1,4 @@ -Real time: Mar/06/2013 20:57:13 +Real time: Jun/08/2013 14:17:53 Profiler Stats -------------- @@ -7,20 +7,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.57 -Virtual_time_in_minutes: 0.0095 -Virtual_time_in_hours: 0.000158333 -Virtual_time_in_days: 6.59722e-06 +Virtual_time_in_seconds: 0.49 +Virtual_time_in_minutes: 0.00816667 +Virtual_time_in_hours: 0.000136111 +Virtual_time_in_days: 5.6713e-06 Ruby_current_time: 107952 Ruby_start_time: 0 Ruby_cycles: 107952 -mbytes_resident: 55.75 -mbytes_total: 154.406 -resident_ratio: 0.361111 - -ruby_cycles_executed: [ 107953 ] +mbytes_resident: 55.6289 +mbytes_total: 144.984 +resident_ratio: 0.383743 Busy Controller Counts: L1Cache-0:0 @@ -64,7 +62,6 @@ Request vs. RubySystem State Profile -------------------------------- -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- @@ -85,10 +82,10 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12080 -page_faults: 2 +page_reclaims: 11996 +page_faults: 0 swaps: 0 -block_inputs: 32 +block_inputs: 0 block_outputs: 88 Network Stats @@ -133,129 +130,3 @@ links_utilized_percent_switch_2: 5.96098 outgoing_messages_switch_2_link_1_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1 - --- L1Cache --- - - Event Counts - -Load [715 ] 715 -Ifetch [5370 ] 5370 -Store [673 ] 673 -Data [1289 ] 1289 -Fwd_GETX [0 ] 0 -Inv [0 ] 0 -Replacement [1285 ] 1285 -Writeback_Ack [1285 ] 1285 -Writeback_Nack [0 ] 0 - - - Transitions - -I Load [395 ] 395 -I Ifetch [715 ] 715 -I Store [179 ] 179 -I Inv [0 ] 0 -I Replacement [0 ] 0 - -II Writeback_Nack [0 ] 0 - -M Load [320 ] 320 -M Ifetch [4655 ] 4655 -M Store [494 ] 494 -M Fwd_GETX [0 ] 0 -M Inv [0 ] 0 -M Replacement [1285 ] 1285 - -MI Fwd_GETX [0 ] 0 -MI Inv [0 ] 0 -MI Writeback_Ack [1285 ] 1285 -MI Writeback_Nack [0 ] 0 - -MII Fwd_GETX [0 ] 0 - -IS Data [1110 ] 1110 - -IM Data [179 ] 179 - -Memory controller: system.ruby.dir_cntrl0.memBuffer: - memory_total_requests: 2574 - memory_reads: 1289 - memory_writes: 1285 - memory_refreshes: 750 - memory_total_request_delays: 1873 - memory_delays_per_request: 0.727661 - memory_delays_in_input_queue: 0 - memory_delays_behind_head_of_bank_queue: 2 - memory_delays_stalled_at_head_of_bank_queue: 1871 - memory_stalls_for_bank_busy: 758 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 69 - memory_stalls_for_bus: 992 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 52 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 166 40 36 48 109 42 63 241 50 34 16 26 60 64 38 46 30 88 202 144 40 58 22 20 60 120 136 125 84 134 166 66 - - --- Directory --- - - Event Counts - -GETX [1289 ] 1289 -GETS [0 ] 0 -PUTX [1285 ] 1285 -PUTX_NotOwner [0 ] 0 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -Memory_Data [1289 ] 1289 -Memory_Ack [1285 ] 1285 - - - Transitions - -I GETX [1289 ] 1289 -I PUTX_NotOwner [0 ] 0 -I DMA_READ [0 ] 0 -I DMA_WRITE [0 ] 0 - -M GETX [0 ] 0 -M PUTX [1285 ] 1285 -M PUTX_NotOwner [0 ] 0 -M DMA_READ [0 ] 0 -M DMA_WRITE [0 ] 0 - -M_DRD GETX [0 ] 0 -M_DRD PUTX [0 ] 0 - -M_DWR GETX [0 ] 0 -M_DWR PUTX [0 ] 0 - -M_DWRI GETX [0 ] 0 -M_DWRI Memory_Ack [0 ] 0 - -M_DRDI GETX [0 ] 0 -M_DRDI Memory_Ack [0 ] 0 - -IM GETX [0 ] 0 -IM GETS [0 ] 0 -IM PUTX [0 ] 0 -IM PUTX_NotOwner [0 ] 0 -IM DMA_READ [0 ] 0 -IM DMA_WRITE [0 ] 0 -IM Memory_Data [1289 ] 1289 - -MI GETX [0 ] 0 -MI GETS [0 ] 0 -MI PUTX [0 ] 0 -MI PUTX_NotOwner [0 ] 0 -MI DMA_READ [0 ] 0 -MI DMA_WRITE [0 ] 0 -MI Memory_Ack [1285 ] 1285 - -ID GETX [0 ] 0 -ID GETS [0 ] 0 -ID PUTX [0 ] 0 -ID PUTX_NotOwner [0 ] 0 -ID DMA_READ [0 ] 0 -ID DMA_WRITE [0 ] 0 -ID Memory_Data [0 ] 0 - -ID_W GETX [0 ] 0 -ID_W GETS [0 ] 0 -ID_W PUTX [0 ] 0 -ID_W PUTX_NotOwner [0 ] 0 -ID_W DMA_READ [0 ] 0 -ID_W DMA_WRITE [0 ] 0 -ID_W Memory_Ack [0 ] 0 - diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index 1ca0b6acd..87117a3bf 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -4,16 +4,31 @@ sim_seconds 0.000108 # Nu sim_ticks 107952 # Number of ticks simulated final_tick 107952 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 36056 # Simulator instruction rate (inst/s) -host_op_rate 36051 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 730482 # Simulator tick rate (ticks/s) -host_mem_usage 160860 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 37306 # Simulator instruction rate (inst/s) +host_op_rate 37301 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 755806 # Simulator tick rate (ticks/s) +host_mem_usage 148468 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses +system.ruby.dir_cntrl0.memBuffer.memReq 2574 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 1289 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 1285 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 750 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 1871 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memBankQ 2 # Delay behind the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 1873 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.727661 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 758 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 992 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 52 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 69 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 166 6.45% 6.45% | 40 1.55% 8.00% | 36 1.40% 9.40% | 48 1.86% 11.27% | 109 4.23% 15.50% | 42 1.63% 17.13% | 63 2.45% 19.58% | 241 9.36% 28.94% | 50 1.94% 30.89% | 34 1.32% 32.21% | 16 0.62% 32.83% | 26 1.01% 33.84% | 60 2.33% 36.17% | 64 2.49% 38.66% | 38 1.48% 40.13% | 46 1.79% 41.92% | 30 1.17% 43.08% | 88 3.42% 46.50% | 202 7.85% 54.35% | 144 5.59% 59.95% | 40 1.55% 61.50% | 58 2.25% 63.75% | 22 0.85% 64.61% | 20 0.78% 65.38% | 60 2.33% 67.72% | 120 4.66% 72.38% | 136 5.28% 77.66% | 125 4.86% 82.52% | 84 3.26% 85.78% | 134 5.21% 90.99% | 166 6.45% 97.44% | 66 2.56% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 2574 # Number of accesses per bank + system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 107952 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -37,5 +52,29 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 107952 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles +system.ruby.l1_cntrl0.Load 715 0.00% 0.00% +system.ruby.l1_cntrl0.Ifetch 5370 0.00% 0.00% +system.ruby.l1_cntrl0.Store 673 0.00% 0.00% +system.ruby.l1_cntrl0.Data 1289 0.00% 0.00% +system.ruby.l1_cntrl0.Replacement 1285 0.00% 0.00% +system.ruby.l1_cntrl0.Writeback_Ack 1285 0.00% 0.00% +system.ruby.l1_cntrl0.I.Load 395 0.00% 0.00% +system.ruby.l1_cntrl0.I.Ifetch 715 0.00% 0.00% +system.ruby.l1_cntrl0.I.Store 179 0.00% 0.00% +system.ruby.l1_cntrl0.M.Load 320 0.00% 0.00% +system.ruby.l1_cntrl0.M.Ifetch 4655 0.00% 0.00% +system.ruby.l1_cntrl0.M.Store 494 0.00% 0.00% +system.ruby.l1_cntrl0.M.Replacement 1285 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Writeback_Ack 1285 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data 1110 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Data 179 0.00% 0.00% +system.ruby.dir_cntrl0.GETX 1289 0.00% 0.00% +system.ruby.dir_cntrl0.PUTX 1285 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 1289 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 1285 0.00% 0.00% +system.ruby.dir_cntrl0.I.GETX 1289 0.00% 0.00% +system.ruby.dir_cntrl0.M.PUTX 1285 0.00% 0.00% +system.ruby.dir_cntrl0.IM.Memory_Data 1289 0.00% 0.00% +system.ruby.dir_cntrl0.MI.Memory_Ack 1285 0.00% 0.00% ---------- End Simulation Statistics ---------- |