Stats: Update stats for cache timings in cycles

This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.

1 files changed, 9 insertions, 9 deletions

diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
index 9881f90a7..a6445a723 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000019                       # Nu
 sim_ticks                                    18570500                       # Number of ticks simulated
 final_tick                                   18570500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  42410                       # Simulator instruction rate (inst/s)
-host_op_rate                                    42404                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              147804999                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 221464                       # Number of bytes of host memory used
-host_seconds                                     0.13                       # Real time elapsed on the host
+host_inst_rate                                  78205                       # Simulator instruction rate (inst/s)
+host_op_rate                                    78177                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              272440141                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214124                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        5327                       # Number of instructions simulated
 sim_ops                                          5327                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             18496                       # Number of bytes read from this memory
@@ -142,11 +142,11 @@ system.cpu.icache.demand_avg_miss_latency::total        55220
 system.cpu.icache.overall_avg_miss_latency::cpu.inst        55220                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::total        55220                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets       109000                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          218                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 36333.333333                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets    72.666667                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst           59                       # number of ReadReq MSHR hits
@@ -238,11 +238,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 55992.711370
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 55992.711370                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::total 55992.711370                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      2307000                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets         4614                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets              45                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 51266.666667                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   102.533333                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data            7                       # number of ReadReq MSHR hits