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authorNilay Vaish <nilay@cs.wisc.edu>2014-02-24 20:50:06 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2014-02-24 20:50:06 -0600
commit53f697a6166a6fe2787882f3448e73a8ebb849aa (patch)
tree34375d648a60551f8a1ccb0a4486a35665b5115a /tests/quick/se/00.hello/ref/sparc
parent8504b079b8e1c5bc4c14fa42ba224fe182ca43df (diff)
downloadgem5-53f697a6166a6fe2787882f3448e73a8ebb849aa.tar.xz
stats: updates due to c0db268f811b
Diffstat (limited to 'tests/quick/se/00.hello/ref/sparc')
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini16
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt12
2 files changed, 21 insertions, 7 deletions
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
index d08f49a30..ff0dc56e6 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000
[system]
type=System
-children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain
+children=clk_domain cpu physmem piobus ruby sys_port_proxy voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
@@ -132,6 +132,16 @@ latency_var=0
null=true
range=0:134217727
+[system.piobus]
+type=NoncoherentBus
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+use_default_range=false
+width=8
+master=system.ruby.l1_cntrl0.sequencer.pio_slave_port
+slave=system.ruby.l1_cntrl0.sequencer.pio_master_port system.ruby.l1_cntrl0.sequencer.mem_master_port
+
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
@@ -251,6 +261,9 @@ system=system
using_network_tester=false
using_ruby_tester=false
version=0
+mem_master_port=system.piobus.slave[1]
+pio_master_port=system.piobus.slave[0]
+pio_slave_port=system.piobus.master[0]
slave=system.cpu.icache_port system.cpu.dcache_port
[system.ruby.memctrl_clk_domain]
@@ -345,7 +358,6 @@ ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
-using_network_tester=false
using_ruby_tester=false
version=0
slave=system.system_port
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
index 2370dec63..e608505da 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
@@ -4,15 +4,17 @@ sim_seconds 0.000108 # Nu
sim_ticks 107952 # Number of ticks simulated
final_tick 107952 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 31490 # Simulator instruction rate (inst/s)
-host_op_rate 31486 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 638004 # Simulator tick rate (ticks/s)
-host_mem_usage 182480 # Number of bytes of host memory used
-host_seconds 0.17 # Real time elapsed on the host
+host_inst_rate 1705 # Simulator instruction rate (inst/s)
+host_op_rate 1705 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 34543 # Simulator tick rate (ticks/s)
+host_mem_usage 182496 # Number of bytes of host memory used
+host_seconds 3.13 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
+system.piobus.throughput 0 # Throughput (bytes/s)
+system.piobus.data_through_bus 0 # Total data (bytes)
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message