stats: Cumulative stats update

This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.

The main reason for bundling them up is to minimise the changeset
size.

1 files changed, 43 insertions, 44 deletions

diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
index 7c9257554..cfacb8ad4 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000020                       # Nu
 sim_ticks                                    19639500                       # Number of ticks simulated
 final_tick                                   19639500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  28578                       # Simulator instruction rate (inst/s)
-host_op_rate                                    51768                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              104294046                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 245432                       # Number of bytes of host memory used
-host_seconds                                     0.19                       # Real time elapsed on the host
+host_inst_rate                                  30549                       # Simulator instruction rate (inst/s)
+host_op_rate                                    55338                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              111488682                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 243516                       # Number of bytes of host memory used
+host_seconds                                     0.18                       # Real time elapsed on the host
 sim_insts                                        5380                       # Number of instructions simulated
 sim_ops                                          9747                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             17536                       # Number of bytes read from this memory
@@ -27,14 +27,15 @@ system.physmem.bw_inst_read::total          892894422                       # In
 system.physmem.bw_total::cpu.inst           892894422                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data           462740905                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total             1355635327                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                           417                       # Total number of read requests seen
-system.physmem.writeReqs                            0                       # Total number of write requests seen
-system.physmem.cpureqs                            417                       # Reqs generatd by CPU via cache - shady
+system.physmem.readReqs                           417                       # Total number of read requests accepted by DRAM controller
+system.physmem.writeReqs                            0                       # Total number of write requests accepted by DRAM controller
+system.physmem.readBursts                         417                       # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
+system.physmem.writeBursts                          0                       # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
 system.physmem.bytesRead                        26624                       # Total number of bytes read from memory
 system.physmem.bytesWritten                         0                       # Total number of bytes written to memory
 system.physmem.bytesConsumedRd                  26624                       # bytesRead derated as per pkt->getSize()
 system.physmem.bytesConsumedWr                      0                       # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ                        0                       # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by write Q
 system.physmem.neitherReadNorWrite                  0                       # Reqs where no action is needed
 system.physmem.perBankRdReqs::0                    34                       # Track reads on a per bank basis
 system.physmem.perBankRdReqs::1                     1                       # Track reads on a per bank basis
@@ -195,11 +196,9 @@ system.membus.trans_dist::ReadExReq                77                       # Tr
 system.membus.trans_dist::ReadExResp               77                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          833                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count_system.cpu.l2cache.mem_side::total          833                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::system.physmem.port          833                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                    833                       # Packet count per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        26624                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total        26624                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size::system.physmem.port        26624                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.tot_pkt_size::total               26624                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.data_through_bus                  26624                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
@@ -478,12 +477,12 @@ system.cpu.toL2Bus.trans_dist::ReadReq            342                       # Tr
 system.cpu.toL2Bus.trans_dist::ReadResp           341                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           77                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           77                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side          550                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side          287                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count                      837                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side        17600                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side         9152                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size                 26752                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side          550                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side          287                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total               837                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17600                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9152                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size::total          26752                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.data_through_bus             26752                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
 system.cpu.toL2Bus.reqLayer0.occupancy         209500                       # Layer occupancy (ticks)
@@ -492,15 +491,15 @@ system.cpu.toL2Bus.respLayer0.occupancy        463250                       # La
 system.cpu.toL2Bus.respLayer0.utilization          2.4                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        239750                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
-system.cpu.icache.tags.replacements                      0                       # number of replacements
-system.cpu.icache.tags.tagsinuse                130.740950                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                     1608                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                    275                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                   5.847273                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     130.740950                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.063838                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.063838                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements                 0                       # number of replacements
+system.cpu.icache.tags.tagsinuse           130.740950                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs                1608                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               275                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs              5.847273                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   130.740950                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.063838                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.063838                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst         1608                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            1608                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          1608                       # number of demand (read+write) hits
@@ -576,17 +575,17 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 69288.181818
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69288.181818                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 69288.181818                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements                     0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse               163.561658                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                       2                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                   339                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  0.005900                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    130.812999                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data     32.748659                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.replacements                0                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse          163.561658                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs                  2                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs              339                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.005900                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   130.812999                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    32.748659                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003992                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.000999                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.004992                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.004992                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
@@ -704,15 +703,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55924.270073
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61298.951049                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57767.386091                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                      0                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                 82.722336                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                     2341                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                    143                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                  16.370629                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data      82.722336                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.020196                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.020196                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements                 0                       # number of replacements
+system.cpu.dcache.tags.tagsinuse            82.722336                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs                2341                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs               143                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             16.370629                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data    82.722336                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.020196                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.020196                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data         1483                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1483                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          858                       # number of WriteReq hits