diff options
| author | Joel Hestness <jthestness@gmail.com> | 2015-08-14 01:19:34 -0500 |
|---|---|---|
| committer | Joel Hestness <jthestness@gmail.com> | 2015-08-14 01:19:34 -0500 |
| commit | 93c173a95e985d6b1fd413a9cfb5a3f8839135c0 (patch) | |
| tree | ba783208d31069c39e34601286ce33dcc212899f /tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt | |
| parent | 905c0b347c785d07b606b6a9f3c6bbdf8ebe96a7 (diff) | |
| download | gem5-93c173a95e985d6b1fd413a9cfb5a3f8839135c0.tar.xz | |
stats: Bump for MessageBuffer, cache latency changes
Diffstat (limited to 'tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt')
| -rw-r--r-- | tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt | 454 |
1 files changed, 227 insertions, 227 deletions
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 478e12e63..10e4434eb 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000107 # Number of seconds simulated -sim_ticks 107256 # Number of ticks simulated -final_tick 107256 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000088 # Number of seconds simulated +sim_ticks 87948 # Number of ticks simulated +final_tick 87948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 57113 # Simulator instruction rate (inst/s) -host_op_rate 103447 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1138055 # Simulator tick rate (ticks/s) -host_mem_usage 467864 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 39587 # Simulator instruction rate (inst/s) +host_op_rate 71707 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 646904 # Simulator tick rate (ticks/s) +host_mem_usage 417864 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1377 # system.mem_ctrls.num_reads::total 1377 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 1373 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 1373 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 821660327 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 821660327 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 819273514 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 819273514 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1640933841 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1640933841 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 1002046664 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1002046664 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 999135853 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 999135853 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 2001182517 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 2001182517 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1377 # Number of read requests accepted system.mem_ctrls.writeReqs 1373 # Number of write requests accepted system.mem_ctrls.readBursts 1377 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 1373 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 43264 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 44864 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 43264 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 40320 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 47808 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 39936 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 88128 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 87872 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 701 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 674 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 747 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 722 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 56 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 59 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 6 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 12 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 54 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 56 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 43 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 70 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 29 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 129 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 124 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 9 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 52 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 55 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 37 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 64 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 25 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 119 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 121 # Per bank write bursts system.mem_ctrls.perBankRdBursts::11 21 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 2 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 34 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 21 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 8 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 31 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 50 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 30 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 51 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 6 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 11 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 54 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 54 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 41 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 72 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 30 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 129 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 129 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 21 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 7 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 52 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 50 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 36 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 66 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 25 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 120 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 125 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 23 # Per bank write bursts system.mem_ctrls.perBankWrBursts::12 2 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 36 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 21 # Per bank write bursts system.mem_ctrls.perBankWrBursts::14 8 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 32 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 31 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 107152 # Total gap between requests +system.mem_ctrls.totGap 87868 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 1373 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 676 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 630 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -135,24 +135,24 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 10 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 45 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 41 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 8 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 41 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 38 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 38 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 38 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 38 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 38 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 38 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -184,93 +184,93 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 276 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 306.782609 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 194.488181 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 303.473845 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 80 28.99% 28.99% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 80 28.99% 57.97% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 33 11.96% 69.93% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 22 7.97% 77.90% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 18 6.52% 84.42% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 7 2.54% 86.96% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 7 2.54% 89.49% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 4 1.45% 90.94% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 25 9.06% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 276 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 41 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 16.243902 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 16.023325 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 3.314970 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 1 2.44% 2.44% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 16 39.02% 41.46% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 18 43.90% 85.37% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 5 12.20% 97.56% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::34-35 1 2.44% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 41 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 41 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.487805 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.459950 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.003044 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 32 78.05% 78.05% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 2 4.88% 82.93% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 3 7.32% 90.24% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 4 9.76% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 41 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 9573 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 22417 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3380 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 14.16 # Average queueing delay per DRAM burst +system.mem_ctrls.bytesPerActivate::samples 271 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 293.313653 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 193.377642 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 283.497497 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 72 26.57% 26.57% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 83 30.63% 57.20% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 37 13.65% 70.85% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 23 8.49% 79.34% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 21 7.75% 87.08% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 5 1.85% 88.93% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 7 2.58% 91.51% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 3 1.11% 92.62% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 20 7.38% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 271 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 38 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 16.289474 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 16.048466 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 3.463383 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 1 2.63% 2.63% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 15 39.47% 42.11% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 16 42.11% 84.21% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 4 10.53% 94.74% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 1 2.63% 97.37% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::34-35 1 2.63% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 38 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 38 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.421053 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.397539 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.919212 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 31 81.58% 81.58% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 5 13.16% 94.74% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 2 5.26% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 38 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 9303 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 21273 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3150 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 14.77 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 33.16 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 403.37 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 403.37 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 821.66 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 819.27 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 33.77 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 458.45 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 454.09 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1002.05 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 999.14 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 6.30 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 3.15 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 3.15 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 7.13 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 3.58 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 3.55 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.88 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 443 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 622 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 65.53 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 88.98 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 38.96 # Average gap between requests -system.mem_ctrls.pageHitRate 77.45 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 703080 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 390600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 3319680 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 2685312 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 57105108 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 10794600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 81609660 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 804.210371 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 17627 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states +system.mem_ctrls.avgWrQLen 25.04 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 420 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 556 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 66.67 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 85.41 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 31.95 # Average gap between requests +system.mem_ctrls.pageHitRate 76.19 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 657720 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 365400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 3407040 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 2623104 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 5594160 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 51093432 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 6724800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 70465656 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 820.264661 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 10886 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 2860 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 80485 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 72174 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 1292760 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 718200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 4630080 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 3805056 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 62793936 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 5804400 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 85655712 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 844.081594 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 9408 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states +system.mem_ctrls_1.actEnergy 1368360 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 760200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 4268160 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 3680640 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 5594160 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 54919728 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3368400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 73959648 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 860.936931 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 5575 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 2860 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 88844 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 77782 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.apic_clk_domain.clock 16 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 107256 # number of cpu cycles simulated +system.cpu.numCycles 87948 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5381 # Number of instructions committed @@ -290,10 +290,10 @@ system.cpu.num_cc_register_writes 3536 # nu system.cpu.num_mem_refs 1988 # number of memory refs system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions -system.cpu.num_idle_cycles 0.999991 # Number of idle cycles -system.cpu.num_busy_cycles 107255.000009 # Number of busy cycles -system.cpu.not_idle_fraction 0.999991 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000009 # Percentage of idle cycles +system.cpu.num_idle_cycles 0.999989 # Number of idle cycles +system.cpu.num_busy_cycles 87947.000011 # Number of busy cycles +system.cpu.not_idle_fraction 0.999989 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000011 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction @@ -346,32 +346,32 @@ system.ruby.outstanding_req_hist::total 8852 system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8852 -system.ruby.latency_hist::mean 11.116584 -system.ruby.latency_hist::gmean 4.640695 -system.ruby.latency_hist::stdev 22.790037 -system.ruby.latency_hist | 8597 97.12% 97.12% | 214 2.42% 99.54% | 29 0.33% 99.86% | 4 0.05% 99.91% | 5 0.06% 99.97% | 3 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::mean 8.935382 +system.ruby.latency_hist::gmean 1.815175 +system.ruby.latency_hist::stdev 22.675647 +system.ruby.latency_hist | 8624 97.42% 97.42% | 191 2.16% 99.58% | 24 0.27% 99.85% | 5 0.06% 99.91% | 2 0.02% 99.93% | 6 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8852 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 system.ruby.hit_latency_hist::samples 7475 -system.ruby.hit_latency_hist::mean 3 -system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7475 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::mean 1 +system.ruby.hit_latency_hist::gmean 1 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 7475 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.hit_latency_hist::total 7475 system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1377 -system.ruby.miss_latency_hist::mean 55.177197 -system.ruby.miss_latency_hist::gmean 49.553011 -system.ruby.miss_latency_hist::stdev 32.253276 -system.ruby.miss_latency_hist | 1122 81.48% 81.48% | 214 15.54% 97.02% | 29 2.11% 99.13% | 4 0.29% 99.42% | 5 0.36% 99.78% | 3 0.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::mean 52.012346 +system.ruby.miss_latency_hist::gmean 46.179478 +system.ruby.miss_latency_hist::stdev 33.292581 +system.ruby.miss_latency_hist | 1149 83.44% 83.44% | 191 13.87% 97.31% | 24 1.74% 99.06% | 5 0.36% 99.42% | 2 0.15% 99.56% | 6 0.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1377 system.ruby.Directory.incomplete_times 1376 system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.409898 +system.ruby.network.routers0.percent_links_utilized 7.817119 system.ruby.network.routers0.msg_count.Control::2 1377 system.ruby.network.routers0.msg_count.Data::2 1373 system.ruby.network.routers0.msg_count.Response_Data::4 1377 @@ -380,7 +380,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 11016 system.ruby.network.routers0.msg_bytes.Data::2 98856 system.ruby.network.routers0.msg_bytes.Response_Data::4 99144 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.routers1.percent_links_utilized 6.409898 +system.ruby.network.routers1.percent_links_utilized 7.817119 system.ruby.network.routers1.msg_count.Control::2 1377 system.ruby.network.routers1.msg_count.Data::2 1373 system.ruby.network.routers1.msg_count.Response_Data::4 1377 @@ -389,7 +389,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 11016 system.ruby.network.routers1.msg_bytes.Data::2 98856 system.ruby.network.routers1.msg_bytes.Response_Data::4 99144 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.routers2.percent_links_utilized 6.409898 +system.ruby.network.routers2.percent_links_utilized 7.817119 system.ruby.network.routers2.msg_count.Control::2 1377 system.ruby.network.routers2.msg_count.Data::2 1373 system.ruby.network.routers2.msg_count.Response_Data::4 1377 @@ -406,32 +406,32 @@ system.ruby.network.msg_byte.Control 33048 system.ruby.network.msg_byte.Data 296568 system.ruby.network.msg_byte.Response_Data 297432 system.ruby.network.msg_byte.Writeback_Control 32952 -system.ruby.network.routers0.throttle0.link_utilization 6.417357 +system.ruby.network.routers0.throttle0.link_utilization 7.826215 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 99144 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.routers0.throttle1.link_utilization 6.402439 +system.ruby.network.routers0.throttle1.link_utilization 7.808023 system.ruby.network.routers0.throttle1.msg_count.Control::2 1377 system.ruby.network.routers0.throttle1.msg_count.Data::2 1373 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11016 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 98856 -system.ruby.network.routers1.throttle0.link_utilization 6.402439 +system.ruby.network.routers1.throttle0.link_utilization 7.808023 system.ruby.network.routers1.throttle0.msg_count.Control::2 1377 system.ruby.network.routers1.throttle0.msg_count.Data::2 1373 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11016 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 98856 -system.ruby.network.routers1.throttle1.link_utilization 6.417357 +system.ruby.network.routers1.throttle1.link_utilization 7.826215 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1377 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1373 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 99144 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.routers2.throttle0.link_utilization 6.417357 +system.ruby.network.routers2.throttle0.link_utilization 7.826215 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1377 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1373 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 99144 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.routers2.throttle1.link_utilization 6.402439 +system.ruby.network.routers2.throttle1.link_utilization 7.808023 system.ruby.network.routers2.throttle1.msg_count.Control::2 1377 system.ruby.network.routers2.throttle1.msg_count.Data::2 1373 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11016 @@ -446,105 +446,105 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 # system.ruby.delayVCHist.vnet_2::samples 1373 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 1373 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 1373 # delay histogram for vnet_2 -system.ruby.LD.latency_hist::bucket_size 64 -system.ruby.LD.latency_hist::max_bucket 639 +system.ruby.LD.latency_hist::bucket_size 32 +system.ruby.LD.latency_hist::max_bucket 319 system.ruby.LD.latency_hist::samples 1045 -system.ruby.LD.latency_hist::mean 24.565550 -system.ruby.LD.latency_hist::gmean 10.818925 -system.ruby.LD.latency_hist::stdev 28.664875 -system.ruby.LD.latency_hist | 965 92.34% 92.34% | 74 7.08% 99.43% | 4 0.38% 99.81% | 1 0.10% 99.90% | 0 0.00% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::mean 22.607656 +system.ruby.LD.latency_hist::gmean 5.952637 +system.ruby.LD.latency_hist::stdev 28.358291 +system.ruby.LD.latency_hist | 546 52.25% 52.25% | 420 40.19% 92.44% | 70 6.70% 99.14% | 2 0.19% 99.33% | 2 0.19% 99.52% | 4 0.38% 99.90% | 0 0.00% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist::total 1045 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 system.ruby.LD.hit_latency_hist::samples 546 -system.ruby.LD.hit_latency_hist::mean 3 -system.ruby.LD.hit_latency_hist::gmean 3.000000 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 546 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::mean 1 +system.ruby.LD.hit_latency_hist::gmean 1 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 546 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.hit_latency_hist::total 546 -system.ruby.LD.miss_latency_hist::bucket_size 64 -system.ruby.LD.miss_latency_hist::max_bucket 639 +system.ruby.LD.miss_latency_hist::bucket_size 32 +system.ruby.LD.miss_latency_hist::max_bucket 319 system.ruby.LD.miss_latency_hist::samples 499 -system.ruby.LD.miss_latency_hist::mean 48.162325 -system.ruby.LD.miss_latency_hist::gmean 44.026667 -system.ruby.LD.miss_latency_hist::stdev 25.587548 -system.ruby.LD.miss_latency_hist | 419 83.97% 83.97% | 74 14.83% 98.80% | 4 0.80% 99.60% | 1 0.20% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::mean 46.250501 +system.ruby.LD.miss_latency_hist::gmean 41.916728 +system.ruby.LD.miss_latency_hist::stdev 24.776985 +system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 420 84.17% 84.17% | 70 14.03% 98.20% | 2 0.40% 98.60% | 2 0.40% 99.00% | 4 0.80% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 499 system.ruby.ST.latency_hist::bucket_size 64 system.ruby.ST.latency_hist::max_bucket 639 system.ruby.ST.latency_hist::samples 935 -system.ruby.ST.latency_hist::mean 16.914439 -system.ruby.ST.latency_hist::gmean 6.394076 -system.ruby.ST.latency_hist::stdev 28.735394 -system.ruby.ST.latency_hist | 895 95.72% 95.72% | 33 3.53% 99.25% | 3 0.32% 99.57% | 2 0.21% 99.79% | 1 0.11% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::mean 15.124064 +system.ruby.ST.latency_hist::gmean 2.829099 +system.ruby.ST.latency_hist::stdev 31.003309 +system.ruby.ST.latency_hist | 897 95.94% 95.94% | 28 2.99% 98.93% | 5 0.53% 99.47% | 3 0.32% 99.79% | 0 0.00% 99.79% | 2 0.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist::total 935 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 system.ruby.ST.hit_latency_hist::samples 681 -system.ruby.ST.hit_latency_hist::mean 3 -system.ruby.ST.hit_latency_hist::gmean 3.000000 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 681 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::mean 1 +system.ruby.ST.hit_latency_hist::gmean 1 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 681 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.hit_latency_hist::total 681 system.ruby.ST.miss_latency_hist::bucket_size 64 system.ruby.ST.miss_latency_hist::max_bucket 639 system.ruby.ST.miss_latency_hist::samples 254 -system.ruby.ST.miss_latency_hist::mean 54.220472 -system.ruby.ST.miss_latency_hist::gmean 48.633946 -system.ruby.ST.miss_latency_hist::stdev 33.614512 -system.ruby.ST.miss_latency_hist | 214 84.25% 84.25% | 33 12.99% 97.24% | 3 1.18% 98.43% | 2 0.79% 99.21% | 1 0.39% 99.61% | 1 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::mean 52.992126 +system.ruby.ST.miss_latency_hist::gmean 45.979346 +system.ruby.ST.miss_latency_hist::stdev 39.646660 +system.ruby.ST.miss_latency_hist | 216 85.04% 85.04% | 28 11.02% 96.06% | 5 1.97% 98.03% | 3 1.18% 99.21% | 0 0.00% 99.21% | 2 0.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 254 system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6864 -system.ruby.IFETCH.latency_hist::mean 8.284237 -system.ruby.IFETCH.latency_hist::gmean 3.905930 -system.ruby.IFETCH.latency_hist::stdev 19.803554 -system.ruby.IFETCH.latency_hist | 6729 98.03% 98.03% | 107 1.56% 99.59% | 22 0.32% 99.91% | 1 0.01% 99.93% | 4 0.06% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::mean 6.015589 +system.ruby.IFETCH.latency_hist::gmean 1.426336 +system.ruby.IFETCH.latency_hist::stdev 19.173758 +system.ruby.IFETCH.latency_hist | 6753 98.38% 98.38% | 91 1.33% 99.71% | 13 0.19% 99.90% | 1 0.01% 99.91% | 2 0.03% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6864 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 system.ruby.IFETCH.hit_latency_hist::samples 6241 -system.ruby.IFETCH.hit_latency_hist::mean 3 -system.ruby.IFETCH.hit_latency_hist::gmean 3.000000 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6241 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::mean 1 +system.ruby.IFETCH.hit_latency_hist::gmean 1 +system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 6241 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.hit_latency_hist::total 6241 system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 623 -system.ruby.IFETCH.miss_latency_hist::mean 61.219904 -system.ruby.IFETCH.miss_latency_hist::gmean 54.926300 -system.ruby.IFETCH.miss_latency_hist::stdev 35.218812 -system.ruby.IFETCH.miss_latency_hist | 488 78.33% 78.33% | 107 17.17% 95.51% | 22 3.53% 99.04% | 1 0.16% 99.20% | 4 0.64% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::mean 56.260032 +system.ruby.IFETCH.miss_latency_hist::gmean 50.022291 +system.ruby.IFETCH.miss_latency_hist::stdev 35.712767 +system.ruby.IFETCH.miss_latency_hist | 512 82.18% 82.18% | 91 14.61% 96.79% | 13 2.09% 98.88% | 1 0.16% 99.04% | 2 0.32% 99.36% | 4 0.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 623 system.ruby.RMW_Read.latency_hist::bucket_size 4 system.ruby.RMW_Read.latency_hist::max_bucket 39 system.ruby.RMW_Read.latency_hist::samples 8 -system.ruby.RMW_Read.latency_hist::mean 6.875000 -system.ruby.RMW_Read.latency_hist::gmean 4.063647 +system.ruby.RMW_Read.latency_hist::mean 4.875000 +system.ruby.RMW_Read.latency_hist::gmean 1.542211 system.ruby.RMW_Read.latency_hist::stdev 10.960155 system.ruby.RMW_Read.latency_hist | 7 87.50% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00% | 0 0.00% 100.00% system.ruby.RMW_Read.latency_hist::total 8 system.ruby.RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.RMW_Read.hit_latency_hist::max_bucket 9 system.ruby.RMW_Read.hit_latency_hist::samples 7 -system.ruby.RMW_Read.hit_latency_hist::mean 3 -system.ruby.RMW_Read.hit_latency_hist::gmean 3.000000 -system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.hit_latency_hist::mean 1 +system.ruby.RMW_Read.hit_latency_hist::gmean 1 +system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.RMW_Read.hit_latency_hist::total 7 system.ruby.RMW_Read.miss_latency_hist::bucket_size 4 system.ruby.RMW_Read.miss_latency_hist::max_bucket 39 system.ruby.RMW_Read.miss_latency_hist::samples 1 -system.ruby.RMW_Read.miss_latency_hist::mean 34 -system.ruby.RMW_Read.miss_latency_hist::gmean 34.000000 +system.ruby.RMW_Read.miss_latency_hist::mean 32 +system.ruby.RMW_Read.miss_latency_hist::gmean 32 system.ruby.RMW_Read.miss_latency_hist::stdev nan system.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% system.ruby.RMW_Read.miss_latency_hist::total 1 system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1377 -system.ruby.Directory.miss_mach_latency_hist::mean 55.177197 -system.ruby.Directory.miss_mach_latency_hist::gmean 49.553011 -system.ruby.Directory.miss_mach_latency_hist::stdev 32.253276 -system.ruby.Directory.miss_mach_latency_hist | 1122 81.48% 81.48% | 214 15.54% 97.02% | 29 2.11% 99.13% | 4 0.29% 99.42% | 5 0.36% 99.78% | 3 0.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::mean 52.012346 +system.ruby.Directory.miss_mach_latency_hist::gmean 46.179478 +system.ruby.Directory.miss_mach_latency_hist::stdev 33.292581 +system.ruby.Directory.miss_mach_latency_hist | 1149 83.44% 83.44% | 191 13.87% 97.31% | 24 1.74% 99.06% | 5 0.36% 99.42% | 2 0.15% 99.56% | 6 0.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1377 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 @@ -572,35 +572,35 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 7 system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 -system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 -system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32 +system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 499 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 48.162325 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 44.026667 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 25.587548 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 419 83.97% 83.97% | 74 14.83% 98.80% | 4 0.80% 99.60% | 1 0.20% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 46.250501 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 41.916728 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 24.776985 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 420 84.17% 84.17% | 70 14.03% 98.20% | 2 0.40% 98.60% | 2 0.40% 99.00% | 4 0.80% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 499 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 254 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 54.220472 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 48.633946 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 33.614512 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 214 84.25% 84.25% | 33 12.99% 97.24% | 3 1.18% 98.43% | 2 0.79% 99.21% | 1 0.39% 99.61% | 1 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 52.992126 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 45.979346 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 39.646660 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 216 85.04% 85.04% | 28 11.02% 96.06% | 5 1.97% 98.03% | 3 1.18% 99.21% | 0 0.00% 99.21% | 2 0.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist::total 254 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 623 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 61.219904 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 54.926300 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 35.218812 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 488 78.33% 78.33% | 107 17.17% 95.51% | 22 3.53% 99.04% | 1 0.16% 99.20% | 4 0.64% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 56.260032 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 50.022291 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 35.712767 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 512 82.18% 82.18% | 91 14.61% 96.79% | 13 2.09% 98.88% | 1 0.16% 99.04% | 2 0.32% 99.36% | 4 0.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 623 system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::bucket_size 4 system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::max_bucket 39 system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::samples 1 -system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::mean 34 -system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::gmean 34.000000 +system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::mean 32 +system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::gmean 32 system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::stdev nan system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::total 1 |