regressions: x86: stats updates due to new x87 insts

4 files changed, 50 insertions, 52 deletions

diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
index 5e5659352..3bdc04678 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
@@ -1,24 +1,24 @@
-Real time: Jan/23/2013 16:34:52
+Real time: Mar/11/2013 13:21:59
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.54
-Virtual_time_in_minutes: 0.009
-Virtual_time_in_hours:   0.00015
-Virtual_time_in_days:    6.25e-06
+Virtual_time_in_seconds: 0.6
+Virtual_time_in_minutes: 0.01
+Virtual_time_in_hours:   0.000166667
+Virtual_time_in_days:    6.94444e-06
 
 Ruby_current_time: 121759
 Ruby_start_time: 0
 Ruby_cycles: 121759
 
-mbytes_resident: 66.3984
-mbytes_total: 290.648
-resident_ratio: 0.22849
+mbytes_resident: 66.582
+mbytes_total: 163.426
+resident_ratio: 0.407486
 
 ruby_cycles_executed: [ 121760 ]
 
@@ -29,17 +29,17 @@ Directory-0:0
 
 Busy Bank Count:0
 
-sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8852 average:     1 | standard deviation: 0 | 0 8852 ]
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8853 average:     1 | standard deviation: 0 | 0 8853 ]
 
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
-miss_latency: [binsize: 1 max: 125 count: 8851 average: 12.7565 | standard deviation: 22.8681 | 0 0 0 7474 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 313 433 492 10 6 5 9 6 11 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 9 16 39 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
-miss_latency_LD: [binsize: 1 max: 101 count: 1044 average: 33.113 | standard deviation: 31.8551 | 0 0 0 545 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 2 97 201 150 1 3 2 0 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 3 5 22 0 0 1 0 0 0 0 0 1 ]
-miss_latency_ST: [binsize: 1 max: 92 count: 935 average: 20.0877 | standard deviation: 28.194 | 0 0 0 681 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 62 106 3 0 0 2 0 3 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 3 9 ]
-miss_latency_IFETCH: [binsize: 1 max: 125 count: 6864 average: 8.66404 | standard deviation: 18.01 | 0 0 0 6241 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 157 170 235 6 3 3 7 5 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 8 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency: [binsize: 1 max: 125 count: 8852 average: 12.755 | standard deviation: 22.8655 | 0 0 0 7475 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 312 432 494 10 6 5 9 7 11 0 1 0 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 9 16 40 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_LD: [binsize: 1 max: 101 count: 1045 average: 33.0842 | standard deviation: 31.8534 | 0 0 0 546 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 2 97 201 150 1 3 2 0 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 3 5 22 0 0 1 0 0 0 0 0 1 ]
+miss_latency_ST: [binsize: 1 max: 92 count: 935 average: 20.0845 | standard deviation: 28.1878 | 0 0 0 681 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 61 107 3 0 0 2 1 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 3 9 ]
+miss_latency_IFETCH: [binsize: 1 max: 125 count: 6864 average: 8.6639 | standard deviation: 18.0088 | 0 0 0 6241 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 156 170 236 6 3 3 7 5 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 miss_latency_RMW_Read: [binsize: 1 max: 65 count: 8 average: 10.75 | standard deviation: 21.9219 | 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
-miss_latency_L1Cache: [binsize: 1 max: 3 count: 7474 average:     3 | standard deviation: 0 | 0 0 0 7474 ]
-miss_latency_Directory: [binsize: 1 max: 125 count: 1377 average: 65.7124 | standard deviation: 6.32886 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 313 433 492 10 6 5 9 6 11 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 9 16 39 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_L1Cache: [binsize: 1 max: 3 count: 7475 average:     3 | standard deviation: 0 | 0 0 0 7475 ]
+miss_latency_Directory: [binsize: 1 max: 125 count: 1377 average: 65.7095 | standard deviation: 6.31582 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 312 432 494 10 6 5 9 7 11 0 1 0 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 9 16 40 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
@@ -50,12 +50,12 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average:
 miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average:     0 | standard deviation: 0 | 1 ]
 miss_latency_dir_first_response_to_completion: [binsize: 1 max: 61 count: 1 average:    61 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 imcomplete_dir_Times: 1376
-miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 545 average:     3 | standard deviation: 0 | 0 0 0 545 ]
+miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 546 average:     3 | standard deviation: 0 | 0 0 0 546 ]
 miss_latency_LD_Directory: [binsize: 1 max: 101 count: 499 average: 66.002 | standard deviation: 7.00186 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 2 97 201 150 1 3 2 0 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 3 5 22 0 0 1 0 0 0 0 0 1 ]
 miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 681 average:     3 | standard deviation: 0 | 0 0 0 681 ]
-miss_latency_ST_Directory: [binsize: 1 max: 92 count: 254 average: 65.9016 | standard deviation: 6.43269 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 62 106 3 0 0 2 0 3 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 3 9 ]
+miss_latency_ST_Directory: [binsize: 1 max: 92 count: 254 average: 65.8898 | standard deviation: 6.41669 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 61 107 3 0 0 2 1 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 3 9 ]
 miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 6241 average:     3 | standard deviation: 0 | 0 0 0 6241 ]
-miss_latency_IFETCH_Directory: [binsize: 1 max: 125 count: 623 average: 65.4045 | standard deviation: 5.68761 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 157 170 235 6 3 3 7 5 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 8 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
+miss_latency_IFETCH_Directory: [binsize: 1 max: 125 count: 623 average: 65.4029 | standard deviation: 5.66282 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 156 170 236 6 3 3 7 5 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 miss_latency_RMW_Read_L1Cache: [binsize: 1 max: 3 count: 7 average:     3 | standard deviation: 0 | 0 0 0 7 ]
 miss_latency_RMW_Read_Directory: [binsize: 1 max: 65 count: 1 average:    65 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
 
@@ -72,7 +72,6 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
 Message Delayed Cycles
 ----------------------
 Total_delay_cycles: [binsize: 1 max: 0 count: 2750 average:     0 | standard deviation: 0 | 2750 ]
-Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 2750 average:     0 | standard deviation: 0 | 2750 ]
   virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
   virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1377 average:     0 | standard deviation: 0 | 1377 ]
   virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1373 average:     0 | standard deviation: 0 | 1373 ]
@@ -89,7 +88,7 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 13733
+page_reclaims: 14769
 page_faults: 0
 swaps: 0
 block_inputs: 0
@@ -152,7 +151,7 @@ Cache Stats: system.ruby.l1_cntrl0.cacheMemory
 
  --- L1Cache ---
  - Event Counts -
-Load [1044 ] 1044
+Load [1045 ] 1045
 Ifetch [6864 ] 6864
 Store [943 ] 943
 Data [1377 ] 1377
@@ -171,7 +170,7 @@ I  Replacement [0 ] 0
 
 II  Writeback_Nack [0 ] 0
 
-M  Load [545 ] 545
+M  Load [546 ] 546
 M  Ifetch [6241 ] 6241
 M  Store [688 ] 688
 M  Fwd_GETX [0 ] 0
@@ -194,18 +193,18 @@ Memory controller: system.ruby.dir_cntrl0.memBuffer:
   memory_reads: 1377
   memory_writes: 1373
   memory_refreshes: 846
-  memory_total_request_delays: 1964
-  memory_delays_per_request: 0.714182
+  memory_total_request_delays: 1968
+  memory_delays_per_request: 0.715636
   memory_delays_in_input_queue: 0
-  memory_delays_behind_head_of_bank_queue: 4
-  memory_delays_stalled_at_head_of_bank_queue: 1960
-  memory_stalls_for_bank_busy: 826
+  memory_delays_behind_head_of_bank_queue: 3
+  memory_delays_stalled_at_head_of_bank_queue: 1965
+  memory_stalls_for_bank_busy: 823
   memory_stalls_for_random_busy: 0
   memory_stalls_for_anti_starvation: 0
-  memory_stalls_for_arbitration: 62
-  memory_stalls_for_bus: 1041
+  memory_stalls_for_arbitration: 65
+  memory_stalls_for_bus: 1044
   memory_stalls_for_tfaw: 0
-  memory_stalls_for_read_write_turnaround: 31
+  memory_stalls_for_read_write_turnaround: 33
   memory_stalls_for_read_read_turnaround: 0
   accesses_per_bank: 160  144  210  146  196  96  66  38  22  20  184  297  71  124  60  18  84  6  8  14  92  56  14  60  34  58  84  66  42  122  104  54  
 
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr
index 723b3760f..bbc0c797e 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr
@@ -1,7 +1,6 @@
-Warning: rounding error > tolerance
+warn: rounding error > tolerance
     0.072760 rounded to 0
-Warning: rounding error > tolerance
+warn: rounding error > tolerance
     0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fldcw_Mw' unimplemented
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
index 931a144eb..8c2cd3936 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-tim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 16:30:44
-gem5 started Jan 23 2013 16:34:52
+gem5 compiled Mar 11 2013 13:21:48
+gem5 started Mar 11 2013 13:21:58
 gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
index 4a0d16755..e2571982e 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
@@ -4,13 +4,13 @@ sim_seconds                                  0.000122                       # Nu
 sim_ticks                                      121759                       # Number of ticks simulated
 final_tick                                     121759                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  20307                       # Simulator instruction rate (inst/s)
-host_op_rate                                    36781                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 459428                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 167176                       # Number of bytes of host memory used
-host_seconds                                     0.27                       # Real time elapsed on the host
+host_inst_rate                                  25458                       # Simulator instruction rate (inst/s)
+host_op_rate                                    46114                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 575943                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 167352                       # Number of bytes of host memory used
+host_seconds                                     0.21                       # Real time elapsed on the host
 sim_insts                                        5381                       # Number of instructions simulated
-sim_ops                                          9747                       # Number of ops (including micro ops) simulated
+sim_ops                                          9748                       # Number of ops (including micro ops) simulated
 system.ruby.l1_cntrl0.cacheMemory.num_data_array_reads            0                       # number of data array reads
 system.ruby.l1_cntrl0.cacheMemory.num_data_array_writes            0                       # number of data array writes
 system.ruby.l1_cntrl0.cacheMemory.num_tag_array_reads            0                       # number of tag array reads
@@ -22,19 +22,19 @@ system.cpu.numCycles                           121759                       # nu
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        5381                       # Number of instructions committed
-system.cpu.committedOps                          9747                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  9653                       # Number of integer alu accesses
+system.cpu.committedOps                          9748                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  9655                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
 system.cpu.num_conditional_control_insts          899                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         9653                       # number of integer instructions
+system.cpu.num_int_insts                         9655                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads               24817                       # number of times the integer registers were read
-system.cpu.num_int_register_writes              11061                       # number of times the integer registers were written
+system.cpu.num_int_register_reads               24822                       # number of times the integer registers were read
+system.cpu.num_int_register_writes              11063                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          1987                       # number of memory refs
-system.cpu.num_load_insts                        1052                       # Number of load instructions
+system.cpu.num_mem_refs                          1988                       # number of memory refs
+system.cpu.num_load_insts                        1053                       # Number of load instructions
 system.cpu.num_store_insts                        935                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_busy_cycles                     121759                       # Number of busy cycles