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authorCurtis Dunham <Curtis.Dunham@arm.com>2016-07-21 17:19:18 +0100
committerCurtis Dunham <Curtis.Dunham@arm.com>2016-07-21 17:19:18 +0100
commit84f138ba96201431513eb2ae5f847389ac731aa2 (patch)
tree3aee721699295c85e4e0c2d3d4a6bb27595bfabd /tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
parenta288c94387b110112461ff5686fa727a43ddbe9c (diff)
downloadgem5-84f138ba96201431513eb2ae5f847389ac731aa2.tar.xz
stats: update references
Diffstat (limited to 'tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini')
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini72
1 files changed, 71 insertions, 1 deletions
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
index ca3cb5481..bc04df7fd 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
readfile=
symbolfile=
thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -94,12 +104,17 @@ addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -118,8 +133,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=262144
@@ -133,8 +153,13 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
num_squash_per_cycle=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
system=system
port=system.cpu.toL2Bus.slave[3]
@@ -145,12 +170,17 @@ addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -169,18 +199,28 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=131072
[system.cpu.interrupts]
type=X86LocalApic
clk_domain=system.cpu.apic_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
int_latency=1000
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=2305843009213693952
pio_latency=100000
+power_model=Null
system=system
int_master=system.membus.slave[2]
int_slave=system.membus.master[2]
@@ -200,8 +240,13 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
num_squash_per_cycle=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
system=system
port=system.cpu.toL2Bus.slave[2]
@@ -212,12 +257,17 @@ addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
@@ -236,8 +286,13 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=2097152
@@ -245,10 +300,15 @@ size=2097152
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
point_of_coherency=false
+power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -279,7 +339,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
kvmInSE=false
@@ -311,10 +371,15 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
point_of_coherency=true
+power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -329,11 +394,16 @@ type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
range=0:134217727
port=system.membus.master[0]