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author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-11 17:45:09 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-11 17:45:09 -0500 |
commit | 53a05978054ac9bb718e419a48371bd10c720267 (patch) | |
tree | 30ea67ba4a3e92d939899de034b64aa313597701 /tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini | |
parent | 5c940fec0aebcce5f81063f195220184918b377b (diff) | |
download | gem5-53a05978054ac9bb718e419a48371bd10c720267.tar.xz |
regressions: x86: stats updates due to new x87 insts
Diffstat (limited to 'tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini')
-rw-r--r-- | tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini index 46354ed27..4f3f120ab 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini @@ -117,7 +117,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=500 +clock=8000 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -168,6 +168,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -200,6 +201,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave |