Stats: Update stats for new default L1-to-L2 bus clock and width

This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.

1 files changed, 60 insertions, 60 deletions

diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
index c50a3998a..bc1030252 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.000030                       # Number of seconds simulated
-sim_ticks                                    29676000                       # Number of ticks simulated
-final_tick                                   29676000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.000028                       # Number of seconds simulated
+sim_ticks                                    28356000                       # Number of ticks simulated
+final_tick                                   28356000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  72347                       # Simulator instruction rate (inst/s)
-host_op_rate                                   131001                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              398795084                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 269536                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                 134366                       # Simulator instruction rate (inst/s)
+host_op_rate                                   243261                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              707485860                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 226568                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                        5381                       # Number of instructions simulated
 sim_ops                                          9746                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             14528                       # Number of bytes read from this memory
@@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total           14528                       # Nu
 system.physmem.num_reads::cpu.inst                227                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                134                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   361                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            489553848                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            288987734                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               778541582                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       489553848                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          489553848                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           489553848                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           288987734                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              778541582                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            512343067                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            302440401                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               814783467                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       512343067                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          512343067                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           512343067                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           302440401                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              814783467                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.numCycles                            59352                       # number of cpu cycles simulated
+system.cpu.numCycles                            56712                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        5381                       # Number of instructions committed
@@ -47,18 +47,18 @@ system.cpu.num_mem_refs                          1986                       # nu
 system.cpu.num_load_insts                        1052                       # Number of load instructions
 system.cpu.num_store_insts                        934                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      59352                       # Number of busy cycles
+system.cpu.num_busy_cycles                      56712                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                105.746399                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                105.556077                       # Cycle average of tags in use
 system.cpu.icache.total_refs                     6637                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    228                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  29.109649                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     105.746399                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.051634                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.051634                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     105.556077                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.051541                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.051541                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst         6637                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            6637                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          6637                       # number of demand (read+write) hits
@@ -71,12 +71,12 @@ system.cpu.icache.demand_misses::cpu.inst          228                       # n
 system.cpu.icache.demand_misses::total            228                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          228                       # number of overall misses
 system.cpu.icache.overall_misses::total           228                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     12726000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     12726000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     12726000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     12726000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     12726000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     12726000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     12498000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     12498000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     12498000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     12498000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     12498000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     12498000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst         6865                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total         6865                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst         6865                       # number of demand (read+write) accesses
@@ -89,12 +89,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.033212
 system.cpu.icache.demand_miss_rate::total     0.033212                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.033212                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.033212                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55815.789474                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 55815.789474                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 55815.789474                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 55815.789474                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 55815.789474                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 55815.789474                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54815.789474                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 54815.789474                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 54815.789474                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 54815.789474                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 54815.789474                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 54815.789474                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474
 system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 80.866493                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                 80.800961                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                     1852                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    134                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  13.820896                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      80.866493                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.019743                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.019743                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data      80.800961                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.019727                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.019727                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data          997                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total             997                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          855                       # number of WriteReq hits
@@ -153,14 +153,14 @@ system.cpu.dcache.demand_misses::cpu.data          134                       # n
 system.cpu.dcache.demand_misses::total            134                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          134                       # number of overall misses
 system.cpu.dcache.overall_misses::total           134                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      3080000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      3080000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      4424000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      4424000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data      7504000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total      7504000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data      7504000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total      7504000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      3025000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      3025000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      4345000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      4345000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data      7370000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      7370000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      7370000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      7370000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1052                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1052                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          934                       # number of WriteReq accesses(hits+misses)
@@ -177,14 +177,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.067472
 system.cpu.dcache.demand_miss_rate::total     0.067472                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.067472                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.067472                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        56000                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total        56000                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total        56000                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data        56000                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total        56000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data        56000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total        56000                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        55000                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total        55000                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        55000                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total        55000                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data        55000                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total        55000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data        55000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total        55000                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -227,16 +227,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               134.266314                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               134.040949                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   282                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.003546                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    105.749768                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     28.516546                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.003227                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.000870                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.004097                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    105.564188                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     28.476761                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.003222                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.000869                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.004091                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits