x86 regressions: stats update due to new x87 instructions

4 files changed, 89 insertions, 90 deletions

diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
index 45681eb64..f8e4933ef 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
 type=System
 children=cpu membus physmem
 boot_osflags=a
-clock=1
+clock=1000
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -61,22 +61,22 @@ type=BaseCache
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=1
+clock=500
 forward_snoops=true
 hash_delay=1
-hit_latency=1000
+hit_latency=2
 is_top_level=true
 max_miss_count=0
-mshrs=10
+mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 prioritizeRequests=false
 repl=Null
-response_latency=1000
+response_latency=2
 size=262144
 subblock_size=0
 system=system
-tgts_per_mshr=5
+tgts_per_mshr=20
 trace_addr=0
 two_queue=false
 write_buffers=8
@@ -91,7 +91,7 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
-clock=1
+clock=500
 system=system
 port=system.cpu.toL2Bus.slave[3]
 
@@ -100,22 +100,22 @@ type=BaseCache
 addr_ranges=0:18446744073709551615
 assoc=2
 block_size=64
-clock=1
+clock=500
 forward_snoops=true
 hash_delay=1
-hit_latency=1000
+hit_latency=2
 is_top_level=true
 max_miss_count=0
-mshrs=10
+mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 prioritizeRequests=false
 repl=Null
-response_latency=1000
+response_latency=2
 size=131072
 subblock_size=0
 system=system
-tgts_per_mshr=5
+tgts_per_mshr=20
 trace_addr=0
 two_queue=false
 write_buffers=8
@@ -124,7 +124,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=X86LocalApic
-clock=1
+clock=500
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -141,31 +141,31 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
-clock=1
+clock=500
 system=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
 addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
 block_size=64
-clock=1
+clock=500
 forward_snoops=true
 hash_delay=1
-hit_latency=10000
+hit_latency=20
 is_top_level=false
 max_miss_count=0
-mshrs=10
+mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 prioritizeRequests=false
 repl=Null
-response_latency=10000
+response_latency=20
 size=2097152
 subblock_size=0
 system=system
-tgts_per_mshr=5
+tgts_per_mshr=12
 trace_addr=0
 two_queue=false
 write_buffers=8
@@ -175,10 +175,10 @@ mem_side=system.membus.slave[1]
 [system.cpu.toL2Bus]
 type=CoherentBus
 block_size=64
-clock=1000
+clock=500
 header_cycles=1
 use_default_range=false
-width=8
+width=32
 master=system.cpu.l2cache.cpu_side
 slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
@@ -217,7 +217,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1
+clock=1000
 conf_table_reported=false
 in_addr_map=true
 latency=30000
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr
index ac4ad20a5..f5691fd64 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr
@@ -1,4 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
-warn: instruction 'fnstcw_Mw' unimplemented
 warn: instruction 'fldcw_Mw' unimplemented
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
index 6c9c7da05..dd8505ccc 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
@@ -3,11 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-tim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 10 2012 21:50:34
-gem5 started Sep 10 2012 21:50:39
+gem5 compiled Dec 30 2012 00:35:18
+gem5 started Dec 30 2012 01:20:12
 gem5 executing on ribera.cs.wisc.edu
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 29676000 because target called exit()
+Exiting @ tick 28357000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
index bc1030252..ce11ecf17 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000028                       # Number of seconds simulated
-sim_ticks                                    28356000                       # Number of ticks simulated
-final_tick                                   28356000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    28357000                       # Number of ticks simulated
+final_tick                                   28357000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 134366                       # Simulator instruction rate (inst/s)
-host_op_rate                                   243261                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              707485860                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 226568                       # Number of bytes of host memory used
-host_seconds                                     0.04                       # Real time elapsed on the host
+host_inst_rate                                  86866                       # Simulator instruction rate (inst/s)
+host_op_rate                                   157296                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              457476490                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 271900                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        5381                       # Number of instructions simulated
-sim_ops                                          9746                       # Number of ops (including micro ops) simulated
+sim_ops                                          9747                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             14528                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              8576                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                23104                       # Number of bytes read from this memory
@@ -19,46 +19,46 @@ system.physmem.bytes_inst_read::total           14528                       # Nu
 system.physmem.num_reads::cpu.inst                227                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                134                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   361                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            512343067                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            302440401                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               814783467                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       512343067                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          512343067                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           512343067                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           302440401                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              814783467                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            512324999                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            302429735                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               814754734                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       512324999                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          512324999                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           512324999                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           302429735                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              814754734                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.numCycles                            56712                       # number of cpu cycles simulated
+system.cpu.numCycles                            56714                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                        5381                       # Number of instructions committed
-system.cpu.committedOps                          9746                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  9651                       # Number of integer alu accesses
+system.cpu.committedOps                          9747                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  9653                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
 system.cpu.num_conditional_control_insts          899                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         9651                       # number of integer instructions
+system.cpu.num_int_insts                         9653                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads               24812                       # number of times the integer registers were read
-system.cpu.num_int_register_writes              11060                       # number of times the integer registers were written
+system.cpu.num_int_register_reads               24817                       # number of times the integer registers were read
+system.cpu.num_int_register_writes              11061                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          1986                       # number of memory refs
+system.cpu.num_mem_refs                          1987                       # number of memory refs
 system.cpu.num_load_insts                        1052                       # Number of load instructions
-system.cpu.num_store_insts                        934                       # Number of store instructions
+system.cpu.num_store_insts                        935                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      56712                       # Number of busy cycles
+system.cpu.num_busy_cycles                      56714                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                105.556077                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                105.553131                       # Cycle average of tags in use
 system.cpu.icache.total_refs                     6637                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    228                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  29.109649                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     105.556077                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.051541                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.051541                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     105.553131                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.051540                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.051540                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst         6637                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            6637                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          6637                       # number of demand (read+write) hits
@@ -129,22 +129,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474
 system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 80.800961                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     1852                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 80.799099                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     1853                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    134                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  13.820896                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  13.828358                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      80.800961                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.019727                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.019727                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::cpu.data      80.799099                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.019726                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.019726                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data          997                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total             997                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          855                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            855                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          1852                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1852                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1852                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1852                       # number of overall hits
+system.cpu.dcache.WriteReq_hits::cpu.data          856                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            856                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          1853                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1853                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1853                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1853                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data           55                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total            55                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data           79                       # number of WriteReq misses
@@ -163,20 +163,20 @@ system.cpu.dcache.overall_miss_latency::cpu.data      7370000
 system.cpu.dcache.overall_miss_latency::total      7370000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data         1052                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1052                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data          934                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total          934                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         1986                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         1986                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         1986                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         1986                       # number of overall (read+write) accesses
+system.cpu.dcache.WriteReq_accesses::cpu.data          935                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          935                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         1987                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         1987                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         1987                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         1987                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.052281                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.052281                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.084582                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.084582                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.067472                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.067472                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.067472                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.067472                       # miss rate for overall accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.084492                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.084492                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.067438                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.067438                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.067438                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.067438                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        55000                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total        55000                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        55000                       # average WriteReq miss latency
@@ -211,12 +211,12 @@ system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7102000
 system.cpu.dcache.overall_mshr_miss_latency::total      7102000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.052281                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.052281                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084582                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084582                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.067472                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.067472                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.067472                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.067472                       # mshr miss rate for overall accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084492                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084492                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.067438                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.067438                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.067438                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.067438                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
@@ -227,14 +227,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               134.040949                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               134.037527                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   282                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.003546                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    105.564188                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     28.476761                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.003222                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    105.561241                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     28.476285                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.003221                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.000869                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::total        0.004091                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits