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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-05 20:26:18 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-05 20:26:18 -0500 |
| commit | 381e9191ddcacb78f2f1e72040d9843d43b3461b (patch) | |
| tree | 4916dbc13db6a6823a0f37552fc45918ad4bd89a /tests/quick/se/00.hello/ref/x86/linux/simple-timing | |
| parent | 9954eb74df98c4749651eb78098595f78d642105 (diff) | |
| download | gem5-381e9191ddcacb78f2f1e72040d9843d43b3461b.tar.xz | |
stats: x86: update stats missed out on in preivous changeset
Diffstat (limited to 'tests/quick/se/00.hello/ref/x86/linux/simple-timing')
| -rw-r--r-- | tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini index 001f21930..02d0f19b1 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini @@ -93,7 +93,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -104,7 +104,6 @@ size=262144 system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -144,7 +143,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=4 prefetch_on_access=false @@ -155,7 +154,6 @@ size=131072 system=system tags=system.cpu.icache.tags tgts_per_mshr=20 -two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -211,7 +209,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -222,7 +220,6 @@ size=2097152 system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 -two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] |