stats: Update the stats to reflect bus and memory changes

This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.

1 files changed, 38 insertions, 0 deletions

diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
index 496e32aca..7844ef634 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -27,6 +27,25 @@ system.physmem.bw_inst_read::total          512306933                       # In
 system.physmem.bw_total::cpu.inst           512306933                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data           302419070                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total              814726003                       # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput                    814726003                       # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq                 282                       # Transaction distribution
+system.membus.trans_dist::ReadResp                282                       # Transaction distribution
+system.membus.trans_dist::ReadExReq                79                       # Transaction distribution
+system.membus.trans_dist::ReadExResp               79                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port          722                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total          722                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.physmem.port          722                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                    722                       # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port        23104                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total        23104                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.physmem.port        23104                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total               23104                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus                  23104                       # Total data (bytes)
+system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy              361000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               1.3                       # Layer utilization (%)
+system.membus.respLayer1.occupancy            3249000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization             11.5                       # Layer utilization (%)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                            56716                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -351,5 +370,24 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total        53000
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput               816982862                       # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq            283                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp           283                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq           79                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp           79                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side          456                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side          268                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count                      724                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side        14592                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side         8576                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size                 23168                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus             23168                       # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy         181000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy        342000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          1.2                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy        201000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------