stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee

1 files changed, 18 insertions, 4 deletions

diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
index 0e6d74be3..be586bcab 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -4,15 +4,16 @@ sim_seconds                                  0.000031                       # Nu
 sim_ticks                                    30886500                       # Number of ticks simulated
 final_tick                                   30886500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 324268                       # Simulator instruction rate (inst/s)
-host_op_rate                                   586988                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1858658321                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 262968                       # Number of bytes of host memory used
+host_inst_rate                                 223066                       # Simulator instruction rate (inst/s)
+host_op_rate                                   403939                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1279464733                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 309460                       # Number of bytes of host memory used
 host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5381                       # Number of instructions simulated
 sim_ops                                          9748                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED     30886500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst             14528                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              8576                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                23104                       # Number of bytes read from this memory
@@ -29,9 +30,14 @@ system.physmem.bw_inst_read::total          470367313                       # In
 system.physmem.bw_total::cpu.inst           470367313                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data           277661762                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total              748029074                       # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED     30886500                       # Cumulative time (in ticks) in various power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED     30886500                       # Cumulative time (in ticks) in various power states
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED     30886500                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED     30886500                       # Cumulative time (in ticks) in various power states
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON        30886500                       # Cumulative time (in ticks) in various power states
 system.cpu.numCycles                            61773                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -92,6 +98,7 @@ system.cpu.op_class::MemWrite                     935      9.59%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                       9748                       # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED     30886500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements                 0                       # number of replacements
 system.cpu.dcache.tags.tagsinuse            80.558239                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs                1854                       # Total number of references to valid blocks.
@@ -107,6 +114,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1          103
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.032715                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses              4110                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses             4110                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED     30886500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data          998                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total             998                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          856                       # number of WriteReq hits
@@ -193,6 +201,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        61000
 system.cpu.dcache.demand_avg_mshr_miss_latency::total        61000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        61000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        61000                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED     30886500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements                 0                       # number of replacements
 system.cpu.icache.tags.tagsinuse           105.267613                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                6636                       # Total number of references to valid blocks.
@@ -208,6 +217,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1          142
 system.cpu.icache.tags.occ_task_id_percent::1024     0.111328                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses             13956                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses            13956                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED     30886500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.ReadReq_hits::cpu.inst         6636                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total            6636                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst          6636                       # number of demand (read+write) hits
@@ -274,6 +284,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60791.666667
 system.cpu.icache.demand_avg_mshr_miss_latency::total 60791.666667                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60791.666667                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 60791.666667                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED     30886500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse          133.672095                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
@@ -291,6 +302,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1          178
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.008606                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             3257                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            3257                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED     30886500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst            1                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadCleanReq_hits::total            1                       # number of ReadCleanReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
@@ -417,6 +429,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED     30886500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp           283                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq           79                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp           79                       # Transaction distribution
@@ -446,6 +459,7 @@ system.cpu.toL2Bus.respLayer0.occupancy        342000                       # La
 system.cpu.toL2Bus.respLayer0.utilization          1.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy        201000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED     30886500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp                282                       # Transaction distribution
 system.membus.trans_dist::ReadExReq                79                       # Transaction distribution
 system.membus.trans_dist::ReadExResp               79                       # Transaction distribution