Regression Tests: Update statistics

3 files changed, 21 insertions, 12 deletions

diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
index 6978d28ee..98b722b0c 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
@@ -132,14 +132,15 @@ block_size=64
 clock=1
 forward_snoops=true
 hash_delay=1
+hit_latency=1000
 is_top_level=true
-latency=1000
 max_miss_count=0
 mshrs=10
 prefetch_on_access=false
 prefetcher=Null
 prioritizeRequests=false
 repl=Null
+response_latency=1000
 size=262144
 subblock_size=0
 system=system
@@ -433,14 +434,15 @@ block_size=64
 clock=1
 forward_snoops=true
 hash_delay=1
+hit_latency=1000
 is_top_level=true
-latency=1000
 max_miss_count=0
 mshrs=10
 prefetch_on_access=false
 prefetcher=Null
 prioritizeRequests=false
 repl=Null
+response_latency=1000
 size=131072
 subblock_size=0
 system=system
@@ -482,14 +484,15 @@ block_size=64
 clock=1
 forward_snoops=true
 hash_delay=1
+hit_latency=1000
 is_top_level=false
-latency=1000
 max_miss_count=0
 mshrs=10
 prefetch_on_access=false
 prefetcher=Null
 prioritizeRequests=false
 repl=Null
+response_latency=1000
 size=2097152
 subblock_size=0
 system=system
@@ -544,9 +547,9 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
 
 [system.physmem]
 type=SimpleMemory
+bandwidth=73.000000
 clock=1
 conf_table_reported=false
-file=
 in_addr_map=true
 latency=30000
 latency_var=0
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
index 8e358d7bf..d97af8c71 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
@@ -207,9 +207,9 @@ slave=system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port s
 
 [system.physmem]
 type=SimpleMemory
+bandwidth=0.000000
 clock=1
 conf_table_reported=false
-file=
 in_addr_map=true
 latency=30
 latency_var=0
@@ -259,8 +259,9 @@ link_id=0
 weight=1
 
 [system.ruby.network.topology.ext_links0.int_node]
-type=BasicRouter
+type=Switch
 router_id=0
+virt_nets=10
 
 [system.ruby.network.topology.ext_links1]
 type=SimpleExtLink
@@ -273,8 +274,9 @@ link_id=1
 weight=1
 
 [system.ruby.network.topology.ext_links1.int_node]
-type=BasicRouter
+type=Switch
 router_id=1
+virt_nets=10
 
 [system.ruby.network.topology.int_links0]
 type=SimpleIntLink
@@ -287,8 +289,9 @@ node_b=system.ruby.network.topology.int_links0.node_b
 weight=1
 
 [system.ruby.network.topology.int_links0.node_b]
-type=BasicRouter
+type=Switch
 router_id=2
+virt_nets=10
 
 [system.ruby.network.topology.int_links1]
 type=SimpleIntLink
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
index e0483161d..45681eb64 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -64,14 +64,15 @@ block_size=64
 clock=1
 forward_snoops=true
 hash_delay=1
+hit_latency=1000
 is_top_level=true
-latency=1000
 max_miss_count=0
 mshrs=10
 prefetch_on_access=false
 prefetcher=Null
 prioritizeRequests=false
 repl=Null
+response_latency=1000
 size=262144
 subblock_size=0
 system=system
@@ -102,14 +103,15 @@ block_size=64
 clock=1
 forward_snoops=true
 hash_delay=1
+hit_latency=1000
 is_top_level=true
-latency=1000
 max_miss_count=0
 mshrs=10
 prefetch_on_access=false
 prefetcher=Null
 prioritizeRequests=false
 repl=Null
+response_latency=1000
 size=131072
 subblock_size=0
 system=system
@@ -151,14 +153,15 @@ block_size=64
 clock=1
 forward_snoops=true
 hash_delay=1
+hit_latency=10000
 is_top_level=false
-latency=10000
 max_miss_count=0
 mshrs=10
 prefetch_on_access=false
 prefetcher=Null
 prioritizeRequests=false
 repl=Null
+response_latency=10000
 size=2097152
 subblock_size=0
 system=system
@@ -213,9 +216,9 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
 
 [system.physmem]
 type=SimpleMemory
+bandwidth=73.000000
 clock=1
 conf_table_reported=false
-file=
 in_addr_map=true
 latency=30000
 latency_var=0