diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-08-15 10:38:05 -0400 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-08-15 10:38:05 -0400 |
| commit | 73e9e923d00c6f5df9e79a6c40ecc159894d2bc5 (patch) | |
| tree | f84188c6697fe79f0521b73d9d38855ce7e04d29 /tests/quick/se/00.hello/ref/x86/linux | |
| parent | dd1b346584e520ba970e62aa3bcc7d32828cdeba (diff) | |
| download | gem5-73e9e923d00c6f5df9e79a6c40ecc159894d2bc5.tar.xz | |
stats: Update stats for syscall emulation Linux kernel changes.
Diffstat (limited to 'tests/quick/se/00.hello/ref/x86/linux')
12 files changed, 637 insertions, 637 deletions
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini index 73bd70079..5085616c4 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini @@ -533,7 +533,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index 3bef840f7..f4d9273f5 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:58:39 -gem5 started Jul 2 2012 12:38:36 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 18:22:30 gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 12803000 because target called exit() +Exiting @ tick 12789500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index d0e4f2a16..89fb2bf27 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,344 +1,344 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 12803000 # Number of ticks simulated -final_tick 12803000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 12789500 # Number of ticks simulated +final_tick 12789500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24032 # Simulator instruction rate (inst/s) -host_op_rate 43521 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56800152 # Simulator tick rate (ticks/s) -host_mem_usage 227452 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host -sim_insts 5416 # Number of instructions simulated -sim_ops 9809 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory +host_inst_rate 20973 # Simulator instruction rate (inst/s) +host_op_rate 37987 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49851854 # Simulator tick rate (ticks/s) +host_mem_usage 232356 # Number of bytes of host memory used +host_seconds 0.26 # Real time elapsed on the host +sim_insts 5380 # Number of instructions simulated +sim_ops 9745 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 19456 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9280 # Number of bytes read from this memory -system.physmem.bytes_read::total 28544 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 304 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 145 # Number of read requests responded to by this memory -system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1504647348 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 724830118 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2229477466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1504647348 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1504647348 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1504647348 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 724830118 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2229477466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 449 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1521247899 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 725595215 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2246843113 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1521247899 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1521247899 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1521247899 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 725595215 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2246843113 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 25607 # number of cpu cycles simulated +system.cpu.numCycles 25580 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 3125 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3125 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 558 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2605 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 830 # Number of BTB hits +system.cpu.BPredUnit.lookups 3138 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3138 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 562 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2607 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 814 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8034 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14981 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3125 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 830 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4070 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2483 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3408 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 41 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 244 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1957 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 281 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 17679 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.502687 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.975668 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 8037 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15123 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3138 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 814 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4093 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2492 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3369 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 178 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 17601 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.521504 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.991998 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 13710 77.55% 77.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 177 1.00% 78.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 164 0.93% 79.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 211 1.19% 80.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 170 0.96% 81.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 182 1.03% 82.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 260 1.47% 84.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 162 0.92% 85.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2643 14.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 13611 77.33% 77.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 183 1.04% 78.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 154 0.87% 79.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 201 1.14% 80.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 179 1.02% 81.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 174 0.99% 82.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 262 1.49% 83.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 168 0.95% 84.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2669 15.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 17679 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.122037 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.585035 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8588 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3390 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3692 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 127 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1882 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 25327 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1882 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8910 # Number of cycles rename is idle +system.cpu.fetch.rateDist::total 17601 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122674 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.591204 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8517 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3363 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3698 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1897 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 25566 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1897 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8847 # Number of cycles rename is idle system.cpu.rename.BlockCycles 2031 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 505 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3461 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 890 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 23802 # Number of instructions processed by rename +system.cpu.rename.serializeStallCycles 471 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3459 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 896 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 24019 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 47 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 747 # Number of times rename has blocked due to LSQ full +system.cpu.rename.IQFullEvents 44 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 760 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 34224 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 68607 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 68591 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 34373 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 69151 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 69135 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 14707 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 19517 # Number of HB maps that are undone due to squashing +system.cpu.rename.CommittedMaps 14595 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 19778 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 35 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 35 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1875 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2306 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1775 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. +system.cpu.rename.skidInsts 1918 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2391 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1803 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21232 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17582 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 92 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10865 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 19620 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 27 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 17679 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.994513 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.826049 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 21439 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 41 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 17729 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 95 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11045 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 19872 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 17601 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.007272 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.841273 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12114 68.52% 68.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1582 8.95% 77.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1012 5.72% 83.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 689 3.90% 87.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 696 3.94% 91.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 692 3.91% 94.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 627 3.55% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 233 1.32% 99.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 34 0.19% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12034 68.37% 68.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1562 8.87% 77.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1007 5.72% 82.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 685 3.89% 86.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 692 3.93% 90.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 711 4.04% 94.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 630 3.58% 98.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 245 1.39% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 35 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 17679 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 17601 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 133 73.08% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.08% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 29 15.93% 89.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 20 10.99% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 137 74.46% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 74.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 28 15.22% 89.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19 10.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14185 80.68% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1924 10.94% 91.64% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1469 8.36% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14250 80.38% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1990 11.22% 91.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1485 8.38% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17582 # Type of FU issued -system.cpu.iq.rate 0.686609 # Inst issue rate -system.cpu.iq.fu_busy_cnt 182 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010351 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 53109 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 32144 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16183 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17729 # Type of FU issued +system.cpu.iq.rate 0.693081 # Inst issue rate +system.cpu.iq.fu_busy_cnt 184 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010378 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 53330 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 32532 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16277 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 17756 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17905 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 148 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 157 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1250 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1339 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 20 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 841 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 869 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1882 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1425 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21272 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 46 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2306 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1775 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 36 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1897 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1429 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 34 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 21480 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 37 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2391 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1803 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 65 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 640 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 705 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16602 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1794 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 980 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 631 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 699 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16697 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1851 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1032 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3144 # number of memory reference insts executed -system.cpu.iew.exec_branches 1642 # Number of branches executed -system.cpu.iew.exec_stores 1350 # Number of stores executed -system.cpu.iew.exec_rate 0.648338 # Inst execution rate -system.cpu.iew.wb_sent 16384 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16187 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10480 # num instructions producing a value -system.cpu.iew.wb_consumers 24095 # num instructions consuming a value +system.cpu.iew.exec_refs 3217 # number of memory reference insts executed +system.cpu.iew.exec_branches 1636 # Number of branches executed +system.cpu.iew.exec_stores 1366 # Number of stores executed +system.cpu.iew.exec_rate 0.652737 # Inst execution rate +system.cpu.iew.wb_sent 16474 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16281 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10466 # num instructions producing a value +system.cpu.iew.wb_consumers 23993 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.632132 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.434945 # average fanout of values written-back +system.cpu.iew.wb_rate 0.636474 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.436211 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 5416 # The number of committed instructions -system.cpu.commit.commitCommittedOps 9809 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 11462 # The number of squashed insts skipped by commit +system.cpu.commit.commitCommittedInsts 5380 # The number of committed instructions +system.cpu.commit.commitCommittedOps 9745 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 11734 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 589 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 15797 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.620941 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.463366 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 583 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 15704 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.620543 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.459156 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 12065 76.38% 76.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1534 9.71% 86.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 576 3.65% 89.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 731 4.63% 94.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 367 2.32% 96.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 129 0.82% 97.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 134 0.85% 98.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 75 0.47% 98.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 186 1.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11988 76.34% 76.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1532 9.76% 86.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 562 3.58% 89.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 734 4.67% 94.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 373 2.38% 96.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 129 0.82% 97.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 134 0.85% 98.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70 0.45% 98.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 182 1.16% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 15797 # Number of insts commited each cycle -system.cpu.commit.committedInsts 5416 # Number of instructions committed -system.cpu.commit.committedOps 9809 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 15704 # Number of insts commited each cycle +system.cpu.commit.committedInsts 5380 # Number of instructions committed +system.cpu.commit.committedOps 9745 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 1990 # Number of memory references committed -system.cpu.commit.loads 1056 # Number of loads committed +system.cpu.commit.refs 1986 # Number of memory references committed +system.cpu.commit.loads 1052 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 1214 # Number of branches committed +system.cpu.commit.branches 1208 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 9714 # Number of committed integer instructions. +system.cpu.commit.int_insts 9650 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 186 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 182 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 36882 # The number of ROB reads -system.cpu.rob.rob_writes 44457 # The number of ROB writes -system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7928 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 5416 # Number of Instructions Simulated -system.cpu.committedOps 9809 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 5416 # Number of Instructions Simulated -system.cpu.cpi 4.728028 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.728028 # CPI: Total CPI of All Threads -system.cpu.ipc 0.211505 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.211505 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 35136 # number of integer regfile reads -system.cpu.int_regfile_writes 21832 # number of integer regfile writes +system.cpu.rob.rob_reads 37001 # The number of ROB reads +system.cpu.rob.rob_writes 44889 # The number of ROB writes +system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7979 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 5380 # Number of Instructions Simulated +system.cpu.committedOps 9745 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 5380 # Number of Instructions Simulated +system.cpu.cpi 4.754647 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.754647 # CPI: Total CPI of All Threads +system.cpu.ipc 0.210321 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.210321 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 35250 # number of integer regfile reads +system.cpu.int_regfile_writes 21824 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7303 # number of misc regfile reads +system.cpu.misc_regfile_reads 7352 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 144.987593 # Cycle average of tags in use -system.cpu.icache.total_refs 1569 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 302 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.195364 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 145.590340 # Cycle average of tags in use +system.cpu.icache.total_refs 1562 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 305 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.121311 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 144.987593 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.070795 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.070795 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1569 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1569 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1569 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1569 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1569 # number of overall hits -system.cpu.icache.overall_hits::total 1569 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 145.590340 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071089 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071089 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1562 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1562 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1562 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1562 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1562 # number of overall hits +system.cpu.icache.overall_hits::total 1562 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 388 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 388 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 388 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 388 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 388 # number of overall misses system.cpu.icache.overall_misses::total 388 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14367500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14367500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14367500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14367500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14367500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14367500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1957 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1957 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1957 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1957 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1957 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1957 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.198263 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.198263 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.198263 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.198263 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.198263 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.198263 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37029.639175 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 37029.639175 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 37029.639175 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 37029.639175 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 37029.639175 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 37029.639175 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14396500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14396500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14396500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14396500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14396500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14396500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1950 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1950 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1950 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1950 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1950 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.198974 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.198974 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.198974 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.198974 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.198974 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.198974 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37104.381443 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 37104.381443 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 37104.381443 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 37104.381443 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 37104.381443 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 37104.381443 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -347,94 +347,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 86 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 86 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 86 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11138000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11138000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11138000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11138000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11138000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11138000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.154318 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.154318 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.154318 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.154318 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.154318 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.154318 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36880.794702 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36880.794702 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36880.794702 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36880.794702 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36880.794702 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36880.794702 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 83 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 83 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 83 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 83 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 83 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 305 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 305 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 305 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 305 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11253500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11253500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11253500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11253500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11253500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11253500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.156410 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.156410 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.156410 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.156410 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.156410 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.156410 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36896.721311 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36896.721311 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36896.721311 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36896.721311 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36896.721311 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36896.721311 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 83.196834 # Cycle average of tags in use -system.cpu.dcache.total_refs 2330 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 83.110838 # Cycle average of tags in use +system.cpu.dcache.total_refs 2373 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.180556 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.479167 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 83.196834 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020312 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020312 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1472 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1472 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 83.110838 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020291 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020291 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1515 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1515 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2330 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2330 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2330 # number of overall hits -system.cpu.dcache.overall_hits::total 2330 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 112 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 112 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2373 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2373 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2373 # number of overall hits +system.cpu.dcache.overall_hits::total 2373 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 114 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 114 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 188 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 188 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 188 # number of overall misses -system.cpu.dcache.overall_misses::total 188 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4401500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4401500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3078500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3078500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7480000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7480000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7480000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7480000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1584 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1584 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 190 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 190 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 190 # number of overall misses +system.cpu.dcache.overall_misses::total 190 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4446000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4446000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3078000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3078000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7524000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7524000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7524000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7524000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1629 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1629 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2518 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2518 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2518 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2518 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070707 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070707 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2563 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2563 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2563 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2563 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.069982 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.069982 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074662 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074662 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074662 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074662 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39299.107143 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 39299.107143 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40506.578947 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40506.578947 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39787.234043 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39787.234043 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39787.234043 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39787.234043 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.074132 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074132 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074132 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074132 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 39000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40500 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40500 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39600 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39600 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39600 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39600 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -443,12 +443,12 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 43 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 43 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 43 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 43 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 43 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 43 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 45 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 45 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 45 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 69 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses @@ -457,103 +457,103 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 145 system.cpu.dcache.demand_mshr_misses::total 145 # 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number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996721 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997305 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997326 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996721 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997778 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996721 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32813.953488 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35021.739130 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33225.675676 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997778 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32832.236842 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35297.101449 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33288.203753 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33440.789474 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33440.789474 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32813.953488 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34193.103448 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33262.331839 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32813.953488 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34193.103448 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33262.331839 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32832.236842 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34324.137931 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33314.031180 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32832.236842 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34324.137931 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33314.031180 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini index 3367142fe..1c047bcde 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -120,8 +120,8 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +width=8 +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master [system.physmem] diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout index 85d4b3244..2878f37c1 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 15:04:09 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 18:22:41 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 5651000 because target called exit() +Exiting @ tick 5614000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index 971607574..288f81674 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 5651000 # Number of ticks simulated -final_tick 5651000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 5614000 # Number of ticks simulated +final_tick 5614000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 420667 # Simulator instruction rate (inst/s) -host_op_rate 760787 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 437668419 # Simulator tick rate (ticks/s) -host_mem_usage 214072 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 5417 # Number of instructions simulated -sim_ops 9810 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 55280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7068 # Number of bytes read from this memory -system.physmem.bytes_read::total 62348 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 55280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 55280 # Number of instructions bytes read from this memory +host_inst_rate 93021 # Simulator instruction rate (inst/s) +host_op_rate 168430 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 96993365 # Simulator tick rate (ticks/s) +host_mem_usage 222752 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +sim_insts 5381 # Number of instructions simulated +sim_ops 9746 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7064 # Number of bytes read from this memory +system.physmem.bytes_read::total 61976 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 54912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 54912 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 7110 # Number of bytes written to this memory system.physmem.bytes_written::total 7110 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6910 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1056 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7966 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 6864 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1052 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7916 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 934 # Number of write requests responded to by this memory system.physmem.num_writes::total 934 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 9782339409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1250752079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11033091488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 9782339409 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 9782339409 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1258184392 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1258184392 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 9782339409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2508936471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12291275880 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 9781261133 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1258282864 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11039543997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 9781261133 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 9781261133 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1266476665 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1266476665 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 9781261133 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2524759530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12306020663 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 11303 # number of cpu cycles simulated +system.cpu.numCycles 11229 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5417 # Number of instructions committed -system.cpu.committedOps 9810 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses +system.cpu.committedInsts 5381 # Number of instructions committed +system.cpu.committedOps 9746 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 9651 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls -system.cpu.num_int_insts 9715 # number of integer instructions +system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls +system.cpu.num_int_insts 9651 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 29934 # number of times the integer registers were read -system.cpu.num_int_register_writes 14707 # number of times the integer registers were written +system.cpu.num_int_register_reads 29744 # number of times the integer registers were read +system.cpu.num_int_register_writes 14595 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1990 # number of memory refs -system.cpu.num_load_insts 1056 # Number of load instructions +system.cpu.num_mem_refs 1986 # number of memory refs +system.cpu.num_load_insts 1052 # Number of load instructions system.cpu.num_store_insts 934 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 11303 # Number of busy cycles +system.cpu.num_busy_cycles 11229 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini index 59420f599..2a819a3dd 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini @@ -99,7 +99,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/x86/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout index 64f5cd1a7..f0077f0d5 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 10 2012 17:58:36 -gem5 started Jul 10 2012 17:59:21 -gem5 executing on sc2b0605 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 18:23:02 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index e50c5939b..c455548e3 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,35 +4,35 @@ sim_seconds 0.000276 # Nu sim_ticks 276484 # Number of ticks simulated final_tick 276484 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 37105 # Simulator instruction rate (inst/s) -host_op_rate 67187 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1893389 # Simulator tick rate (ticks/s) -host_mem_usage 244968 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host -sim_insts 5417 # Number of instructions simulated -sim_ops 9810 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 55280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7068 # Number of bytes read from this memory -system.physmem.bytes_read::total 62348 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 55280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 55280 # Number of instructions bytes read from this memory +host_inst_rate 51763 # Simulator instruction rate (inst/s) +host_op_rate 93738 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2658830 # Simulator tick rate (ticks/s) +host_mem_usage 243356 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host +sim_insts 5381 # Number of instructions simulated +sim_ops 9746 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7064 # Number of bytes read from this memory +system.physmem.bytes_read::total 61976 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 54912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 54912 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 7110 # Number of bytes written to this memory system.physmem.bytes_written::total 7110 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6910 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1056 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7966 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 6864 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1052 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7916 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 934 # Number of write requests responded to by this memory system.physmem.num_writes::total 934 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 199939237 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 25563866 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 225503103 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 199939237 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 199939237 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 198608238 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 25549399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 224157637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 198608238 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 198608238 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 25715774 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 25715774 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 199939237 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 51279640 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 251218877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 198608238 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 51265173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 249873410 # Total bandwidth to/from this memory (bytes/s) system.l1_cntrl0.cacheMemory.num_data_array_reads 0 # number of data array reads system.l1_cntrl0.cacheMemory.num_data_array_writes 0 # number of data array writes system.l1_cntrl0.cacheMemory.num_tag_array_reads 0 # number of tag array reads @@ -43,20 +43,20 @@ system.cpu.workload.num_syscalls 11 # Nu system.cpu.numCycles 276484 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5417 # Number of instructions committed -system.cpu.committedOps 9810 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses +system.cpu.committedInsts 5381 # Number of instructions committed +system.cpu.committedOps 9746 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 9651 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls -system.cpu.num_int_insts 9715 # number of integer instructions +system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls +system.cpu.num_int_insts 9651 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 29934 # number of times the integer registers were read -system.cpu.num_int_register_writes 14707 # number of times the integer registers were written +system.cpu.num_int_register_reads 29744 # number of times the integer registers were read +system.cpu.num_int_register_writes 14595 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1990 # number of memory refs -system.cpu.num_load_insts 1056 # Number of load instructions +system.cpu.num_mem_refs 1986 # number of memory refs +system.cpu.num_load_insts 1052 # Number of load instructions system.cpu.num_store_insts 934 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_busy_cycles 276484 # Number of busy cycles diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini index 75df56c4d..3f04b065a 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini @@ -202,7 +202,7 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave +master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout index c1b9925b1..4ca1a9d26 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:58:39 -gem5 started Jul 2 2012 12:38:59 +gem5 compiled Aug 13 2012 17:08:22 +gem5 started Aug 13 2012 18:22:51 gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 29726000 because target called exit() +Exiting @ tick 29676000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 4b1ad61d2..c89020746 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 29726000 # Number of ticks simulated -final_tick 29726000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 29676000 # Number of ticks simulated +final_tick 29676000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 107097 # Simulator instruction rate (inst/s) -host_op_rate 193883 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 587308683 # Simulator tick rate (ticks/s) -host_mem_usage 226300 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -sim_insts 5417 # Number of instructions simulated -sim_ops 9810 # Number of ops (including micro ops) simulated +host_inst_rate 192246 # Simulator instruction rate (inst/s) +host_op_rate 347982 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1058982197 # Simulator tick rate (ticks/s) +host_mem_usage 231200 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +sim_insts 5381 # Number of instructions simulated +sim_ops 9746 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory system.physmem.bytes_read::total 23104 # Number of bytes read from this memory @@ -19,52 +19,52 @@ system.physmem.bytes_inst_read::total 14528 # Nu system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 361 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 488730404 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 288501648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 777232053 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 488730404 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 488730404 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 488730404 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 288501648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 777232053 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 489553848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 288987734 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 778541582 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 489553848 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 489553848 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 489553848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 288987734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 778541582 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 59452 # number of cpu cycles simulated +system.cpu.numCycles 59352 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5417 # Number of instructions committed -system.cpu.committedOps 9810 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses +system.cpu.committedInsts 5381 # Number of instructions committed +system.cpu.committedOps 9746 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 9651 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls -system.cpu.num_int_insts 9715 # number of integer instructions +system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls +system.cpu.num_int_insts 9651 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 29934 # number of times the integer registers were read -system.cpu.num_int_register_writes 14707 # number of times the integer registers were written +system.cpu.num_int_register_reads 29744 # number of times the integer registers were read +system.cpu.num_int_register_writes 14595 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1990 # number of memory refs -system.cpu.num_load_insts 1056 # Number of load instructions +system.cpu.num_mem_refs 1986 # number of memory refs +system.cpu.num_load_insts 1052 # Number of load instructions system.cpu.num_store_insts 934 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 59452 # Number of busy cycles +system.cpu.num_busy_cycles 59352 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 105.590396 # Cycle average of tags in use -system.cpu.icache.total_refs 6683 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 105.746399 # Cycle average of tags in use +system.cpu.icache.total_refs 6637 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 29.311404 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29.109649 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 105.590396 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.051558 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.051558 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 6683 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6683 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 6683 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6683 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 6683 # number of overall hits -system.cpu.icache.overall_hits::total 6683 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 105.746399 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.051634 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.051634 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 6637 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 6637 # number of overall hits +system.cpu.icache.overall_hits::total 6637 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses @@ -77,18 +77,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 12726000 system.cpu.icache.demand_miss_latency::total 12726000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 12726000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 12726000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 6911 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6911 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 6911 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6911 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 6911 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6911 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.032991 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.032991 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.032991 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.032991 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.032991 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.032991 # miss rate for overall accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 6865 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6865 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 6865 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 6865 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 6865 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 6865 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.033212 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.033212 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.033212 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.033212 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.033212 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.033212 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55815.789474 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 55815.789474 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency @@ -115,12 +115,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042000 system.cpu.icache.demand_mshr_miss_latency::total 12042000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.032991 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.032991 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.032991 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033212 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.033212 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.033212 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency @@ -129,22 +129,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 80.767478 # Cycle average of tags in use -system.cpu.dcache.total_refs 1856 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 80.866493 # Cycle average of tags in use +system.cpu.dcache.total_refs 1852 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13.850746 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13.820896 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 80.767478 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.019719 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.019719 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1001 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1001 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 80.866493 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.019743 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.019743 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 997 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 997 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 855 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 855 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1856 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1856 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1856 # number of overall hits -system.cpu.dcache.overall_hits::total 1856 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1852 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1852 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1852 # number of overall hits +system.cpu.dcache.overall_hits::total 1852 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses @@ -161,22 +161,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 7504000 system.cpu.dcache.demand_miss_latency::total 7504000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 7504000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 7504000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1056 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1056 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 1052 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1052 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1990 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1990 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1990 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1990 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052083 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.052083 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 1986 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1986 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1986 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1986 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052281 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052281 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084582 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.084582 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.067337 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.067337 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.067337 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.067337 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.067472 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.067472 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.067472 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.067472 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency @@ -209,14 +209,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052083 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052083 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052281 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052281 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084582 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084582 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067337 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.067337 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067337 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.067337 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067472 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.067472 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067472 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.067472 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency @@ -227,16 +227,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 134.079161 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 134.266314 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 105.593760 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28.485401 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003222 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004092 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 105.749768 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28.516546 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003227 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000870 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004097 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits |