diff options
| author | Gabe Black <gabeblack@google.com> | 2017-03-29 16:14:05 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2017-04-05 18:40:59 +0000 |
| commit | f7ddc4672a17ee4fab3011bb1b570cc7c17dff28 (patch) | |
| tree | 1b09ee7160f513160fdbd766af3afed63f053e1d /tests/quick/se/00.hello/ref/x86/linux | |
| parent | 8ebc3834651857ae5e2ea755844f263d9a8c34ae (diff) | |
| download | gem5-f7ddc4672a17ee4fab3011bb1b570cc7c17dff28.tar.xz | |
stats: Update some stats after simulated program exit behavior was changed.
The following CL delayed program exit and changed the stats for many if not
most of the SE mode regressions.
commit 2c1286865fc2542a0586ca4ff40b00765d17b348
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 14:52:23 2017 -0600
syscall-emul: Rewrite system call exit code
Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16
Reviewed-on: https://gem5-review.googlesource.com/2656
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/quick/se/00.hello/ref/x86/linux')
16 files changed, 2148 insertions, 2111 deletions
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini index 5809007c6..b5dc4aa3b 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -65,7 +66,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -139,6 +140,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -764,7 +766,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -773,14 +775,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr index bbcd9d751..707fed98b 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index 5ab7e4cb5..d96836b29 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 29 2016 18:55:59 -gem5 started Nov 29 2016 18:56:21 -gem5 executing on zizzer, pid 719 -command line: /z/powerjg/gem5-upstream/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/x86/linux/o3-timing +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:21 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87180 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 22466500 because target called exit() +Exiting @ tick 22516500 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index a160b1441..f96155fcc 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,995 +1,995 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000023 # Number of seconds simulated -sim_ticks 22516500 # Number of ticks simulated -final_tick 22516500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69174 # Simulator instruction rate (inst/s) -host_op_rate 125309 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 289442861 # Simulator tick rate (ticks/s) -host_mem_usage 271352 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -sim_insts 5380 # Number of instructions simulated -sim_ops 9747 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory -system.physmem.num_reads::total 417 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 787333733 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 397930407 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1185264140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 787333733 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 787333733 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 787333733 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 397930407 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1185264140 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 417 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26688 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26688 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 31 # Per bank write bursts -system.physmem.perBankRdBursts::1 1 # Per bank write bursts -system.physmem.perBankRdBursts::2 5 # Per bank write bursts -system.physmem.perBankRdBursts::3 8 # Per bank write bursts -system.physmem.perBankRdBursts::4 51 # Per bank write bursts -system.physmem.perBankRdBursts::5 44 # Per bank write bursts -system.physmem.perBankRdBursts::6 21 # Per bank write bursts -system.physmem.perBankRdBursts::7 36 # Per bank write bursts -system.physmem.perBankRdBursts::8 24 # Per bank write bursts -system.physmem.perBankRdBursts::9 71 # Per bank write bursts -system.physmem.perBankRdBursts::10 64 # Per bank write bursts -system.physmem.perBankRdBursts::11 16 # Per bank write bursts -system.physmem.perBankRdBursts::12 2 # Per bank write bursts -system.physmem.perBankRdBursts::13 20 # Per bank write bursts -system.physmem.perBankRdBursts::14 6 # Per bank write bursts -system.physmem.perBankRdBursts::15 17 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22387500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 417 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 98 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 239.673469 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 154.283411 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 255.721287 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 41 41.84% 41.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22 22.45% 64.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 16 16.33% 80.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 7.14% 87.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1 1.02% 88.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 3.06% 91.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 2.04% 93.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 2.04% 95.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4 4.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 98 # Bytes accessed per row activation -system.physmem.totQLat 6651000 # Total ticks spent queuing -system.physmem.totMemAccLat 14469750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15949.64 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34699.64 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1185.26 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1185.26 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.26 # Data bus utilization in percentage -system.physmem.busUtilRead 9.26 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.67 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 307 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 53687.05 # Average gap between requests -system.physmem.pageHitRate 73.62 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 307020 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 140415 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1406580 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2488050 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 28320 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 7581570 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 138720 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 13319955 # Total energy per rank (pJ) -system.physmem_0.averagePower 591.537915 # Core power per rank (mW) -system.physmem_0.totalIdleTime 16888750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 17500 # Time in different power states -system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 361000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 4997500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 16620500 # Time in different power states -system.physmem_1.actEnergy 478380 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 231495 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1570800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2961150 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 80160 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 7211640 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 13762905 # Total energy per rank (pJ) -system.physmem_1.averagePower 611.209282 # Core power per rank (mW) -system.physmem_1.totalIdleTime 15691750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 103000 # Time in different power states -system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 6065500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 15828000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 3542 # Number of BP lookups -system.cpu.branchPred.condPredicted 3542 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 576 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 3006 # Number of BTB lookups -system.cpu.branchPred.BTBHits 0 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 386 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 97 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3006 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 514 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2492 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 416 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 22516500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 45034 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12047 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16169 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3542 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 900 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 10333 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1321 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 74 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1582 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 15 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 2077 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 274 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 24737 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.175931 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.701309 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20389 82.42% 82.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 178 0.72% 83.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 168 0.68% 83.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 246 0.99% 84.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 215 0.87% 85.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 220 0.89% 86.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 262 1.06% 87.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 167 0.68% 88.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2892 11.69% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 24737 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.078652 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.359040 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12032 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8141 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3437 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 467 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 660 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 26977 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 660 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 12302 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2135 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1085 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3589 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4966 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 25351 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 77 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 4831 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 28444 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 61768 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 35524 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 17381 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 24 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1430 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2685 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1593 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 22118 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 18234 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 157 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12393 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 17118 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 24737 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.737114 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.712019 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19548 79.02% 79.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1204 4.87% 83.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 865 3.50% 87.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 579 2.34% 89.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 831 3.36% 93.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 615 2.49% 95.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 628 2.54% 98.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 340 1.37% 99.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127 0.51% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 24737 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 218 79.85% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 40 14.65% 94.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 15 5.49% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14605 80.10% 80.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.03% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2269 12.44% 92.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1341 7.35% 99.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 4 0.02% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 18234 # Type of FU issued -system.cpu.iq.rate 0.404894 # Inst issue rate -system.cpu.iq.fu_busy_cnt 273 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014972 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 61627 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 34538 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16576 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18501 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 199 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1632 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 658 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 660 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1518 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 153 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 22140 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 9 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2685 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1593 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 152 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 127 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 676 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 803 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 17166 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2051 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1068 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3303 # number of memory reference insts executed -system.cpu.iew.exec_branches 1740 # Number of branches executed -system.cpu.iew.exec_stores 1252 # Number of stores executed -system.cpu.iew.exec_rate 0.381179 # Inst execution rate -system.cpu.iew.wb_sent 16892 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16580 # cumulative count of insts written-back -system.cpu.iew.wb_producers 11141 # num instructions producing a value -system.cpu.iew.wb_consumers 17351 # num instructions consuming a value -system.cpu.iew.wb_rate 0.368166 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.642096 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 12392 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 648 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 22646 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.430407 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.314219 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19391 85.63% 85.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1011 4.46% 90.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 560 2.47% 92.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 726 3.21% 95.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 383 1.69% 97.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 128 0.57% 98.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 118 0.52% 98.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 74 0.33% 98.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 255 1.13% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 22646 # Number of insts commited each cycle -system.cpu.commit.committedInsts 5380 # Number of instructions committed -system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 1988 # Number of memory references committed -system.cpu.commit.loads 1053 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 1208 # Number of branches committed -system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 9653 # Number of committed integer instructions. -system.cpu.commit.function_calls 106 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 1 0.01% 0.01% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 7748 79.49% 79.50% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 3 0.03% 79.53% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 7 0.07% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 1053 10.80% 90.41% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 9747 # Class of committed instruction -system.cpu.commit.bw_lim_events 255 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 44530 # The number of ROB reads -system.cpu.rob.rob_writes 46401 # The number of ROB writes -system.cpu.timesIdled 157 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20297 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 5380 # Number of Instructions Simulated -system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.370632 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.370632 # CPI: Total CPI of All Threads -system.cpu.ipc 0.119465 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.119465 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 21947 # number of integer regfile reads -system.cpu.int_regfile_writes 13377 # number of integer regfile writes -system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.cc_regfile_reads 8355 # number of cc regfile reads -system.cpu.cc_regfile_writes 5130 # number of cc regfile writes -system.cpu.misc_regfile_reads 7644 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.908470 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2549 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 18.207143 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.908470 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019997 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019997 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5608 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5608 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1687 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1687 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 862 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 862 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2549 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2549 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2549 # number of overall hits -system.cpu.dcache.overall_hits::total 2549 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 112 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 112 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 185 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 185 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 185 # number of overall misses -system.cpu.dcache.overall_misses::total 185 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9812000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9812000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6772000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6772000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16584000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16584000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16584000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16584000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1799 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1799 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2734 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2734 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2734 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2734 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062257 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.062257 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078075 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.078075 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.067666 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.067666 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.067666 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.067666 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87607.142857 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 87607.142857 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 92767.123288 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 92767.123288 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 89643.243243 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 89643.243243 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 89643.243243 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 89643.243243 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 45 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 45 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 45 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 67 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 67 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 140 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 140 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6419000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6419000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6699000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6699000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13118000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13118000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13118000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13118000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.037243 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.037243 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.078075 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.078075 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051207 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051207 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051207 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051207 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 95805.970149 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 95805.970149 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91767.123288 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91767.123288 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 93700 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 93700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 93700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 93700 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 130.523512 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1695 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 278 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.097122 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 130.523512 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063732 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063732 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 278 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.135742 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4432 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4432 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1695 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1695 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1695 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1695 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1695 # number of overall hits -system.cpu.icache.overall_hits::total 1695 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 382 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 382 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 382 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 382 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 382 # number of overall misses -system.cpu.icache.overall_misses::total 382 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30098500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30098500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30098500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30098500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30098500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30098500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2077 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2077 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2077 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2077 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2077 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2077 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183919 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.183919 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.183919 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.183919 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.183919 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.183919 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78791.884817 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 78791.884817 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 78791.884817 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 78791.884817 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 78791.884817 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 78791.884817 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 159 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 104 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 104 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 104 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 104 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 104 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 104 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 278 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 278 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23308500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23308500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23308500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23308500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23308500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23308500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133847 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133847 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133847 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.133847 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133847 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.133847 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83843.525180 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83843.525180 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83843.525180 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 83843.525180 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83843.525180 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 83843.525180 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 212.529421 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 417 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002398 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.555666 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 81.973755 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003984 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002502 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006486 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 417 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012726 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3761 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3761 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits -system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 277 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 277 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 67 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 67 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 277 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 140 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 417 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 277 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 140 # number of overall misses -system.cpu.l2cache.overall_misses::total 417 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6589500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6589500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22879500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 22879500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6317500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6317500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22879500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12907000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35786500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22879500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12907000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35786500 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 278 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 278 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 67 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 67 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 278 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 140 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 278 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 140 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996403 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996403 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996403 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997608 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996403 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997608 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90267.123288 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90267.123288 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82597.472924 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82597.472924 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 94291.044776 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 94291.044776 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82597.472924 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92192.857143 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 85818.944844 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82597.472924 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92192.857143 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 85818.944844 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 277 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 277 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 67 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 67 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 417 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5859500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5859500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20109500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20109500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5647500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5647500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20109500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11507000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 31616500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20109500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11507000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 31616500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996403 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80267.123288 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80267.123288 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72597.472924 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72597.472924 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 84291.044776 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84291.044776 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72597.472924 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82192.857143 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75818.944844 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72597.472924 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82192.857143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75818.944844 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 278 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 67 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 556 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 280 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002392 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.048912 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 417 99.76% 99.76% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.24% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 417000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 210000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 417 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 344 # Transaction distribution -system.membus.trans_dist::ReadExReq 73 # Transaction distribution -system.membus.trans_dist::ReadExResp 73 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 344 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 834 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 834 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 834 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 417 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 417 # Request fanout histogram -system.membus.reqLayer0.occupancy 504000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2226500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 9.9 # Layer utilization (%) +sim_seconds 0.000023 +sim_ticks 22516500 +final_tick 22516500 +sim_freq 1000000000000 +host_inst_rate 26720 +host_op_rate 48405 +host_tick_rate 111808950 +host_mem_usage 281880 +host_seconds 0.20 +sim_insts 5380 +sim_ops 9747 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 22516500 +system.physmem.bytes_read::cpu.inst 17728 +system.physmem.bytes_read::cpu.data 8960 +system.physmem.bytes_read::total 26688 +system.physmem.bytes_inst_read::cpu.inst 17728 +system.physmem.bytes_inst_read::total 17728 +system.physmem.num_reads::cpu.inst 277 +system.physmem.num_reads::cpu.data 140 +system.physmem.num_reads::total 417 +system.physmem.bw_read::cpu.inst 787333733 +system.physmem.bw_read::cpu.data 397930407 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+system.cpu.toL2Bus.trans_dist::ReadResp 345 +system.cpu.toL2Bus.trans_dist::ReadExReq 73 +system.cpu.toL2Bus.trans_dist::ReadExResp 73 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 278 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 67 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 556 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 280 +system.cpu.toL2Bus.pkt_count::total 836 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17792 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8960 +system.cpu.toL2Bus.pkt_size::total 26752 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 418 +system.cpu.toL2Bus.snoop_fanout::mean 0.002392 +system.cpu.toL2Bus.snoop_fanout::stdev 0.048912 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 417 99.76% 99.76% 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+system.membus.trans_dist::ReadExResp 73 +system.membus.trans_dist::ReadSharedReq 344 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 834 +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 834 +system.membus.pkt_count::total 834 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26688 +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26688 +system.membus.pkt_size::total 26688 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 417 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 417 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 417 +system.membus.reqLayer0.occupancy 504000 +system.membus.reqLayer0.utilization 2.2 +system.membus.respLayer1.occupancy 2226500 +system.membus.respLayer1.utilization 9.9 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini index 62043a3c5..8968a4ed6 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=atomic @@ -88,6 +89,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -167,7 +169,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -176,14 +178,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/x86/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -207,6 +210,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -218,7 +222,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -226,6 +230,13 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -234,6 +245,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -241,7 +253,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout index bd2d6df6a..8dcc9cbbd 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:19 -gem5 executing on e108600-lin, pid 18561 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-atomic +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:21 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87156 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 5615000 because target called exit() +Exiting @ tick 5615000 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index 54ef40828..2360c7c26 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -1,145 +1,145 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 5615000 # Number of ticks simulated -final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 340881 # Simulator instruction rate (inst/s) -host_op_rate 616836 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 354943212 # Simulator tick rate (ticks/s) -host_mem_usage 258192 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 5381 # Number of instructions simulated -sim_ops 9748 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7066 # Number of bytes read from this memory -system.physmem.bytes_read::total 61978 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 54912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 54912 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 7112 # Number of bytes written to this memory -system.physmem.bytes_written::total 7112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6864 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1053 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7917 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 935 # Number of write requests responded to by this memory -system.physmem.num_writes::total 935 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 9779519145 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1258414960 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11037934105 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 9779519145 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 9779519145 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1266607302 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1266607302 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 9779519145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2525022262 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12304541407 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 5615000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 11231 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5381 # Number of instructions committed -system.cpu.committedOps 9748 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 209 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls -system.cpu.num_int_insts 9654 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 18335 # number of times the integer registers were read -system.cpu.num_int_register_writes 7527 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read -system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written -system.cpu.num_mem_refs 1988 # number of memory refs -system.cpu.num_load_insts 1053 # Number of load instructions -system.cpu.num_store_insts 935 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 11230.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1208 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction -system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction -system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction -system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 9748 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 7917 # Transaction distribution -system.membus.trans_dist::ReadResp 7917 # Transaction distribution -system.membus.trans_dist::WriteReq 935 # Transaction distribution -system.membus.trans_dist::WriteResp 935 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 13728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 13728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3976 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 3976 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17704 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 54912 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 54912 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 14178 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 14178 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 69090 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 8852 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 8852 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 8852 # Request fanout histogram +sim_seconds 0.000006 +sim_ticks 5615000 +final_tick 5615000 +sim_freq 1000000000000 +host_inst_rate 289662 +host_op_rate 524226 +host_tick_rate 301675446 +host_mem_usage 269844 +host_seconds 0.02 +sim_insts 5381 +sim_ops 9748 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 5615000 +system.physmem.bytes_read::cpu.inst 54912 +system.physmem.bytes_read::cpu.data 7066 +system.physmem.bytes_read::total 61978 +system.physmem.bytes_inst_read::cpu.inst 54912 +system.physmem.bytes_inst_read::total 54912 +system.physmem.bytes_written::cpu.data 7112 +system.physmem.bytes_written::total 7112 +system.physmem.num_reads::cpu.inst 6864 +system.physmem.num_reads::cpu.data 1053 +system.physmem.num_reads::total 7917 +system.physmem.num_writes::cpu.data 935 +system.physmem.num_writes::total 935 +system.physmem.bw_read::cpu.inst 9779519145 +system.physmem.bw_read::cpu.data 1258414960 +system.physmem.bw_read::total 11037934105 +system.physmem.bw_inst_read::cpu.inst 9779519145 +system.physmem.bw_inst_read::total 9779519145 +system.physmem.bw_write::cpu.data 1266607302 +system.physmem.bw_write::total 1266607302 +system.physmem.bw_total::cpu.inst 9779519145 +system.physmem.bw_total::cpu.data 2525022262 +system.physmem.bw_total::total 12304541407 +system.pwrStateResidencyTicks::UNDEFINED 5615000 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5615000 +system.cpu.apic_clk_domain.clock 8000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5615000 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5615000 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 5615000 +system.cpu.numCycles 11231 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5381 +system.cpu.committedOps 9748 +system.cpu.num_int_alu_accesses 9654 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 209 +system.cpu.num_conditional_control_insts 899 +system.cpu.num_int_insts 9654 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 18335 +system.cpu.num_int_register_writes 7527 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 6487 +system.cpu.num_cc_register_writes 3536 +system.cpu.num_mem_refs 1988 +system.cpu.num_load_insts 1053 +system.cpu.num_store_insts 935 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 11231 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1208 +system.cpu.op_class::No_OpClass 1 0.01% 0.01% +system.cpu.op_class::IntAlu 7749 79.49% 79.50% +system.cpu.op_class::IntMult 3 0.03% 79.53% +system.cpu.op_class::IntDiv 7 0.07% 79.61% +system.cpu.op_class::FloatAdd 0 0.00% 79.61% +system.cpu.op_class::FloatCmp 0 0.00% 79.61% +system.cpu.op_class::FloatCvt 0 0.00% 79.61% +system.cpu.op_class::FloatMult 0 0.00% 79.61% +system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% +system.cpu.op_class::FloatDiv 0 0.00% 79.61% +system.cpu.op_class::FloatMisc 0 0.00% 79.61% +system.cpu.op_class::FloatSqrt 0 0.00% 79.61% +system.cpu.op_class::SimdAdd 0 0.00% 79.61% +system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% +system.cpu.op_class::SimdAlu 0 0.00% 79.61% +system.cpu.op_class::SimdCmp 0 0.00% 79.61% +system.cpu.op_class::SimdCvt 0 0.00% 79.61% +system.cpu.op_class::SimdMisc 0 0.00% 79.61% +system.cpu.op_class::SimdMult 0 0.00% 79.61% +system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% +system.cpu.op_class::SimdShift 0 0.00% 79.61% +system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% +system.cpu.op_class::SimdSqrt 0 0.00% 79.61% +system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% +system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% +system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% +system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% +system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% +system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% +system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% +system.cpu.op_class::MemRead 1053 10.80% 90.41% +system.cpu.op_class::MemWrite 935 9.59% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 9748 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 5615000 +system.membus.trans_dist::ReadReq 7917 +system.membus.trans_dist::ReadResp 7917 +system.membus.trans_dist::WriteReq 935 +system.membus.trans_dist::WriteResp 935 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 13728 +system.membus.pkt_count_system.cpu.icache_port::total 13728 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3976 +system.membus.pkt_count_system.cpu.dcache_port::total 3976 +system.membus.pkt_count::total 17704 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 54912 +system.membus.pkt_size_system.cpu.icache_port::total 54912 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 14178 +system.membus.pkt_size_system.cpu.dcache_port::total 14178 +system.membus.pkt_size::total 69090 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 8852 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 8852 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 8852 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini index 49adea038..155aa9c1d 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -85,6 +86,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -171,7 +173,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -180,14 +182,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/x86/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -346,6 +349,7 @@ type=RubyDirectoryMemory eventq_index=0 numa_high_bit=5 size=268435456 +system=system version=0 [system.ruby.dir_cntrl0.dmaRequestToDir] diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr index f6f6f15a5..95500d55b 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr @@ -7,4 +7,5 @@ warn: rounding error > tolerance warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout index 60c5b94b3..18eac1046 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 21:09:01 -gem5 executing on e108600-lin, pid 17636 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-timing-ruby +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:22 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87199 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 91859 because target called exit() +Exiting @ tick 91859 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 843ed7643..f79527e54 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -1,369 +1,369 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000092 # Number of seconds simulated -sim_ticks 91859 # Number of ticks simulated -final_tick 91859 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 94122 # Simulator instruction rate (inst/s) -host_op_rate 170479 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1606243 # Simulator tick rate (ticks/s) -host_mem_usage 432368 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -sim_insts 5381 # Number of instructions simulated -sim_ops 9748 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 88128 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 88128 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 87872 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 87872 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 1377 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 1377 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 1373 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 1373 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 959383403 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 959383403 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 956596523 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 956596523 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1915979926 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1915979926 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 1377 # Number of read requests accepted -system.mem_ctrls.writeReqs 1373 # Number of write requests accepted -system.mem_ctrls.readBursts 1377 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 1373 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 41408 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 46720 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 41728 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 88128 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 87872 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 730 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 702 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 60 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 2 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 6 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 10 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 51 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 53 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 39 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 57 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 28 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 129 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 115 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 24 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 2 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 28 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 8 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 35 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 55 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 2 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 6 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 8 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 52 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 48 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 38 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 60 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 28 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 130 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 123 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 24 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 2 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 31 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 8 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 37 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 91773 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 1377 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 1373 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 647 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 33 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 263 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 304.669202 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 201.653389 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 284.735596 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 72 27.38% 27.38% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 68 25.86% 53.23% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 44 16.73% 69.96% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 29 11.03% 80.99% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 12 4.56% 85.55% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 9 3.42% 88.97% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 6 2.28% 91.25% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 3 1.14% 92.40% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 20 7.60% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 263 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 40 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 16.100000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.846587 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 3.484765 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 3 7.50% 7.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 12 30.00% 37.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 19 47.50% 85.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 4 10.00% 95.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 1 2.50% 97.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::34-35 1 2.50% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 40 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 40 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.300000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.281263 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.822753 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 35 87.50% 87.50% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 3 7.50% 95.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 2 5.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 40 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 12721 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 25014 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3235 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 19.66 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 38.66 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 450.78 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 454.26 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 959.38 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 956.60 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 7.07 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 3.52 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 3.55 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.84 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 435 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 591 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 67.23 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 88.08 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 33.37 # Average gap between requests -system.mem_ctrls.pageHitRate 77.85 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 664020 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 340032 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 3175872 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 2246688 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 7375680.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 10273224 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 269568 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 25208136 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 4818816 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 743760.000000 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 55115796 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 600.004311 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 68393 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 346 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 3126 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 798 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 12549 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 19759 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 55281 # Time in different power states -system.mem_ctrls_1.actEnergy 1285200 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 676200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 4215456 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 3198816 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 6761040.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 9576912 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 183552 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 28147512 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 3322368 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 57367056 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 624.512089 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 70328 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 150 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 2866 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 8652 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 18464 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 61727 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 16 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 91859 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 91859 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5381 # Number of instructions committed -system.cpu.committedOps 9748 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 209 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls -system.cpu.num_int_insts 9654 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 18335 # number of times the integer registers were read -system.cpu.num_int_register_writes 7527 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read -system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written -system.cpu.num_mem_refs 1988 # number of memory refs -system.cpu.num_load_insts 1053 # Number of load instructions -system.cpu.num_store_insts 935 # Number of store instructions -system.cpu.num_idle_cycles 0.999989 # Number of idle cycles -system.cpu.num_busy_cycles 91858.000011 # Number of busy cycles -system.cpu.not_idle_fraction 0.999989 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000011 # Percentage of idle cycles -system.cpu.Branches 1208 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction -system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction -system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction -system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 9748 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 2750 # delay histogram for all message -system.ruby.delayHist | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 2750 # delay histogram for all message +sim_seconds 0.000092 +sim_ticks 91859 +final_tick 91859 +sim_freq 1000000000 +host_inst_rate 44912 +host_op_rate 81347 +host_tick_rate 766447 +host_mem_usage 444688 +host_seconds 0.12 +sim_insts 5381 +sim_ops 9748 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1 +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 91859 +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 88128 +system.mem_ctrls.bytes_read::total 88128 +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 87872 +system.mem_ctrls.bytes_written::total 87872 +system.mem_ctrls.num_reads::ruby.dir_cntrl0 1377 +system.mem_ctrls.num_reads::total 1377 +system.mem_ctrls.num_writes::ruby.dir_cntrl0 1373 +system.mem_ctrls.num_writes::total 1373 +system.mem_ctrls.bw_read::ruby.dir_cntrl0 959383403 +system.mem_ctrls.bw_read::total 959383403 +system.mem_ctrls.bw_write::ruby.dir_cntrl0 956596523 +system.mem_ctrls.bw_write::total 956596523 +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1915979926 +system.mem_ctrls.bw_total::total 1915979926 +system.mem_ctrls.readReqs 1377 +system.mem_ctrls.writeReqs 1373 +system.mem_ctrls.readBursts 1377 +system.mem_ctrls.writeBursts 1373 +system.mem_ctrls.bytesReadDRAM 41408 +system.mem_ctrls.bytesReadWrQ 46720 +system.mem_ctrls.bytesWritten 41728 +system.mem_ctrls.bytesReadSys 88128 +system.mem_ctrls.bytesWrittenSys 87872 +system.mem_ctrls.servicedByWrQ 730 +system.mem_ctrls.mergedWrBursts 702 +system.mem_ctrls.neitherReadNorWriteReqs 0 +system.mem_ctrls.perBankRdBursts::0 60 +system.mem_ctrls.perBankRdBursts::1 2 +system.mem_ctrls.perBankRdBursts::2 6 +system.mem_ctrls.perBankRdBursts::3 10 +system.mem_ctrls.perBankRdBursts::4 51 +system.mem_ctrls.perBankRdBursts::5 53 +system.mem_ctrls.perBankRdBursts::6 39 +system.mem_ctrls.perBankRdBursts::7 57 +system.mem_ctrls.perBankRdBursts::8 28 +system.mem_ctrls.perBankRdBursts::9 129 +system.mem_ctrls.perBankRdBursts::10 115 +system.mem_ctrls.perBankRdBursts::11 24 +system.mem_ctrls.perBankRdBursts::12 2 +system.mem_ctrls.perBankRdBursts::13 28 +system.mem_ctrls.perBankRdBursts::14 8 +system.mem_ctrls.perBankRdBursts::15 35 +system.mem_ctrls.perBankWrBursts::0 55 +system.mem_ctrls.perBankWrBursts::1 2 +system.mem_ctrls.perBankWrBursts::2 6 +system.mem_ctrls.perBankWrBursts::3 8 +system.mem_ctrls.perBankWrBursts::4 52 +system.mem_ctrls.perBankWrBursts::5 48 +system.mem_ctrls.perBankWrBursts::6 38 +system.mem_ctrls.perBankWrBursts::7 60 +system.mem_ctrls.perBankWrBursts::8 28 +system.mem_ctrls.perBankWrBursts::9 130 +system.mem_ctrls.perBankWrBursts::10 123 +system.mem_ctrls.perBankWrBursts::11 24 +system.mem_ctrls.perBankWrBursts::12 2 +system.mem_ctrls.perBankWrBursts::13 31 +system.mem_ctrls.perBankWrBursts::14 8 +system.mem_ctrls.perBankWrBursts::15 37 +system.mem_ctrls.numRdRetry 0 +system.mem_ctrls.numWrRetry 0 +system.mem_ctrls.totGap 91773 +system.mem_ctrls.readPktSize::0 0 +system.mem_ctrls.readPktSize::1 0 +system.mem_ctrls.readPktSize::2 0 +system.mem_ctrls.readPktSize::3 0 +system.mem_ctrls.readPktSize::4 0 +system.mem_ctrls.readPktSize::5 0 +system.mem_ctrls.readPktSize::6 1377 +system.mem_ctrls.writePktSize::0 0 +system.mem_ctrls.writePktSize::1 0 +system.mem_ctrls.writePktSize::2 0 +system.mem_ctrls.writePktSize::3 0 +system.mem_ctrls.writePktSize::4 0 +system.mem_ctrls.writePktSize::5 0 +system.mem_ctrls.writePktSize::6 1373 +system.mem_ctrls.rdQLenPdf::0 647 +system.mem_ctrls.rdQLenPdf::1 0 +system.mem_ctrls.rdQLenPdf::2 0 +system.mem_ctrls.rdQLenPdf::3 0 +system.mem_ctrls.rdQLenPdf::4 0 +system.mem_ctrls.rdQLenPdf::5 0 +system.mem_ctrls.rdQLenPdf::6 0 +system.mem_ctrls.rdQLenPdf::7 0 +system.mem_ctrls.rdQLenPdf::8 0 +system.mem_ctrls.rdQLenPdf::9 0 +system.mem_ctrls.rdQLenPdf::10 0 +system.mem_ctrls.rdQLenPdf::11 0 +system.mem_ctrls.rdQLenPdf::12 0 +system.mem_ctrls.rdQLenPdf::13 0 +system.mem_ctrls.rdQLenPdf::14 0 +system.mem_ctrls.rdQLenPdf::15 0 +system.mem_ctrls.rdQLenPdf::16 0 +system.mem_ctrls.rdQLenPdf::17 0 +system.mem_ctrls.rdQLenPdf::18 0 +system.mem_ctrls.rdQLenPdf::19 0 +system.mem_ctrls.rdQLenPdf::20 0 +system.mem_ctrls.rdQLenPdf::21 0 +system.mem_ctrls.rdQLenPdf::22 0 +system.mem_ctrls.rdQLenPdf::23 0 +system.mem_ctrls.rdQLenPdf::24 0 +system.mem_ctrls.rdQLenPdf::25 0 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+system.mem_ctrls.wrQLenPdf::23 40 +system.mem_ctrls.wrQLenPdf::24 40 +system.mem_ctrls.wrQLenPdf::25 40 +system.mem_ctrls.wrQLenPdf::26 40 +system.mem_ctrls.wrQLenPdf::27 40 +system.mem_ctrls.wrQLenPdf::28 40 +system.mem_ctrls.wrQLenPdf::29 40 +system.mem_ctrls.wrQLenPdf::30 40 +system.mem_ctrls.wrQLenPdf::31 40 +system.mem_ctrls.wrQLenPdf::32 40 +system.mem_ctrls.wrQLenPdf::33 0 +system.mem_ctrls.wrQLenPdf::34 0 +system.mem_ctrls.wrQLenPdf::35 0 +system.mem_ctrls.wrQLenPdf::36 0 +system.mem_ctrls.wrQLenPdf::37 0 +system.mem_ctrls.wrQLenPdf::38 0 +system.mem_ctrls.wrQLenPdf::39 0 +system.mem_ctrls.wrQLenPdf::40 0 +system.mem_ctrls.wrQLenPdf::41 0 +system.mem_ctrls.wrQLenPdf::42 0 +system.mem_ctrls.wrQLenPdf::43 0 +system.mem_ctrls.wrQLenPdf::44 0 +system.mem_ctrls.wrQLenPdf::45 0 +system.mem_ctrls.wrQLenPdf::46 0 +system.mem_ctrls.wrQLenPdf::47 0 +system.mem_ctrls.wrQLenPdf::48 0 +system.mem_ctrls.wrQLenPdf::49 0 +system.mem_ctrls.wrQLenPdf::50 0 +system.mem_ctrls.wrQLenPdf::51 0 +system.mem_ctrls.wrQLenPdf::52 0 +system.mem_ctrls.wrQLenPdf::53 0 +system.mem_ctrls.wrQLenPdf::54 0 +system.mem_ctrls.wrQLenPdf::55 0 +system.mem_ctrls.wrQLenPdf::56 0 +system.mem_ctrls.wrQLenPdf::57 0 +system.mem_ctrls.wrQLenPdf::58 0 +system.mem_ctrls.wrQLenPdf::59 0 +system.mem_ctrls.wrQLenPdf::60 0 +system.mem_ctrls.wrQLenPdf::61 0 +system.mem_ctrls.wrQLenPdf::62 0 +system.mem_ctrls.wrQLenPdf::63 0 +system.mem_ctrls.bytesPerActivate::samples 263 +system.mem_ctrls.bytesPerActivate::mean 304.669202 +system.mem_ctrls.bytesPerActivate::gmean 201.653389 +system.mem_ctrls.bytesPerActivate::stdev 284.735596 +system.mem_ctrls.bytesPerActivate::0-127 72 27.38% 27.38% +system.mem_ctrls.bytesPerActivate::128-255 68 25.86% 53.23% +system.mem_ctrls.bytesPerActivate::256-383 44 16.73% 69.96% +system.mem_ctrls.bytesPerActivate::384-511 29 11.03% 80.99% +system.mem_ctrls.bytesPerActivate::512-639 12 4.56% 85.55% +system.mem_ctrls.bytesPerActivate::640-767 9 3.42% 88.97% +system.mem_ctrls.bytesPerActivate::768-895 6 2.28% 91.25% +system.mem_ctrls.bytesPerActivate::896-1023 3 1.14% 92.40% +system.mem_ctrls.bytesPerActivate::1024-1151 20 7.60% 100.00% +system.mem_ctrls.bytesPerActivate::total 263 +system.mem_ctrls.rdPerTurnAround::samples 40 +system.mem_ctrls.rdPerTurnAround::mean 16.100000 +system.mem_ctrls.rdPerTurnAround::gmean 15.846587 +system.mem_ctrls.rdPerTurnAround::stdev 3.484765 +system.mem_ctrls.rdPerTurnAround::12-13 3 7.50% 7.50% +system.mem_ctrls.rdPerTurnAround::14-15 12 30.00% 37.50% +system.mem_ctrls.rdPerTurnAround::16-17 19 47.50% 85.00% +system.mem_ctrls.rdPerTurnAround::18-19 4 10.00% 95.00% +system.mem_ctrls.rdPerTurnAround::20-21 1 2.50% 97.50% +system.mem_ctrls.rdPerTurnAround::34-35 1 2.50% 100.00% +system.mem_ctrls.rdPerTurnAround::total 40 +system.mem_ctrls.wrPerTurnAround::samples 40 +system.mem_ctrls.wrPerTurnAround::mean 16.300000 +system.mem_ctrls.wrPerTurnAround::gmean 16.281263 +system.mem_ctrls.wrPerTurnAround::stdev 0.822753 +system.mem_ctrls.wrPerTurnAround::16 35 87.50% 87.50% +system.mem_ctrls.wrPerTurnAround::18 3 7.50% 95.00% +system.mem_ctrls.wrPerTurnAround::19 2 5.00% 100.00% +system.mem_ctrls.wrPerTurnAround::total 40 +system.mem_ctrls.totQLat 12721 +system.mem_ctrls.totMemAccLat 25014 +system.mem_ctrls.totBusLat 3235 +system.mem_ctrls.avgQLat 19.66 +system.mem_ctrls.avgBusLat 5.00 +system.mem_ctrls.avgMemAccLat 38.66 +system.mem_ctrls.avgRdBW 450.78 +system.mem_ctrls.avgWrBW 454.26 +system.mem_ctrls.avgRdBWSys 959.38 +system.mem_ctrls.avgWrBWSys 956.60 +system.mem_ctrls.peakBW 12800.00 +system.mem_ctrls.busUtil 7.07 +system.mem_ctrls.busUtilRead 3.52 +system.mem_ctrls.busUtilWrite 3.55 +system.mem_ctrls.avgRdQLen 1.00 +system.mem_ctrls.avgWrQLen 25.84 +system.mem_ctrls.readRowHits 435 +system.mem_ctrls.writeRowHits 591 +system.mem_ctrls.readRowHitRate 67.23 +system.mem_ctrls.writeRowHitRate 88.08 +system.mem_ctrls.avgGap 33.37 +system.mem_ctrls.pageHitRate 77.85 +system.mem_ctrls_0.actEnergy 664020 +system.mem_ctrls_0.preEnergy 340032 +system.mem_ctrls_0.readEnergy 3175872 +system.mem_ctrls_0.writeEnergy 2246688 +system.mem_ctrls_0.refreshEnergy 7375680.000000 +system.mem_ctrls_0.actBackEnergy 10273224 +system.mem_ctrls_0.preBackEnergy 269568 +system.mem_ctrls_0.actPowerDownEnergy 25208136 +system.mem_ctrls_0.prePowerDownEnergy 4818816 +system.mem_ctrls_0.selfRefreshEnergy 743760.000000 +system.mem_ctrls_0.totalEnergy 55115796 +system.mem_ctrls_0.averagePower 600.004311 +system.mem_ctrls_0.totalIdleTime 68393 +system.mem_ctrls_0.memoryStateTime::IDLE 346 +system.mem_ctrls_0.memoryStateTime::REF 3126 +system.mem_ctrls_0.memoryStateTime::SREF 798 +system.mem_ctrls_0.memoryStateTime::PRE_PDN 12549 +system.mem_ctrls_0.memoryStateTime::ACT 19759 +system.mem_ctrls_0.memoryStateTime::ACT_PDN 55281 +system.mem_ctrls_1.actEnergy 1285200 +system.mem_ctrls_1.preEnergy 676200 +system.mem_ctrls_1.readEnergy 4215456 +system.mem_ctrls_1.writeEnergy 3198816 +system.mem_ctrls_1.refreshEnergy 6761040.000000 +system.mem_ctrls_1.actBackEnergy 9576912 +system.mem_ctrls_1.preBackEnergy 183552 +system.mem_ctrls_1.actPowerDownEnergy 28147512 +system.mem_ctrls_1.prePowerDownEnergy 3322368 +system.mem_ctrls_1.selfRefreshEnergy 0 +system.mem_ctrls_1.totalEnergy 57367056 +system.mem_ctrls_1.averagePower 624.512089 +system.mem_ctrls_1.totalIdleTime 70328 +system.mem_ctrls_1.memoryStateTime::IDLE 150 +system.mem_ctrls_1.memoryStateTime::REF 2866 +system.mem_ctrls_1.memoryStateTime::SREF 0 +system.mem_ctrls_1.memoryStateTime::PRE_PDN 8652 +system.mem_ctrls_1.memoryStateTime::ACT 18464 +system.mem_ctrls_1.memoryStateTime::ACT_PDN 61727 +system.pwrStateResidencyTicks::UNDEFINED 91859 +system.cpu.clk_domain.clock 1 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 91859 +system.cpu.apic_clk_domain.clock 16 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 91859 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 91859 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 91859 +system.cpu.numCycles 91859 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5381 +system.cpu.committedOps 9748 +system.cpu.num_int_alu_accesses 9654 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 209 +system.cpu.num_conditional_control_insts 899 +system.cpu.num_int_insts 9654 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 18335 +system.cpu.num_int_register_writes 7527 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 6487 +system.cpu.num_cc_register_writes 3536 +system.cpu.num_mem_refs 1988 +system.cpu.num_load_insts 1053 +system.cpu.num_store_insts 935 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 91859 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1208 +system.cpu.op_class::No_OpClass 1 0.01% 0.01% +system.cpu.op_class::IntAlu 7749 79.49% 79.50% +system.cpu.op_class::IntMult 3 0.03% 79.53% +system.cpu.op_class::IntDiv 7 0.07% 79.61% +system.cpu.op_class::FloatAdd 0 0.00% 79.61% +system.cpu.op_class::FloatCmp 0 0.00% 79.61% +system.cpu.op_class::FloatCvt 0 0.00% 79.61% +system.cpu.op_class::FloatMult 0 0.00% 79.61% +system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% +system.cpu.op_class::FloatDiv 0 0.00% 79.61% +system.cpu.op_class::FloatMisc 0 0.00% 79.61% +system.cpu.op_class::FloatSqrt 0 0.00% 79.61% +system.cpu.op_class::SimdAdd 0 0.00% 79.61% +system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% +system.cpu.op_class::SimdAlu 0 0.00% 79.61% +system.cpu.op_class::SimdCmp 0 0.00% 79.61% +system.cpu.op_class::SimdCvt 0 0.00% 79.61% +system.cpu.op_class::SimdMisc 0 0.00% 79.61% +system.cpu.op_class::SimdMult 0 0.00% 79.61% +system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% +system.cpu.op_class::SimdShift 0 0.00% 79.61% +system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% +system.cpu.op_class::SimdSqrt 0 0.00% 79.61% +system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% +system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% +system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% +system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% +system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% +system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% +system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% +system.cpu.op_class::MemRead 1053 10.80% 90.41% +system.cpu.op_class::MemWrite 935 9.59% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 9748 +system.ruby.clk_domain.clock 1 +system.ruby.pwrStateResidencyTicks::UNDEFINED 91859 +system.ruby.delayHist::bucket_size 1 +system.ruby.delayHist::max_bucket 9 +system.ruby.delayHist::samples 2750 +system.ruby.delayHist | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayHist::total 2750 system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 8852 +system.ruby.outstanding_req_hist_seqr::samples 8853 system.ruby.outstanding_req_hist_seqr::mean 1 system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8852 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 8852 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8853 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 8853 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 system.ruby.latency_hist_seqr::samples 8852 @@ -388,36 +388,36 @@ system.ruby.miss_latency_hist_seqr::stdev 33.880423 system.ruby.miss_latency_hist_seqr | 751 54.54% 54.54% | 589 42.77% 97.31% | 26 1.89% 99.20% | 4 0.29% 99.49% | 3 0.22% 99.71% | 4 0.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1377 system.ruby.Directory.incomplete_times_seqr 1376 -system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.996691 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.029937 # Average number of messages in buffer -system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.743740 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999249 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029937 # Average number of messages in buffer -system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999260 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses -system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.976377 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.096364 # Average number of messages in buffer -system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999989 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.059874 # Average number of messages in buffer -system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999935 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.994285 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers03.avg_stall_time 5.979817 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers04.avg_stall_time 5.995167 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.089723 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers07.avg_stall_time 6.744611 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.014947 +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.996691 +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.029937 +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.743740 +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.014990 +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999249 +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029937 +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999260 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 91859 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 +system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.014947 +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.976377 +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.096375 +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999989 +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.059874 +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999935 +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.014990 +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.994285 +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 91859 +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 91859 +system.ruby.memctrl_clk_domain.clock 3 +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.014947 +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.979817 +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.014990 +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.995167 +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.089723 +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.744611 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 91859 system.ruby.network.routers0.percent_links_utilized 7.484297 system.ruby.network.routers0.msg_count.Control::2 1377 system.ruby.network.routers0.msg_count.Data::2 1373 @@ -427,13 +427,13 @@ system.ruby.network.routers0.msg_bytes.Control::2 11016 system.ruby.network.routers0.msg_bytes.Data::2 98856 system.ruby.network.routers0.msg_bytes.Response_Data::4 99144 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.029937 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers02.avg_stall_time 10.743958 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers06.avg_stall_time 1.993359 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998476 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.029937 +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.743958 +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.014947 +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.993359 +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.014990 +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998476 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 91859 system.ruby.network.routers1.percent_links_utilized 7.484297 system.ruby.network.routers1.msg_count.Control::2 1377 system.ruby.network.routers1.msg_count.Data::2 1373 @@ -443,25 +443,25 @@ system.ruby.network.routers1.msg_bytes.Control::2 11016 system.ruby.network.routers1.msg_bytes.Data::2 98856 system.ruby.network.routers1.msg_bytes.Response_Data::4 99144 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.int_link_buffers02.avg_buf_msgs 0.029937 # Average number of messages in buffer -system.ruby.network.int_link_buffers02.avg_stall_time 7.744481 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers08.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.network.int_link_buffers08.avg_stall_time 2.990007 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers09.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.network.int_link_buffers09.avg_stall_time 2.997681 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers13.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.network.int_link_buffers13.avg_stall_time 4.983235 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers14.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.network.int_link_buffers14.avg_stall_time 4.996027 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers17.avg_buf_msgs 0.029937 # Average number of messages in buffer -system.ruby.network.int_link_buffers17.avg_stall_time 9.744154 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers03.avg_stall_time 3.986632 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers04.avg_stall_time 3.996865 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.029937 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers07.avg_stall_time 8.744328 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.029937 +system.ruby.network.int_link_buffers02.avg_stall_time 7.744481 +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.014947 +system.ruby.network.int_link_buffers08.avg_stall_time 2.990007 +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.014990 +system.ruby.network.int_link_buffers09.avg_stall_time 2.997681 +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.014947 +system.ruby.network.int_link_buffers13.avg_stall_time 4.983235 +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.014990 +system.ruby.network.int_link_buffers14.avg_stall_time 4.996027 +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.029937 +system.ruby.network.int_link_buffers17.avg_stall_time 9.744154 +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.014947 +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.986632 +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.014990 +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.996865 +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.029937 +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.744328 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 91859 system.ruby.network.routers2.percent_links_utilized 7.484297 system.ruby.network.routers2.msg_count.Control::2 1377 system.ruby.network.routers2.msg_count.Data::2 1373 @@ -471,7 +471,7 @@ system.ruby.network.routers2.msg_bytes.Control::2 11016 system.ruby.network.routers2.msg_bytes.Data::2 98856 system.ruby.network.routers2.msg_bytes.Response_Data::4 99144 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 91859 system.ruby.network.msg_count.Control 4131 system.ruby.network.msg_count.Data 4119 system.ruby.network.msg_count.Response_Data 4131 @@ -480,7 +480,7 @@ system.ruby.network.msg_byte.Control 33048 system.ruby.network.msg_byte.Data 296568 system.ruby.network.msg_byte.Response_Data 297432 system.ruby.network.msg_byte.Writeback_Control 32952 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 91859 system.ruby.network.routers0.throttle0.link_utilization 7.493006 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373 @@ -511,16 +511,16 @@ system.ruby.network.routers2.throttle1.msg_count.Control::2 1377 system.ruby.network.routers2.throttle1.msg_count.Data::2 1373 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11016 system.ruby.network.routers2.throttle1.msg_bytes.Data::2 98856 -system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 1377 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 1377 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 1377 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 1373 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 1373 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 1373 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_1::bucket_size 1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 +system.ruby.delayVCHist.vnet_1::samples 1377 +system.ruby.delayVCHist.vnet_1 | 1377 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayVCHist.vnet_1::total 1377 +system.ruby.delayVCHist.vnet_2::bucket_size 1 +system.ruby.delayVCHist.vnet_2::max_bucket 9 +system.ruby.delayVCHist.vnet_2::samples 1373 +system.ruby.delayVCHist.vnet_2 | 1373 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayVCHist.vnet_2::total 1373 system.ruby.LD.latency_hist_seqr::bucket_size 32 system.ruby.LD.latency_hist_seqr::max_bucket 319 system.ruby.LD.latency_hist_seqr::samples 1045 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini index bc04df7fd..1bbdae21e 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -85,6 +86,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -100,14 +102,14 @@ eventq_index=0 [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -121,6 +123,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -133,15 +136,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=X86TLB @@ -166,14 +170,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -187,6 +191,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -199,15 +204,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=X86LocalApic @@ -253,14 +259,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -274,6 +280,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -286,15 +293,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -330,7 +338,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -339,14 +347,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/x86/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -370,6 +379,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -381,7 +391,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -389,6 +399,13 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -397,6 +414,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -404,7 +422,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout index 17523a325..30d3fbf05 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:20 -gem5 executing on e108600-lin, pid 18567 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-timing +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:21 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87155 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 30886500 because target called exit() +Exiting @ tick 31247500 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index b6ef5972c..e9a5f137e 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,501 +1,501 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 31247500 # Number of ticks simulated -final_tick 31247500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 377585 # Simulator instruction rate (inst/s) -host_op_rate 682900 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2185869298 # Simulator tick rate (ticks/s) -host_mem_usage 268708 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 5381 # Number of instructions simulated -sim_ops 9748 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory -system.physmem.bytes_read::total 23104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 14528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 14528 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory -system.physmem.num_reads::total 361 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 464933195 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 274453956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 739387151 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 464933195 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 464933195 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 464933195 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 274453956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 739387151 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 31247500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 62495 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5381 # Number of instructions committed -system.cpu.committedOps 9748 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 209 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls -system.cpu.num_int_insts 9654 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 18335 # number of times the integer registers were read -system.cpu.num_int_register_writes 7527 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read -system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written -system.cpu.num_mem_refs 1988 # number of memory refs -system.cpu.num_load_insts 1053 # Number of load instructions -system.cpu.num_store_insts 935 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 62494.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1208 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction -system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction -system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction -system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 9748 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 80.527852 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 80.527852 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019660 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019660 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits -system.cpu.dcache.overall_hits::total 1854 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses -system.cpu.dcache.overall_misses::total 134 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3465000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3465000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4977000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4977000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8442000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8442000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8442000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8442000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3410000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3410000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4898000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4898000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8308000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8308000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8308000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8308000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 105.231814 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 105.231814 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.051383 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.051383 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 13956 # Number of tag accesses -system.cpu.icache.tags.data_accesses 13956 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 6636 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6636 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 6636 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6636 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 6636 # number of overall hits -system.cpu.icache.overall_hits::total 6636 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses -system.cpu.icache.overall_misses::total 228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14315500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14315500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14315500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14315500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14315500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14315500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6864 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 6864 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6864 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.033217 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.033217 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.033217 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62787.280702 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62787.280702 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62787.280702 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62787.280702 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62787.280702 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62787.280702 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14087500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14087500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14087500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14087500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14087500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14087500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61787.280702 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61787.280702 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61787.280702 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61787.280702 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61787.280702 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61787.280702 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 185.792229 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 361 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002770 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.219349 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 80.572880 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003211 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002459 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005670 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 361 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 247 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011017 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3257 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits -system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 227 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 227 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 55 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 227 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 361 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses -system.cpu.l2cache.overall_misses::total 361 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4779500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4779500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13734000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 13734000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3327500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3327500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13734000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8107000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21841000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13734000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8107000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21841000 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 228 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 228 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 55 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 55 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 228 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 134 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 362 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 228 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 134 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 362 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.995614 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997238 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.202643 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.202643 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.202643 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60501.385042 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.202643 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60501.385042 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 227 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 227 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 55 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3989500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3989500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11464000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11464000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2777500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2777500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11464000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6767000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18231000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11464000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6767000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18231000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995614 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.202643 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.202643 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.202643 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.385042 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.202643 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.385042 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 228 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 724 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 362 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002762 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.052559 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 361 99.72% 99.72% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.28% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 361 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 282 # Transaction distribution -system.membus.trans_dist::ReadExReq 79 # Transaction distribution -system.membus.trans_dist::ReadExResp 79 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 282 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 361 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 361 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 361 # Request fanout histogram -system.membus.reqLayer0.occupancy 361500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1805000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 5.8 # Layer utilization (%) +sim_seconds 0.000031 +sim_ticks 31247500 +final_tick 31247500 +sim_freq 1000000000000 +host_inst_rate 194718 +host_op_rate 352470 +host_tick_rate 1129073998 +host_mem_usage 278812 +host_seconds 0.03 +sim_insts 5381 +sim_ops 9748 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 31247500 +system.physmem.bytes_read::cpu.inst 14528 +system.physmem.bytes_read::cpu.data 8576 +system.physmem.bytes_read::total 23104 +system.physmem.bytes_inst_read::cpu.inst 14528 +system.physmem.bytes_inst_read::total 14528 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+system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.202643 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.202643 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.202643 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.385042 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.202643 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.385042 +system.cpu.toL2Bus.snoop_filter.tot_requests 362 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 31247500 +system.cpu.toL2Bus.trans_dist::ReadResp 283 +system.cpu.toL2Bus.trans_dist::ReadExReq 79 +system.cpu.toL2Bus.trans_dist::ReadExResp 79 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 228 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 +system.cpu.toL2Bus.pkt_count::total 724 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8576 +system.cpu.toL2Bus.pkt_size::total 23168 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 362 +system.cpu.toL2Bus.snoop_fanout::mean 0.002762 +system.cpu.toL2Bus.snoop_fanout::stdev 0.052559 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 361 99.72% 99.72% +system.cpu.toL2Bus.snoop_fanout::1 1 0.28% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 362 +system.cpu.toL2Bus.reqLayer0.occupancy 181000 +system.cpu.toL2Bus.reqLayer0.utilization 0.6 +system.cpu.toL2Bus.respLayer0.occupancy 342000 +system.cpu.toL2Bus.respLayer0.utilization 1.1 +system.cpu.toL2Bus.respLayer1.occupancy 201000 +system.cpu.toL2Bus.respLayer1.utilization 0.6 +system.membus.snoop_filter.tot_requests 361 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 31247500 +system.membus.trans_dist::ReadResp 282 +system.membus.trans_dist::ReadExReq 79 +system.membus.trans_dist::ReadExResp 79 +system.membus.trans_dist::ReadSharedReq 282 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 +system.membus.pkt_count::total 722 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 +system.membus.pkt_size::total 23104 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 361 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 361 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 361 +system.membus.reqLayer0.occupancy 361500 +system.membus.reqLayer0.utilization 1.2 +system.membus.respLayer1.occupancy 1805000 +system.membus.respLayer1.utilization 5.8 ---------- End Simulation Statistics ---------- |