diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-13 12:30:30 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-13 12:30:30 -0600 |
| commit | 0d46708dc20c438d29bd724fb7d4b54d4d2f318a (patch) | |
| tree | 337e1a7404c57817cd08106a0369542ea5c4ac30 /tests/quick/se/00.hello/ref/x86/linux | |
| parent | 9b05e96b9efdb9cdcc4e40ef9c96b1228df7a175 (diff) | |
| download | gem5-0d46708dc20c438d29bd724fb7d4b54d4d2f318a.tar.xz | |
bp: fix up stats for changes to branch predictor
Diffstat (limited to 'tests/quick/se/00.hello/ref/x86/linux')
| -rwxr-xr-x | tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout | 6 | ||||
| -rw-r--r-- | tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt | 834 |
2 files changed, 420 insertions, 420 deletions
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index ac1cd3610..eda7f85a5 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 14:04:05 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 18:26:23 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 11989500 because target called exit() +Exiting @ tick 12299500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 658a056fb..475f993c2 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,264 +1,264 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11989500 # Number of ticks simulated -final_tick 11989500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 12299500 # Number of ticks simulated +final_tick 12299500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61798 # Simulator instruction rate (inst/s) -host_op_rate 111900 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 136747555 # Simulator tick rate (ticks/s) -host_mem_usage 218292 # Number of bytes of host memory used +host_inst_rate 59298 # Simulator instruction rate (inst/s) +host_op_rate 107375 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 134612595 # Simulator tick rate (ticks/s) +host_mem_usage 218308 # Number of bytes of host memory used host_seconds 0.09 # Real time elapsed on the host sim_insts 5416 # Number of instructions simulated sim_ops 9809 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 28288 # Number of bytes read from this memory -system.physmem.bytes_inst_read 18944 # Number of instructions bytes read from this memory +system.physmem.bytes_read 28864 # Number of bytes read from this memory +system.physmem.bytes_inst_read 19328 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 442 # Number of read requests responded to by this memory +system.physmem.num_reads 451 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2359397806 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1580049210 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2359397806 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2346762063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1571445994 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2346762063 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 23980 # number of cpu cycles simulated +system.cpu.numCycles 24600 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 3019 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3019 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 495 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2695 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 978 # Number of BTB hits +system.cpu.BPredUnit.lookups 3225 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3225 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 566 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2653 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 811 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7194 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13831 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3019 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 978 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3921 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2194 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3367 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1866 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 16182 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.543567 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.980612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7427 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15574 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3225 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 811 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4199 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2532 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3117 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 203 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1968 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 16907 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.630863 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.070076 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 12367 76.42% 76.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 166 1.03% 77.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 172 1.06% 78.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 238 1.47% 79.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 224 1.38% 81.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 191 1.18% 82.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 276 1.71% 84.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 137 0.85% 85.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2411 14.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 12804 75.73% 75.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 179 1.06% 76.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 164 0.97% 77.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 216 1.28% 79.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 176 1.04% 80.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 185 1.09% 81.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 253 1.50% 82.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 169 1.00% 83.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2761 16.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 16182 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.125897 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.576772 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7550 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3315 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3508 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 122 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1687 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 23802 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1687 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7843 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2077 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 553 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3329 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 693 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22457 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 68 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 553 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 21026 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 47090 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 47074 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 16907 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.131098 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.633089 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7993 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3065 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3795 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1928 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 26201 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1928 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8331 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1936 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 442 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3571 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 699 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 24623 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 40 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 586 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 22939 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 51440 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 51424 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9368 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 11658 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 13571 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 33 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1820 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2219 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1751 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20306 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 16792 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10001 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12754 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 16182 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.037696 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.845376 # Number of insts issued each cycle +system.cpu.rename.skidInsts 1885 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2380 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1795 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 21756 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 17955 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 74 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11342 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13993 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 26 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 16907 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.061986 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.892645 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10903 67.38% 67.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1372 8.48% 75.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1062 6.56% 82.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 680 4.20% 86.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 659 4.07% 90.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 684 4.23% 94.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 588 3.63% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 200 1.24% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 34 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11435 67.63% 67.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1387 8.20% 75.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1028 6.08% 81.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 682 4.03% 85.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 697 4.12% 90.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 717 4.24% 94.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 667 3.95% 98.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 261 1.54% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 33 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 16182 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 16907 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 86 64.66% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 24 18.05% 82.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 17.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 147 74.24% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 30 15.15% 89.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 21 10.61% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13517 80.50% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1828 10.89% 91.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1443 8.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14483 80.66% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1993 11.10% 91.79% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1475 8.21% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 16792 # Type of FU issued -system.cpu.iq.rate 0.700250 # Inst issue rate -system.cpu.iq.fu_busy_cnt 133 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007920 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 49947 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 30352 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 15608 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17955 # Type of FU issued +system.cpu.iq.rate 0.729878 # Inst issue rate +system.cpu.iq.fu_busy_cnt 198 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011028 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 53081 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 33143 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16452 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 16917 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 18145 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 142 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 152 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1163 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 817 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1324 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 861 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1687 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1417 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 38 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20343 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 26 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2219 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1751 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 1928 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1329 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 21795 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2380 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1795 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 35 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 65 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 525 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 590 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 15942 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1725 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 850 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 63 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 653 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 716 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16888 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1847 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1067 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3065 # number of memory reference insts executed -system.cpu.iew.exec_branches 1589 # Number of branches executed -system.cpu.iew.exec_stores 1340 # Number of stores executed -system.cpu.iew.exec_rate 0.664804 # Inst execution rate -system.cpu.iew.wb_sent 15766 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 15612 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10251 # num instructions producing a value -system.cpu.iew.wb_consumers 15131 # num instructions consuming a value +system.cpu.iew.exec_refs 3212 # number of memory reference insts executed +system.cpu.iew.exec_branches 1649 # Number of branches executed +system.cpu.iew.exec_stores 1365 # Number of stores executed +system.cpu.iew.exec_rate 0.686504 # Inst execution rate +system.cpu.iew.wb_sent 16662 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16456 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10670 # num instructions producing a value +system.cpu.iew.wb_consumers 15796 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.651043 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.677483 # average fanout of values written-back +system.cpu.iew.wb_rate 0.668943 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.675487 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5416 # The number of committed instructions system.cpu.commit.commitCommittedOps 9809 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 10533 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 11985 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 495 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14495 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.676716 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.510487 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 593 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 14979 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.654850 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.499757 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10831 74.72% 74.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1349 9.31% 84.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 680 4.69% 88.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 780 5.38% 94.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 337 2.32% 96.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 129 0.89% 97.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 140 0.97% 98.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 65 0.45% 98.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 184 1.27% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11331 75.65% 75.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1373 9.17% 84.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 652 4.35% 89.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 726 4.85% 94.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 372 2.48% 96.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 130 0.87% 97.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 138 0.92% 98.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 68 0.45% 98.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 189 1.26% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14495 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14979 # Number of insts commited each cycle system.cpu.commit.committedInsts 5416 # Number of instructions committed system.cpu.commit.committedOps 9809 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -269,62 +269,62 @@ system.cpu.commit.branches 1214 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 9714 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 184 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 189 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 34653 # The number of ROB reads -system.cpu.rob.rob_writes 42403 # The number of ROB writes +system.cpu.rob.rob_reads 36584 # The number of ROB reads +system.cpu.rob.rob_writes 45550 # The number of ROB writes system.cpu.timesIdled 150 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7798 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 7693 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5416 # Number of Instructions Simulated system.cpu.committedOps 9809 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5416 # Number of Instructions Simulated -system.cpu.cpi 4.427622 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.427622 # CPI: Total CPI of All Threads -system.cpu.ipc 0.225855 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.225855 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 23430 # number of integer regfile reads -system.cpu.int_regfile_writes 14518 # number of integer regfile writes +system.cpu.cpi 4.542097 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.542097 # CPI: Total CPI of All Threads +system.cpu.ipc 0.220163 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.220163 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 24791 # number of integer regfile reads +system.cpu.int_regfile_writes 15157 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7136 # number of misc regfile reads +system.cpu.misc_regfile_reads 7406 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 140.870525 # Cycle average of tags in use -system.cpu.icache.total_refs 1498 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 298 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.026846 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 146.671178 # Cycle average of tags in use +system.cpu.icache.total_refs 1576 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.184211 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 140.870525 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.068784 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.068784 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1498 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1498 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1498 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1498 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1498 # number of overall hits -system.cpu.icache.overall_hits::total 1498 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses -system.cpu.icache.overall_misses::total 368 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13394000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13394000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13394000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13394000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13394000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13394000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1866 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1866 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1866 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1866 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1866 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1866 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.197213 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.197213 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.197213 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36396.739130 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36396.739130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36396.739130 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 146.671178 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071617 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071617 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1576 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1576 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1576 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1576 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1576 # number of overall hits +system.cpu.icache.overall_hits::total 1576 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 392 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 392 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 392 # 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number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -333,80 +333,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 298 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 298 # 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mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.159700 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.159700 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35139.261745 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35139.261745 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35139.261745 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 88 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 88 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 88 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 88 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 88 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10684500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10684500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10684500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10684500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10684500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10684500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.154472 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.154472 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.154472 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35146.381579 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35146.381579 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35146.381579 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 83.526549 # Cycle average of tags in use -system.cpu.dcache.total_refs 2275 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 145 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.689655 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 85.091432 # Cycle average of tags in use +system.cpu.dcache.total_refs 2365 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.979730 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 83.526549 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020392 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020392 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1417 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1417 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 85.091432 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020774 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020774 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1507 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1507 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2275 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2275 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2275 # number of overall hits -system.cpu.dcache.overall_hits::total 2275 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 111 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 111 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2365 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2365 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2365 # number of overall hits +system.cpu.dcache.overall_hits::total 2365 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 117 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 117 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 187 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 187 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 187 # number of overall misses -system.cpu.dcache.overall_misses::total 187 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3859500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3859500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2916500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2916500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6776000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6776000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6776000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6776000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1528 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1528 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 193 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 193 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 193 # number of overall misses +system.cpu.dcache.overall_misses::total 193 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4056500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4056500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2917500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2917500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6974000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6974000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6974000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6974000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1624 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1624 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2462 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2462 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2462 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2462 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.072644 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2558 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2558 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2558 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2558 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.072044 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.075955 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075955 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34770.270270 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38375 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36235.294118 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36235.294118 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.075450 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075450 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34670.940171 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38388.157895 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36134.715026 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36134.715026 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -415,101 +415,101 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 41 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 41 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 41 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 41 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 41 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 41 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 44 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 44 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 44 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 44 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 44 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 44 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 73 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 73 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2463000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2463000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2688500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2688500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5151500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5151500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5151500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5151500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045812 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 149 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2572000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2572000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2689500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2689500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5261500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5261500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5261500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5261500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044951 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059301 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059301 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35185.714286 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35375 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35284.246575 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35284.246575 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058249 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058249 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35232.876712 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35388.157895 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35312.080537 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35312.080537 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 173.809724 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 180.810821 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 365 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005479 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 374 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005348 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 140.468506 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 33.341218 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004287 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001017 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005304 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 146.260836 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 34.549985 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004464 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001054 # 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number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 302 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 149 # number of overall misses +system.cpu.l2cache.overall_misses::total 451 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10365500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2486500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12852000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2603000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2603000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 10158000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4986000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15144000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 10158000 # 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number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 73 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 377 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 298 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 444 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 298 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 444 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993289 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 304 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 149 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 453 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 304 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 453 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993421 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993289 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993421 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993289 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993421 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34317.567568 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34042.857143 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34322.847682 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34061.643836 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34250 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34317.567568 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34150.684932 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34317.567568 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34150.684932 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34322.847682 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34322.847682 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -518,42 +518,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 73 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 375 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 442 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 442 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9202000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2167000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11369000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2368500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2368500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9202000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4535500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13737500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9202000 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11655500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2369500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2369500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9393500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4631500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14025000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9393500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4631500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14025000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993289 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993289 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.837838 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30957.142857 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31164.473684 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.837838 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.068493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.837838 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.068493 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31104.304636 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30986.301370 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31177.631579 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31104.304636 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31083.892617 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31104.304636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31083.892617 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |