diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-05-22 11:38:04 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-05-22 11:38:04 -0500 |
| commit | 0bff8eb210fedd89baed36ecab3608bb259ff520 (patch) | |
| tree | dc4a9c3ec0a1ab297a69a3fec3111d7e431b09cd /tests/quick/se/00.hello/ref/x86 | |
| parent | 1031fe7b6f6e29e3367750c3029b4dc850e062f5 (diff) | |
| download | gem5-0bff8eb210fedd89baed36ecab3608bb259ff520.tar.xz | |
X86 Regression: update stats due to cc register split
Diffstat (limited to 'tests/quick/se/00.hello/ref/x86')
13 files changed, 397 insertions, 388 deletions
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini index 1666732e2..c82cb42ab 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini @@ -516,7 +516,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +executable=tests/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index 9c9739cf4..b715ba6b6 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -1,11 +1,13 @@ +Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simout +Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:30 -gem5 started May 8 2012 15:49:56 -gem5 executing on piton +gem5 compiled May 21 2012 19:00:49 +gem5 started May 21 2012 19:03:20 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 12299500 because target called exit() +Exiting @ tick 12198000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index cb09e3c8e..f253ef45b 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12299500 # Number of ticks simulated -final_tick 12299500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 12198000 # Number of ticks simulated +final_tick 12198000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24245 # Simulator instruction rate (inst/s) -host_op_rate 43905 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55046151 # Simulator tick rate (ticks/s) -host_mem_usage 223460 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host +host_inst_rate 10821 # Simulator instruction rate (inst/s) +host_op_rate 19598 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24369729 # Simulator tick rate (ticks/s) +host_mem_usage 271424 # Number of bytes of host memory used +host_seconds 0.50 # Real time elapsed on the host sim_insts 5416 # Number of instructions simulated sim_ops 9809 # Number of ops (including micro ops) simulated system.physmem.bytes_read 28864 # Number of bytes read from this memory @@ -17,248 +17,249 @@ system.physmem.bytes_written 0 # Nu system.physmem.num_reads 451 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2346762063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1571445994 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2346762063 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2366289556 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1584522053 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2366289556 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 24600 # number of cpu cycles simulated +system.cpu.numCycles 24397 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 3225 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3225 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 566 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2653 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 811 # Number of BTB hits +system.cpu.BPredUnit.lookups 3206 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3206 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 560 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2627 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 792 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7427 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 15574 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3225 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 811 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4199 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2532 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3117 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 203 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1968 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 16907 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.630863 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.070076 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7375 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15410 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3206 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 792 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4170 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2487 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3163 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 16 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 98 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1951 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 281 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 16727 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.635918 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.075272 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 12804 75.73% 75.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 179 1.06% 76.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 164 0.97% 77.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 216 1.28% 79.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 176 1.04% 80.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 185 1.09% 81.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 253 1.50% 82.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 169 1.00% 83.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2761 16.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 12659 75.68% 75.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 177 1.06% 76.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 166 0.99% 77.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 214 1.28% 79.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 171 1.02% 80.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 175 1.05% 81.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 250 1.49% 82.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 166 0.99% 83.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2749 16.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 16907 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.131098 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.633089 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7993 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3065 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3795 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1928 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 26201 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1928 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8331 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1936 # Number of cycles rename is blocking +system.cpu.fetch.rateDist::total 16727 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.131410 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.631635 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7836 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3109 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3749 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 128 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1905 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 26025 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1905 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8180 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1960 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 442 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3571 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 699 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 24623 # Number of instructions processed by rename +system.cpu.rename.RunCycles 3522 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 718 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 24463 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 40 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 586 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 22939 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 51440 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 51424 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 50 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 591 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 35223 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 70482 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 70466 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 9368 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 13571 # Number of HB maps that are undone due to squashing +system.cpu.rename.CommittedMaps 14707 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 20516 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 33 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1885 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2380 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1795 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 1918 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2376 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1791 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21756 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17955 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 74 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11342 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 13993 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 26 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 16907 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.061986 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.892645 # Number of insts issued each cycle +system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 21692 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 17854 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 82 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11255 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 20549 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 25 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 16727 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.067376 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.893384 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11435 67.63% 67.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1387 8.20% 75.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1028 6.08% 81.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 682 4.03% 85.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 697 4.12% 90.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 717 4.24% 94.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 667 3.95% 98.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 261 1.54% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11276 67.41% 67.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1383 8.27% 75.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1035 6.19% 81.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 667 3.99% 85.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 692 4.14% 89.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 723 4.32% 94.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 673 4.02% 98.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 245 1.46% 99.80% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 33 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 16907 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 16727 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 147 74.24% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 74.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 30 15.15% 89.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 21 10.61% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 140 73.30% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 30 15.71% 89.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 21 10.99% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14483 80.66% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.69% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1993 11.10% 91.79% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1475 8.21% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14397 80.64% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.66% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1982 11.10% 91.76% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1471 8.24% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17955 # Type of FU issued -system.cpu.iq.rate 0.729878 # Inst issue rate -system.cpu.iq.fu_busy_cnt 198 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011028 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 53081 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 33143 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16452 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17854 # Type of FU issued +system.cpu.iq.rate 0.731811 # Inst issue rate +system.cpu.iq.fu_busy_cnt 191 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010698 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 52700 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 32991 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16402 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18145 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 18037 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 152 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 151 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1324 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1320 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 20 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 861 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 857 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1928 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1905 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 1329 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21795 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2380 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1795 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 35 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 21730 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 24 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2376 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1791 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 63 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 653 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 716 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16888 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1847 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1067 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 59 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 631 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 690 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16824 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1844 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1030 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3212 # number of memory reference insts executed -system.cpu.iew.exec_branches 1649 # Number of branches executed -system.cpu.iew.exec_stores 1365 # Number of stores executed -system.cpu.iew.exec_rate 0.686504 # Inst execution rate -system.cpu.iew.wb_sent 16662 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16456 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10670 # num instructions producing a value -system.cpu.iew.wb_consumers 15796 # num instructions consuming a value +system.cpu.iew.exec_refs 3203 # number of memory reference insts executed +system.cpu.iew.exec_branches 1645 # Number of branches executed +system.cpu.iew.exec_stores 1359 # Number of stores executed +system.cpu.iew.exec_rate 0.689593 # Inst execution rate +system.cpu.iew.wb_sent 16593 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16406 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10679 # num instructions producing a value +system.cpu.iew.wb_consumers 24448 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.668943 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.675487 # average fanout of values written-back +system.cpu.iew.wb_rate 0.672460 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.436805 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5416 # The number of committed instructions system.cpu.commit.commitCommittedOps 9809 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 11985 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 11920 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 593 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14979 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.654850 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.499757 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 571 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 14822 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.661787 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.507902 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11331 75.65% 75.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1373 9.17% 84.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 652 4.35% 89.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 726 4.85% 94.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 372 2.48% 96.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 130 0.87% 97.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 138 0.92% 98.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 68 0.45% 98.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 189 1.26% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11181 75.44% 75.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1365 9.21% 84.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 653 4.41% 89.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 730 4.93% 93.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 365 2.46% 96.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 129 0.87% 97.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 139 0.94% 98.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71 0.48% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 189 1.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14979 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14822 # Number of insts commited each cycle system.cpu.commit.committedInsts 5416 # Number of instructions committed system.cpu.commit.committedOps 9809 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -271,60 +272,60 @@ system.cpu.commit.int_insts 9714 # Nu system.cpu.commit.function_calls 0 # Number of function calls committed. system.cpu.commit.bw_lim_events 189 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 36584 # The number of ROB reads -system.cpu.rob.rob_writes 45550 # The number of ROB writes +system.cpu.rob.rob_reads 36362 # The number of ROB reads +system.cpu.rob.rob_writes 45397 # The number of ROB writes system.cpu.timesIdled 150 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7693 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 7670 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5416 # Number of Instructions Simulated system.cpu.committedOps 9809 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5416 # Number of Instructions Simulated -system.cpu.cpi 4.542097 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.542097 # CPI: Total CPI of All Threads -system.cpu.ipc 0.220163 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.220163 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 24791 # number of integer regfile reads -system.cpu.int_regfile_writes 15157 # number of integer regfile writes +system.cpu.cpi 4.504616 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.504616 # CPI: Total CPI of All Threads +system.cpu.ipc 0.221995 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.221995 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 35454 # number of integer regfile reads +system.cpu.int_regfile_writes 22063 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7406 # number of misc regfile reads +system.cpu.misc_regfile_reads 7402 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 146.671178 # Cycle average of tags in use -system.cpu.icache.total_refs 1576 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 145.636183 # Cycle average of tags in use +system.cpu.icache.total_refs 1561 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.184211 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.134868 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 146.671178 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071617 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071617 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1576 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1576 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1576 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1576 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1576 # number of overall hits -system.cpu.icache.overall_hits::total 1576 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 392 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 392 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 392 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 392 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 392 # number of overall misses -system.cpu.icache.overall_misses::total 392 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13905000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13905000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13905000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13905000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13905000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13905000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1968 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1968 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1968 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1968 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1968 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1968 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199187 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.199187 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.199187 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35471.938776 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35471.938776 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35471.938776 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 145.636183 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071111 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071111 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1561 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1561 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1561 # 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miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35555.128205 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35555.128205 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35555.128205 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -333,40 +334,40 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 88 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 88 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 88 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 88 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 88 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 86 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 86 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 86 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 304 # 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mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.154472 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35146.381579 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35146.381579 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35146.381579 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10687000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10687000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10687000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10687000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10687000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10687000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35154.605263 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35154.605263 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35154.605263 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 85.091432 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 84.751522 # Cycle average of tags in use system.cpu.dcache.total_refs 2365 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 15.979730 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 85.091432 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020774 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020774 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 84.751522 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020691 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020691 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1507 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1507 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits @@ -375,38 +376,38 @@ system.cpu.dcache.demand_hits::cpu.data 2365 # nu system.cpu.dcache.demand_hits::total 2365 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 2365 # number of overall hits system.cpu.dcache.overall_hits::total 2365 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 117 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 117 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 193 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 193 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 193 # number of overall misses -system.cpu.dcache.overall_misses::total 193 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4056500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4056500 # number of ReadReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 191 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 191 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 191 # number of overall misses +system.cpu.dcache.overall_misses::total 191 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4030500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4030500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 2917500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 2917500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6974000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6974000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6974000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6974000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1624 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1624 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 6948000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6948000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6948000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6948000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1622 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1622 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2558 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2558 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2558 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2558 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.072044 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2556 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2556 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2556 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2556 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070900 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.075450 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075450 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34670.940171 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.074726 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074726 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35047.826087 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38388.157895 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36134.715026 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36134.715026 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36376.963351 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36376.963351 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -415,12 +416,12 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 44 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 44 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 44 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 44 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 44 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 44 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 42 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 42 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 42 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 42 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 73 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 73 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses @@ -429,34 +430,34 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 149 system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2572000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2572000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2574000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2574000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2689500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2689500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5261500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5261500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5261500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5261500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044951 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5263500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5263500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5263500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5263500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045006 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058249 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058249 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35232.876712 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058294 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058294 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35260.273973 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35388.157895 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35312.080537 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35312.080537 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35325.503356 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35325.503356 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 180.810821 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 179.622577 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 374 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005348 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 146.260836 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 34.549985 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004464 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001054 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005518 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 145.234150 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 34.388427 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004432 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001049 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005482 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -474,17 +475,17 @@ system.cpu.l2cache.demand_misses::total 451 # nu system.cpu.l2cache.overall_misses::cpu.inst 302 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 149 # number of overall misses system.cpu.l2cache.overall_misses::total 451 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10365500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10368000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2486500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12852000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12854500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2603000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2603000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 10365500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 10368000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 5089500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15455000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 10365500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 15457500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 10368000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 5089500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15455000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15457500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 73 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 377 # number of ReadReq accesses(hits+misses) @@ -503,12 +504,12 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993421 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993421 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34322.847682 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.125828 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34061.643836 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34250 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34322.847682 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.125828 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34322.847682 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.125828 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -529,17 +530,17 @@ system.cpu.l2cache.demand_mshr_misses::total 451 system.cpu.l2cache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9393500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2262000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11655500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9394000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2263500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11657500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2369500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2369500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9393500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4631500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14025000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9393500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4631500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14025000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9394000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4633000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14027000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9394000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4633000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14027000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses @@ -547,13 +548,13 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993421 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31104.304636 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30986.301370 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31105.960265 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31006.849315 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31177.631579 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31104.304636 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31083.892617 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31104.304636 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31083.892617 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31105.960265 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31093.959732 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31105.960265 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31093.959732 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini index c00e48a14..8422307f0 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -103,7 +103,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +executable=tests/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout index 972a98347..4c14d0aa7 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:30 -gem5 started May 8 2012 15:49:56 -gem5 executing on piton +gem5 compiled May 21 2012 19:00:49 +gem5 started May 21 2012 19:10:03 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index 0f9f946d6..9d71bb46a 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000006 # Nu sim_ticks 5651000 # Number of ticks simulated final_tick 5651000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 330960 # Simulator instruction rate (inst/s) -host_op_rate 598371 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 344132346 # Simulator tick rate (ticks/s) -host_mem_usage 213012 # Number of bytes of host memory used +host_inst_rate 288907 # Simulator instruction rate (inst/s) +host_op_rate 522587 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 300697068 # Simulator tick rate (ticks/s) +host_mem_usage 260908 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 5417 # Number of instructions simulated sim_ops 9810 # Number of ops (including micro ops) simulated @@ -33,8 +33,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls system.cpu.num_int_insts 9715 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 21313 # number of times the integer registers were read -system.cpu.num_int_register_writes 9368 # number of times the integer registers were written +system.cpu.num_int_register_reads 29928 # number of times the integer registers were read +system.cpu.num_int_register_writes 14707 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 1990 # number of memory refs diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini index e879347ff..ab4fb38df 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini @@ -99,7 +99,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +executable=tests/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats index 442d60f8b..a99abad11 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:50:07 +Real time: May/21/2012 19:13:48 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.37 -Virtual_time_in_minutes: 0.00616667 -Virtual_time_in_hours: 0.000102778 -Virtual_time_in_days: 4.28241e-06 +Virtual_time_in_seconds: 0.46 +Virtual_time_in_minutes: 0.00766667 +Virtual_time_in_hours: 0.000127778 +Virtual_time_in_days: 5.32407e-06 Ruby_current_time: 276484 Ruby_start_time: 0 Ruby_cycles: 276484 -mbytes_resident: 52 -mbytes_total: 227.848 -resident_ratio: 0.228223 +mbytes_resident: 53.1328 +mbytes_total: 274.648 +resident_ratio: 0.193486 ruby_cycles_executed: [ 276485 ] @@ -125,11 +125,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 13872 -page_faults: 0 +page_reclaims: 15001 +page_faults: 3 swaps: 0 block_inputs: 0 -block_outputs: 88 +block_outputs: 0 Network Stats ------------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout index 15a51cba3..ab4279ad8 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby/simout +Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:30 -gem5 started May 8 2012 15:50:07 -gem5 executing on piton +gem5 compiled May 21 2012 19:00:49 +gem5 started May 21 2012 19:13:47 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 3c66f2b85..0a683990f 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000276 # Nu sim_ticks 276484 # Number of ticks simulated final_tick 276484 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 46315 # Simulator instruction rate (inst/s) -host_op_rate 83864 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2363372 # Simulator tick rate (ticks/s) -host_mem_usage 233320 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 40683 # Simulator instruction rate (inst/s) +host_op_rate 73662 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2075784 # Simulator tick rate (ticks/s) +host_mem_usage 281244 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 5417 # Number of instructions simulated sim_ops 9810 # Number of ops (including micro ops) simulated system.physmem.bytes_read 62348 # Number of bytes read from this memory @@ -33,8 +33,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls system.cpu.num_int_insts 9715 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 21313 # number of times the integer registers were read -system.cpu.num_int_register_writes 9368 # number of times the integer registers were written +system.cpu.num_int_register_reads 29928 # number of times the integer registers were read +system.cpu.num_int_register_writes 14707 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 1990 # number of memory refs diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini index b01f0f148..dddeed309 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini @@ -185,7 +185,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +executable=tests/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout index f6aa045a2..bbf370aff 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing/simout +Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:05:30 -gem5 started May 8 2012 15:50:07 -gem5 executing on piton +gem5 compiled May 21 2012 19:00:49 +gem5 started May 21 2012 19:09:59 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index bb825e929..2734be727 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000029 # Nu sim_ticks 28768000 # Number of ticks simulated final_tick 28768000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 193646 # Simulator instruction rate (inst/s) -host_op_rate 350298 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1026195488 # Simulator tick rate (ticks/s) -host_mem_usage 221892 # Number of bytes of host memory used +host_inst_rate 209143 # Simulator instruction rate (inst/s) +host_op_rate 378428 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1108849830 # Simulator tick rate (ticks/s) +host_mem_usage 269844 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host sim_insts 5417 # Number of instructions simulated sim_ops 9810 # Number of ops (including micro ops) simulated @@ -32,8 +32,8 @@ system.cpu.num_func_calls 0 # nu system.cpu.num_conditional_control_insts 904 # number of instructions that are conditional controls system.cpu.num_int_insts 9715 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 21313 # number of times the integer registers were read -system.cpu.num_int_register_writes 9368 # number of times the integer registers were written +system.cpu.num_int_register_reads 29928 # number of times the integer registers were read +system.cpu.num_int_register_writes 14707 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 1990 # number of memory refs |