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authorAli Saidi <Ali.Saidi@ARM.com>2012-11-02 11:50:06 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2012-11-02 11:50:06 -0500
commit1dbf9bb4ca6cc3bee68713a28778c1bdfe222f75 (patch)
tree81108e7ff1951b652258f53bd5615a617b734ce2 /tests/quick/se/00.hello/ref/x86
parentddd6af414cdd4939f4ff382f0e83e7dfa695781d (diff)
downloadgem5-1dbf9bb4ca6cc3bee68713a28778c1bdfe222f75.tar.xz
update stats for preceeding changes
Diffstat (limited to 'tests/quick/se/00.hello/ref/x86')
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini71
-rwxr-xr-xtests/quick/se/00.hello/ref/x86/linux/o3-timing/simout10
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt1046
3 files changed, 571 insertions, 556 deletions
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
index 98b722b0c..85178b3d5 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -78,6 +78,7 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@@ -129,18 +130,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
-response_latency=1000
+response_latency=2
size=262144
subblock_size=0
system=system
@@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.cpu.toL2Bus.slave[3]
@@ -431,18 +432,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
-response_latency=1000
+response_latency=2
size=131072
subblock_size=0
system=system
@@ -455,7 +456,7 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=X86LocalApic
-clock=1
+clock=500
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
@@ -464,6 +465,9 @@ int_master=system.membus.slave[2]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
@@ -472,31 +476,31 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
-clock=1
+clock=500
system=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
-hit_latency=1000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
-response_latency=1000
+response_latency=20
size=2097152
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
@@ -506,10 +510,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@@ -524,7 +528,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/x86/linux/hello
+executable=/projects/pd/randd/dist/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -546,15 +550,28 @@ master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_s
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clock=1
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
conf_table_reported=false
in_addr_map=true
-latency=30000
-latency_var=0
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
null=false
+page_policy=open
range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
zero=false
port=system.membus.master[0]
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
index 1bec04837..c8ef0214a 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
@@ -1,13 +1,11 @@
-Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 10 2012 21:50:34
-gem5 started Sep 10 2012 21:50:39
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Oct 30 2012 11:14:29
+gem5 started Oct 30 2012 16:15:47
+gem5 executing on u200540-lin
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 12607000 because target called exit()
+Exiting @ tick 15014000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
index 272509d41..e6a1ad3f3 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -1,53 +1,53 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000015 # Number of seconds simulated
-sim_ticks 15249000 # Number of ticks simulated
-final_tick 15249000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 15014000 # Number of ticks simulated
+final_tick 15014000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 41998 # Simulator instruction rate (inst/s)
-host_op_rate 76065 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 119014725 # Simulator tick rate (ticks/s)
-host_mem_usage 225728 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
+host_inst_rate 32657 # Simulator instruction rate (inst/s)
+host_op_rate 59148 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 91121721 # Simulator tick rate (ticks/s)
+host_mem_usage 223384 # Number of bytes of host memory used
+host_seconds 0.16 # Real time elapsed on the host
sim_insts 5380 # Number of instructions simulated
sim_ops 9745 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9280 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28800 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 145 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 450 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1280083940 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 608564496 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1888648436 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1280083940 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1280083940 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1280083940 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 608564496 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1888648436 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 451 # Total number of read requests seen
+system.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28736 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 19392 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 19392 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 303 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 449 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1291594512 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 622352471 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1913946983 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1291594512 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1291594512 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1291594512 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 622352471 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1913946983 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 450 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 451 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 28800 # Total number of bytes read from memory
+system.physmem.cpureqs 450 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 28736 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 28800 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 28736 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 40 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 41 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 20 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 55 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 23 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 52 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 23 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 16 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 17 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 14 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 35 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 40 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 29 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 39 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 12 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 34 # Track reads on a per bank basis
@@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 15226500 # Total gap between requests
+system.physmem.totGap 14992500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 451 # Categorize read packet sizes
+system.physmem.readPktSize::6 450 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@@ -99,8 +99,8 @@ system.physmem.neitherpktsize::6 0 # ca
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
system.physmem.rdQLenPdf::0 230 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 155 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 56 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
@@ -164,265 +164,265 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 1663951 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 11993951 # Sum of mem lat for all requests
-system.physmem.totBusLat 1804000 # Total cycles spent in databus access
-system.physmem.totBankLat 8526000 # Total cycles spent in bank access
-system.physmem.avgQLat 3689.47 # Average queueing delay per request
-system.physmem.avgBankLat 18904.66 # Average bank access latency per request
+system.physmem.totQLat 1656450 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 12024450 # Sum of mem lat for all requests
+system.physmem.totBusLat 1800000 # Total cycles spent in databus access
+system.physmem.totBankLat 8568000 # Total cycles spent in bank access
+system.physmem.avgQLat 3681.00 # Average queueing delay per request
+system.physmem.avgBankLat 19040.00 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 26594.13 # Average memory access latency
-system.physmem.avgRdBW 1888.65 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 26721.00 # Average memory access latency
+system.physmem.avgRdBW 1913.95 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1888.65 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1913.95 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 11.80 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.79 # Average read queue length over time
+system.physmem.busUtil 11.96 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.80 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 354 # Number of row buffer hits during reads
+system.physmem.readRowHits 352 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 78.49 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 78.22 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 33761.64 # Average gap between requests
+system.physmem.avgGap 33316.67 # Average gap between requests
system.cpu.workload.num_syscalls 11 # Number of system calls
-system.cpu.numCycles 30499 # number of cpu cycles simulated
+system.cpu.numCycles 30029 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 3124 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 3124 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 575 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 2554 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 779 # Number of BTB hits
+system.cpu.BPredUnit.lookups 3018 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 3018 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 546 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 2500 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 796 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 9097 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 15002 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 3124 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 779 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 4073 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 2573 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 3671 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 217 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 1972 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 311 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 19065 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.398846 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.899430 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 8962 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 14512 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 3018 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 796 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 3937 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 2417 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 3663 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 144 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 1880 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 18583 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.378572 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.879282 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 15096 79.18% 79.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 179 0.94% 80.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 149 0.78% 80.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 207 1.09% 81.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 179 0.94% 82.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 177 0.93% 83.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 231 1.21% 85.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 192 1.01% 86.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 2655 13.93% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 14745 79.35% 79.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 189 1.02% 80.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 157 0.84% 81.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 193 1.04% 82.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 162 0.87% 83.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 175 0.94% 84.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 261 1.40% 85.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 161 0.87% 86.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 2540 13.67% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 19065 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.102430 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.491885 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 9663 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 3644 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 3665 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 140 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1953 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 25430 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 1953 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 10013 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 2382 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 508 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 3439 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 770 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 23869 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 27 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 648 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 26126 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 57405 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 57389 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 18583 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.100503 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.483266 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 9455 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 3616 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 3547 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1830 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 24449 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 1830 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 9798 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 2386 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 485 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 3325 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 759 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 22967 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 39 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 640 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 25104 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 55188 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 55172 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 11060 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 15066 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 14044 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 31 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 31 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 2094 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2405 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1772 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 21302 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts 2021 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2205 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1755 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 20454 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 17998 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 209 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 10762 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 14777 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 17349 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 213 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 9974 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 13873 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 19065 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.944034 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.806602 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 18583 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.933595 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.794406 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 13533 70.98% 70.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1394 7.31% 78.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 1058 5.55% 83.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 719 3.77% 87.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 757 3.97% 91.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 676 3.55% 95.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 613 3.22% 98.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 275 1.44% 99.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 40 0.21% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 13202 71.04% 71.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1386 7.46% 78.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 1042 5.61% 84.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 691 3.72% 87.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 742 3.99% 91.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 623 3.35% 95.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 598 3.22% 98.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 257 1.38% 99.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 42 0.23% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 19065 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 18583 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 132 74.58% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 74.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 23 12.99% 87.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 22 12.43% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 138 77.53% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 19 10.67% 88.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 21 11.80% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 14399 80.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.03% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2084 11.58% 91.60% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1511 8.40% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 5 0.03% 0.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 13962 80.48% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 1900 10.95% 91.46% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1482 8.54% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 17998 # Type of FU issued
-system.cpu.iq.rate 0.590118 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 177 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.009834 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 55439 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 32107 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 16514 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 17349 # Type of FU issued
+system.cpu.iq.rate 0.577742 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 178 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.010260 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 53664 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 30472 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 16003 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 18167 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 17518 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 180 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 157 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1353 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 24 # Number of memory responses ignored because the instruction is squashed
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system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
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+system.cpu.iew.lsq.thread0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1953 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1731 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 30 # Number of cycles IEW is unblocking
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-system.cpu.iew.iewDispSquashedInsts 34 # Number of squashed instructions skipped by dispatch
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system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
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-system.cpu.iew.predictedNotTakenIncorrect 652 # Number of branches that were predicted not taken incorrectly
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-system.cpu.commit.committed_per_cycle::8 203 1.19% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committedInsts 5380 # Number of instructions committed
system.cpu.commit.committedOps 9745 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -433,283 +433,179 @@ system.cpu.commit.branches 1208 # Nu
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 9650 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.committedInsts 5380 # Number of Instructions Simulated
system.cpu.committedOps 9745 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 5380 # Number of Instructions Simulated
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-system.cpu.cpi_total 5.668959 # CPI: Total CPI of All Threads
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 83.281408 # Cycle average of tags in use
+system.cpu.dcache.total_refs 2284 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks.
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+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53532.894737 # average WriteReq mshr miss latency
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+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------