diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
| commit | df8df4fd0a95763cb0658cbe77615e7deac391d3 (patch) | |
| tree | 0c8776db2ef482a4f6e5db099133105f9af799d7 /tests/quick/se/00.hello/ref/x86 | |
| parent | b2342c5d9aea0b732f6d5a5b6c9c3961940ed8e7 (diff) | |
| download | gem5-df8df4fd0a95763cb0658cbe77615e7deac391d3.tar.xz | |
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
Diffstat (limited to 'tests/quick/se/00.hello/ref/x86')
| -rw-r--r-- | tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt | 393 | ||||
| -rw-r--r-- | tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt | 229 |
2 files changed, 316 insertions, 306 deletions
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 83799ecfd..3b4d7b677 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 19678000 # Number of ticks simulated final_tick 19678000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 30596 # Simulator instruction rate (inst/s) -host_op_rate 55428 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 111894824 # Simulator tick rate (ticks/s) -host_mem_usage 253080 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 46918 # Simulator instruction rate (inst/s) +host_op_rate 84992 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 171550123 # Simulator tick rate (ticks/s) +host_mem_usage 309548 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -220,55 +220,34 @@ system.physmem.readRowHitRate 74.10 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 47073.14 # Average gap between requests system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 11000 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15318250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 219240 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 446040 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 119625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 243375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1084200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1567800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 10796085 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 10703745 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 31500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 112500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 13267770 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 14090580 # Total energy per rank (pJ) -system.physmem.averagePower::0 837.810088 # Core power per rank (mW) -system.physmem.averagePower::1 889.767464 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 339 # Transaction distribution -system.membus.trans_dist::ReadResp 338 # Transaction distribution -system.membus.trans_dist::ReadExReq 78 # Transaction distribution -system.membus.trans_dist::ReadExResp 78 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 417 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 417 # Request fanout histogram -system.membus.reqLayer0.occupancy 505000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 3897000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 19.8 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 219240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 119625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1084200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 13267770 # Total energy per rank (pJ) +system.physmem_0.averagePower 837.810088 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15318250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 446040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 243375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1567800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10701180 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 112500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14088015 # Total energy per rank (pJ) +system.physmem_1.averagePower 889.816201 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 882750 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15230750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 3423 # Number of BP lookups system.cpu.branchPred.condPredicted 3423 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 535 # Number of conditional branches incorrect @@ -278,6 +257,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 33.962264 # BTB Hit Percentage system.cpu.branchPred.usedRAS 247 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 76 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 39357 # number of cpu cycles simulated @@ -572,36 +552,116 @@ system.cpu.cc_regfile_reads 8069 # nu system.cpu.cc_regfile_writes 5036 # number of cc regfile writes system.cpu.misc_regfile_reads 7491 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 78 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 78 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 552 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 283 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 835 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 418 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 462500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 234500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 82.331185 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.021277 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 82.331185 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020100 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020100 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5369 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5369 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1543 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1543 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 857 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 857 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2400 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2400 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2400 # number of overall hits +system.cpu.dcache.overall_hits::total 2400 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 136 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 136 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 78 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 78 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 214 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 214 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 214 # number of overall misses +system.cpu.dcache.overall_misses::total 214 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9815500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9815500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5771000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5771000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15586500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15586500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15586500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15586500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1679 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1679 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2614 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2614 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2614 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2614 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081001 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081001 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083422 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.083422 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.081867 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.081867 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.081867 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.081867 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72172.794118 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72172.794118 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73987.179487 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73987.179487 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72834.112150 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72834.112150 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 72 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 72 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 72 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 72 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 78 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 78 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5009500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5009500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5588000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5588000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10597500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10597500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10597500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10597500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083422 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083422 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.054323 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.054323 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78273.437500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78273.437500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71641.025641 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71641.025641 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 131.539722 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1800 # Total number of references to valid blocks. @@ -823,115 +883,60 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59334.545455 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61235.915493 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59982.014388 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.331185 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.021277 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.331185 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020100 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020100 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5369 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5369 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1543 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1543 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 857 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 857 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2400 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2400 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2400 # number of overall hits -system.cpu.dcache.overall_hits::total 2400 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 136 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 136 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 78 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 78 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 214 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 214 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 214 # number of overall misses -system.cpu.dcache.overall_misses::total 214 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9815500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9815500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5771000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5771000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15586500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15586500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15586500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15586500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1679 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1679 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2614 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2614 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2614 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2614 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081001 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.081001 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083422 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.083422 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.081867 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.081867 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.081867 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.081867 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72172.794118 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72172.794118 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73987.179487 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73987.179487 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72834.112150 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72834.112150 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.200000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 72 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 72 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 72 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 72 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 78 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 78 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5009500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5009500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5588000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5588000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10597500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10597500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10597500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10597500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.054323 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.054323 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78273.437500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78273.437500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71641.025641 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71641.025641 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 78 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 78 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 552 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 283 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 835 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 418 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 462500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 234500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 339 # Transaction distribution +system.membus.trans_dist::ReadResp 338 # Transaction distribution +system.membus.trans_dist::ReadExReq 78 # Transaction distribution +system.membus.trans_dist::ReadExResp 78 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 417 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 417 # Request fanout histogram +system.membus.reqLayer0.occupancy 505000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 3897000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 19.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index f27f9e229..6ad7b9146 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000107 # Nu sim_ticks 107237 # Number of ticks simulated final_tick 107237 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 14917 # Simulator instruction rate (inst/s) -host_op_rate 27022 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 297251 # Simulator tick rate (ticks/s) -host_mem_usage 452416 # Number of bytes of host memory used -host_seconds 0.36 # Real time elapsed on the host +host_inst_rate 59170 # Simulator instruction rate (inst/s) +host_op_rate 107175 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1178869 # Simulator tick rate (ticks/s) +host_mem_usage 466480 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -238,29 +238,97 @@ system.mem_ctrls.readRowHitRate 64.11 # Ro system.mem_ctrls.writeRowHitRate 90.98 # Row buffer hit rate for writes system.mem_ctrls.avgGap 38.96 # Average gap between requests system.mem_ctrls.pageHitRate 77.75 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 6647 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 3380 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 91465 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 695520 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 1270080 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 386400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 705600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 3219840 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 4605120 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 2623104 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 3784320 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 57894444 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 62913636 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 10102200 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 5699400 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 81532788 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 85589436 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 803.452847 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 843.428487 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 695520 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 386400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 3219840 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 2623104 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 57895812 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 10101000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 81532956 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 803.454502 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 16443 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 81669 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 1270080 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 705600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 4605120 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 3784320 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 62916372 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 5697000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 85589772 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 843.431798 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 9164 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 89065 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.apic_clk_domain.clock 16 # Clock period in ticks +system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.numCycles 107237 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 5381 # Number of instructions committed +system.cpu.committedOps 9748 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 209 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls +system.cpu.num_int_insts 9654 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 18335 # number of times the integer registers were read +system.cpu.num_int_register_writes 7527 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read +system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written +system.cpu.num_mem_refs 1988 # number of memory refs +system.cpu.num_load_insts 1053 # Number of load instructions +system.cpu.num_store_insts 935 # Number of store instructions +system.cpu.num_idle_cycles 0.999991 # Number of idle cycles +system.cpu.num_busy_cycles 107236.000009 # Number of busy cycles +system.cpu.not_idle_fraction 0.999991 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000009 # Percentage of idle cycles +system.cpu.Branches 1208 # Number of branches fetched +system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction +system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction +system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction +system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction +system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 9748 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message @@ -278,8 +346,8 @@ system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8852 system.ruby.latency_hist::mean 11.114437 -system.ruby.latency_hist::gmean 4.638311 -system.ruby.latency_hist::stdev 22.978637 +system.ruby.latency_hist::gmean 4.638310 +system.ruby.latency_hist::stdev 22.979355 system.ruby.latency_hist | 8594 97.09% 97.09% | 215 2.43% 99.51% | 29 0.33% 99.84% | 6 0.07% 99.91% | 6 0.07% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8852 system.ruby.hit_latency_hist::bucket_size 1 @@ -293,16 +361,15 @@ system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1377 system.ruby.miss_latency_hist::mean 55.163399 -system.ruby.miss_latency_hist::gmean 49.389613 -system.ruby.miss_latency_hist::stdev 33.121212 +system.ruby.miss_latency_hist::gmean 49.389540 +system.ruby.miss_latency_hist::stdev 33.124416 system.ruby.miss_latency_hist | 1119 81.26% 81.26% | 215 15.61% 96.88% | 29 2.11% 98.98% | 6 0.44% 99.42% | 6 0.44% 99.85% | 2 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1377 system.ruby.Directory.incomplete_times 1376 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 6.411034 system.ruby.network.routers0.msg_count.Control::2 1377 system.ruby.network.routers0.msg_count.Data::2 1373 @@ -338,68 +405,6 @@ system.ruby.network.msg_byte.Control 33048 system.ruby.network.msg_byte.Data 296568 system.ruby.network.msg_byte.Response_Data 297432 system.ruby.network.msg_byte.Writeback_Control 32952 -system.cpu.apic_clk_domain.clock 16 # Clock period in ticks -system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 107237 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5381 # Number of instructions committed -system.cpu.committedOps 9748 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 209 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls -system.cpu.num_int_insts 9654 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 18335 # number of times the integer registers were read -system.cpu.num_int_register_writes 7527 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read -system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written -system.cpu.num_mem_refs 1988 # number of memory refs -system.cpu.num_load_insts 1053 # Number of load instructions -system.cpu.num_store_insts 935 # Number of store instructions -system.cpu.num_idle_cycles 0.999991 # Number of idle cycles -system.cpu.num_busy_cycles 107236.000009 # Number of busy cycles -system.cpu.not_idle_fraction 0.999991 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000009 # Percentage of idle cycles -system.cpu.Branches 1208 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction -system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction -system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction -system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 9748 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 6.418494 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373 @@ -490,8 +495,8 @@ system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6864 system.ruby.IFETCH.latency_hist::mean 8.263112 -system.ruby.IFETCH.latency_hist::gmean 3.900454 -system.ruby.IFETCH.latency_hist::stdev 20.208626 +system.ruby.IFETCH.latency_hist::gmean 3.900453 +system.ruby.IFETCH.latency_hist::stdev 20.209679 system.ruby.IFETCH.latency_hist | 6731 98.06% 98.06% | 102 1.49% 99.55% | 22 0.32% 99.87% | 3 0.04% 99.91% | 5 0.07% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6864 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 @@ -505,8 +510,8 @@ system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 623 system.ruby.IFETCH.miss_latency_hist::mean 60.987159 -system.ruby.IFETCH.miss_latency_hist::gmean 54.083768 -system.ruby.IFETCH.miss_latency_hist::stdev 37.997755 +system.ruby.IFETCH.miss_latency_hist::gmean 54.083593 +system.ruby.IFETCH.miss_latency_hist::stdev 38.003932 system.ruby.IFETCH.miss_latency_hist | 490 78.65% 78.65% | 102 16.37% 95.02% | 22 3.53% 98.56% | 3 0.48% 99.04% | 5 0.80% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 623 system.ruby.RMW_Read.latency_hist::bucket_size 4 @@ -536,8 +541,8 @@ system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1377 system.ruby.Directory.miss_mach_latency_hist::mean 55.163399 -system.ruby.Directory.miss_mach_latency_hist::gmean 49.389613 -system.ruby.Directory.miss_mach_latency_hist::stdev 33.121212 +system.ruby.Directory.miss_mach_latency_hist::gmean 49.389540 +system.ruby.Directory.miss_mach_latency_hist::stdev 33.124416 system.ruby.Directory.miss_mach_latency_hist | 1119 81.26% 81.26% | 215 15.61% 96.88% | 29 2.11% 98.98% | 6 0.44% 99.42% | 6 0.44% 99.85% | 2 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1377 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 @@ -586,8 +591,8 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 623 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 60.987159 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 54.083768 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 37.997755 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 54.083593 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 38.003932 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 490 78.65% 78.65% | 102 16.37% 95.02% | 22 3.53% 98.56% | 3 0.48% 99.04% | 5 0.80% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 623 system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::bucket_size 4 @@ -598,6 +603,14 @@ system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::gmean 34.000000 system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::stdev nan system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::total 1 +system.ruby.Directory_Controller.GETX 1377 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 1373 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1377 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 1373 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 1377 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 1373 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 1377 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 1373 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1045 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 6864 0.00% 0.00% system.ruby.L1Cache_Controller.Store 943 0.00% 0.00% @@ -614,13 +627,5 @@ system.ruby.L1Cache_Controller.M.Replacement 1373 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 1373 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data 1122 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Data 255 0.00% 0.00% -system.ruby.Directory_Controller.GETX 1377 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 1373 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1377 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 1373 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 1377 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 1373 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 1377 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 1373 0.00% 0.00% ---------- End Simulation Statistics ---------- |