diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-11-01 11:56:34 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-11-01 11:56:34 -0400 |
| commit | ccfdc533b9d679f1596d43d647a093885d5e74ab (patch) | |
| tree | 4c785a5e7a7e2d7244fbdbb0a316405898f99e75 /tests/quick/se/00.hello/ref/x86 | |
| parent | 460cc77d6db46eef34b14a458816084bf6097b32 (diff) | |
| download | gem5-ccfdc533b9d679f1596d43d647a093885d5e74ab.tar.xz | |
stats: Bump stats to match DRAM controller changes
This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.
Diffstat (limited to 'tests/quick/se/00.hello/ref/x86')
| -rw-r--r-- | tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt | 1211 |
1 files changed, 609 insertions, 602 deletions
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 45776fad9..b42a03bbb 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,95 +1,97 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19639500 # Number of ticks simulated -final_tick 19639500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19970500 # Number of ticks simulated +final_tick 19970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 27608 # Simulator instruction rate (inst/s) -host_op_rate 50013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 100764572 # Simulator tick rate (ticks/s) -host_mem_usage 247304 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 37809 # Simulator instruction rate (inst/s) +host_op_rate 68492 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 140319695 # Simulator tick rate (ticks/s) +host_mem_usage 243588 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory -system.physmem.bytes_read::total 26624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17536 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 274 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory -system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 892894422 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 462740905 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1355635327 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 892894422 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 892894422 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 892894422 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 462740905 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1355635327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 417 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 417 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 26624 # Total number of bytes read from memory -system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 26624 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 20 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 73 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 63 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 2 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 19591000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 417 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see +system.physmem.bytes_read::cpu.inst 17472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory +system.physmem.bytes_read::total 26496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17472 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 273 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory +system.physmem.num_reads::total 414 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 874890463 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 451866503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1326756967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 874890463 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 874890463 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 874890463 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 451866503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1326756967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 415 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 415 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26560 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26560 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 33 # Per bank write bursts +system.physmem.perBankRdBursts::1 1 # Per bank write bursts +system.physmem.perBankRdBursts::2 5 # Per bank write bursts +system.physmem.perBankRdBursts::3 8 # Per bank write bursts +system.physmem.perBankRdBursts::4 50 # Per bank write bursts +system.physmem.perBankRdBursts::5 44 # Per bank write bursts +system.physmem.perBankRdBursts::6 20 # Per bank write bursts +system.physmem.perBankRdBursts::7 36 # Per bank write bursts +system.physmem.perBankRdBursts::8 23 # Per bank write bursts +system.physmem.perBankRdBursts::9 73 # Per bank write bursts +system.physmem.perBankRdBursts::10 63 # Per bank write bursts +system.physmem.perBankRdBursts::11 17 # Per bank write bursts +system.physmem.perBankRdBursts::12 2 # Per bank write bursts +system.physmem.perBankRdBursts::13 17 # Per bank write bursts +system.physmem.perBankRdBursts::14 6 # Per bank write bursts +system.physmem.perBankRdBursts::15 17 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 19922000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 415 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 250 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -150,300 +152,305 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 88 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 216 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.605669 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 322.610045 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 42 47.73% 47.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 13 14.77% 62.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 12 13.64% 76.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 4 4.55% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 6 6.82% 87.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 3 3.41% 90.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1 1.14% 92.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 1 1.14% 93.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1 1.14% 94.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1 1.14% 95.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 2 2.27% 97.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 1 1.14% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 1 1.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 88 # Bytes accessed per row activation -system.physmem.totQLat 1395750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11125750 # Sum of mem lat for all requests -system.physmem.totBusLat 2085000 # Total cycles spent in databus access -system.physmem.totBankLat 7645000 # Total cycles spent in bank access -system.physmem.avgQLat 3347.12 # Average queueing delay per request -system.physmem.avgBankLat 18333.33 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26680.46 # Average memory access latency -system.physmem.avgRdBW 1355.64 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1355.64 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 10.59 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.57 # Average read queue length over time -system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 329 # Number of row buffer hits during reads +system.physmem.bytesPerActivate::samples 103 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 226.174757 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 137.685606 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 319.474459 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 47 45.63% 45.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 17 16.50% 62.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 14 13.59% 75.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 5 4.85% 80.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 5 4.85% 85.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3 2.91% 88.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 4 3.88% 92.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 1.94% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1 0.97% 95.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 2 1.94% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 0.97% 98.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 1 0.97% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 1 0.97% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation +system.physmem.totQLat 2039250 # Total ticks spent queuing +system.physmem.totMemAccLat 11731750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2075000 # Total ticks spent in databus transfers +system.physmem.totBankLat 7617500 # Total ticks spent accessing banks +system.physmem.avgQLat 4913.86 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 18355.42 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 28269.28 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1329.96 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1329.96 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 10.39 # Data bus utilization in percentage +system.physmem.busUtilRead 10.39 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.59 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 312 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.90 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.18 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 46980.82 # Average gap between requests -system.membus.throughput 1355635327 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 340 # Transaction distribution -system.membus.trans_dist::ReadResp 339 # Transaction distribution +system.physmem.avgGap 48004.82 # Average gap between requests +system.physmem.pageHitRate 75.18 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 1326756967 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 338 # Transaction distribution +system.membus.trans_dist::ReadResp 337 # Transaction distribution system.membus.trans_dist::ReadExReq 77 # Transaction distribution system.membus.trans_dist::ReadExResp 77 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 26624 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 829 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 829 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 829 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26496 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26496 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 26496 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 26496 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 505500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 3891500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 19.8 # Layer utilization (%) -system.cpu.branchPred.lookups 3060 # Number of BP lookups -system.cpu.branchPred.condPredicted 3060 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 546 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2257 # Number of BTB lookups -system.cpu.branchPred.BTBHits 719 # Number of BTB hits +system.membus.reqLayer0.occupancy 500500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 3871500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 19.4 # Layer utilization (%) +system.cpu.branchPred.lookups 3084 # Number of BP lookups +system.cpu.branchPred.condPredicted 3084 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 542 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2283 # Number of BTB lookups +system.cpu.branchPred.BTBHits 726 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 31.856447 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 208 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 31.800263 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 207 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 39280 # number of cpu cycles simulated +system.cpu.numCycles 39942 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 10420 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14154 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3060 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 927 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3932 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2487 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5289 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 384 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1977 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 21952 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.145317 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.661061 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 10287 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14134 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3084 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 933 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3940 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2474 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5300 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 58 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 392 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 1980 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 21845 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.153353 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.669079 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 18121 82.55% 82.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 212 0.97% 83.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 149 0.68% 84.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 217 0.99% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 180 0.82% 86.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 202 0.92% 86.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 278 1.27% 88.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 161 0.73% 88.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2432 11.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18006 82.43% 82.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 216 0.99% 83.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 142 0.65% 84.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 224 1.03% 85.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 181 0.83% 85.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 200 0.92% 86.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 275 1.26% 88.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 159 0.73% 88.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2442 11.18% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 21952 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.077902 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.360336 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11197 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5173 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3579 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 137 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1866 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 24141 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1866 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 11552 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3842 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 569 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3343 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 780 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22717 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 35 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 666 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 25267 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 55251 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 31469 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 21845 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.077212 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.353863 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11079 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5195 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3583 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 131 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1857 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24173 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1857 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 11444 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3834 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 603 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3331 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 776 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 22661 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 32 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 663 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 25256 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 55040 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 31380 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14204 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 14193 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2015 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2290 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1582 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 2047 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2285 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1565 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20306 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17094 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 292 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9804 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14093 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 21952 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.778699 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.655311 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 20236 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 17027 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 290 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9729 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13960 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 21845 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.779446 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.654421 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16455 74.96% 74.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1544 7.03% 81.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1078 4.91% 86.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 728 3.32% 90.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 707 3.22% 93.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 584 2.66% 96.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 572 2.61% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 242 1.10% 99.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16359 74.89% 74.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1539 7.05% 81.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1092 5.00% 86.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 724 3.31% 90.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 698 3.20% 93.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 576 2.64% 96.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 581 2.66% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 234 1.07% 99.81% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 42 0.19% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 21952 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 21845 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 143 77.72% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 26 14.13% 91.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 15 8.15% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 140 77.35% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 26 14.36% 91.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 15 8.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13719 80.26% 80.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1979 11.58% 91.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1382 8.08% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13667 80.27% 80.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1973 11.59% 91.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1373 8.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17094 # Type of FU issued -system.cpu.iq.rate 0.435183 # Inst issue rate -system.cpu.iq.fu_busy_cnt 184 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010764 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 56608 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 30145 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 15699 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17027 # Type of FU issued +system.cpu.iq.rate 0.426293 # Inst issue rate +system.cpu.iq.fu_busy_cnt 181 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010630 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 56362 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 29998 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 15642 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 17271 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17201 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 170 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 168 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1237 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1232 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 647 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 630 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1866 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3033 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1857 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3034 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20334 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 50 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2290 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1582 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 20262 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 39 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2285 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1565 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 113 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 578 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 691 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16182 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1848 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 912 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 116 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 570 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 686 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16124 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1854 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 903 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3125 # number of memory reference insts executed -system.cpu.iew.exec_branches 1615 # Number of branches executed -system.cpu.iew.exec_stores 1277 # Number of stores executed -system.cpu.iew.exec_rate 0.411965 # Inst execution rate -system.cpu.iew.wb_sent 15923 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 15703 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10139 # num instructions producing a value -system.cpu.iew.wb_consumers 15623 # num instructions consuming a value +system.cpu.iew.exec_refs 3127 # number of memory reference insts executed +system.cpu.iew.exec_branches 1623 # Number of branches executed +system.cpu.iew.exec_stores 1273 # Number of stores executed +system.cpu.iew.exec_rate 0.403685 # Inst execution rate +system.cpu.iew.wb_sent 15865 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 15646 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10128 # num instructions producing a value +system.cpu.iew.wb_consumers 15579 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.399771 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.648979 # average fanout of values written-back +system.cpu.iew.wb_rate 0.391718 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.650106 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10598 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10526 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 599 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 20086 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.485263 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.340827 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 593 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 19988 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.487643 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.344274 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16512 82.21% 82.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1365 6.80% 89.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 596 2.97% 91.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 708 3.52% 95.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 362 1.80% 97.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 137 0.68% 97.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 121 0.60% 98.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 73 0.36% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16420 82.15% 82.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1360 6.80% 88.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 589 2.95% 91.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 713 3.57% 95.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 364 1.82% 97.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 136 0.68% 97.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 120 0.60% 98.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 74 0.37% 98.94% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 212 1.06% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 20086 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 19988 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -456,138 +463,138 @@ system.cpu.commit.int_insts 9653 # Nu system.cpu.commit.function_calls 106 # Number of function calls committed. system.cpu.commit.bw_lim_events 212 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 40219 # The number of ROB reads -system.cpu.rob.rob_writes 42582 # The number of ROB writes -system.cpu.timesIdled 167 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17328 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 40049 # The number of ROB reads +system.cpu.rob.rob_writes 42426 # The number of ROB writes +system.cpu.timesIdled 166 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18097 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5380 # Number of Instructions Simulated -system.cpu.cpi 7.301115 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.301115 # CPI: Total CPI of All Threads -system.cpu.ipc 0.136965 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.136965 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 20780 # number of integer regfile reads -system.cpu.int_regfile_writes 12385 # number of integer regfile writes +system.cpu.cpi 7.424164 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.424164 # CPI: Total CPI of All Threads +system.cpu.ipc 0.134695 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.134695 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 20727 # number of integer regfile reads +system.cpu.int_regfile_writes 12358 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.cc_regfile_reads 8044 # number of cc regfile reads -system.cpu.cc_regfile_writes 4852 # number of cc regfile writes -system.cpu.misc_regfile_reads 7122 # number of misc regfile reads +system.cpu.cc_regfile_reads 8004 # number of cc regfile reads +system.cpu.cc_regfile_writes 4850 # number of cc regfile writes +system.cpu.misc_regfile_reads 7135 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1362152804 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 342 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 341 # Transaction distribution +system.cpu.toL2Bus.throughput 1333166420 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 550 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 837 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 548 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 833 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 26624 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 209500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 463250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 239750 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 208500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 458500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 236000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 130.740950 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1608 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 275 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.847273 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 130.946729 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1609 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 274 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.872263 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 130.740950 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063838 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063838 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1608 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1608 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1608 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1608 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1608 # number of overall hits -system.cpu.icache.overall_hits::total 1608 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 369 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 369 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 369 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses -system.cpu.icache.overall_misses::total 369 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24439500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24439500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24439500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24439500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24439500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24439500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1977 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1977 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1977 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1977 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1977 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1977 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186646 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.186646 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.186646 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.186646 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.186646 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.186646 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66231.707317 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66231.707317 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66231.707317 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66231.707317 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66231.707317 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66231.707317 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 70 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 130.946729 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.063939 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063939 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1609 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1609 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1609 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1609 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1609 # number of overall hits +system.cpu.icache.overall_hits::total 1609 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 371 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 371 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 371 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 371 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 371 # number of overall misses +system.cpu.icache.overall_misses::total 371 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25087750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25087750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25087750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25087750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25087750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25087750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1980 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1980 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24590500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.984848 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994118 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996364 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993056 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.995227 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996364 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993056 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61298.951049 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57767.386091 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993007 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995204 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993007 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995204 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58342.490842 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64700 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59565.088757 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57889.610390 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57889.610390 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58342.490842 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61007.042254 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59254.216867 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58342.490842 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61007.042254 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59254.216867 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # 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average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74324.675325 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73014.285714 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73014.285714 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73014.285714 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73014.285714 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 163 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.082090 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.082090 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.082090 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.082090 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71272.727273 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71272.727273 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73714.285714 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73714.285714 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72172.248804 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72172.248804 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72172.248804 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72172.248804 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 183 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.750000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -776,38 +783,38 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 66 system.cpu.dcache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 66 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 67 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 67 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 66 # 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number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5494000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5494000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10573000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10573000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10573000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10573000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040968 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040968 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.056448 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.056448 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76891.791045 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76891.791045 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71922.077922 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71922.077922 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74234.375000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74234.375000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74234.375000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74234.375000 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056167 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.056167 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056167 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.056167 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76954.545455 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76954.545455 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71350.649351 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71350.649351 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73937.062937 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73937.062937 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73937.062937 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73937.062937 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |