stats: Update stats to reflect cache changes

Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.

2 files changed, 10 insertions, 28 deletions

diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
index 9accffb70..3c1544f1d 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000021                       # Nu
 sim_ticks                                    21273500                       # Number of ticks simulated
 final_tick                                   21273500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  39176                       # Simulator instruction rate (inst/s)
-host_op_rate                                    70969                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              151562567                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 245924                       # Number of bytes of host memory used
-host_seconds                                     0.14                       # Real time elapsed on the host
+host_inst_rate                                  70008                       # Simulator instruction rate (inst/s)
+host_op_rate                                   126817                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              276755373                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 271684                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        5380                       # Number of instructions simulated
 sim_ops                                          9747                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -625,8 +625,6 @@ system.cpu.dcache.blocked::no_mshrs                 3                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs    40.666667                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           51                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           51                       # number of ReadReq MSHR hits
 system.cpu.dcache.demand_mshr_hits::cpu.data           51                       # number of demand (read+write) MSHR hits
@@ -665,7 +663,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83525.179856
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 83525.179856                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83525.179856                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 83525.179856                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
 system.cpu.icache.tags.tagsinuse           130.801873                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                1651                       # Total number of references to valid blocks.
@@ -723,8 +720,6 @@ system.cpu.icache.blocked::no_mshrs                 3                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs    47.333333                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst          107                       # number of ReadReq MSHR hits
 system.cpu.icache.ReadReq_mshr_hits::total          107                       # number of ReadReq MSHR hits
 system.cpu.icache.demand_mshr_hits::cpu.inst          107                       # number of demand (read+write) MSHR hits
@@ -755,7 +750,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78663.669065
 system.cpu.icache.demand_avg_mshr_miss_latency::total 78663.669065                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78663.669065                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 78663.669065                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse          163.058861                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
@@ -845,8 +839,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           75                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           75                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          277                       # number of ReadCleanReq MSHR misses
@@ -895,7 +887,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68941.105769
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67398.916968                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72014.388489                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68941.105769                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests          417                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests            1                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
index 79b38ccd2..b345a9c01 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000031                       # Nu
 sim_ticks                                    30886500                       # Number of ticks simulated
 final_tick                                   30886500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  79759                       # Simulator instruction rate (inst/s)
-host_op_rate                                   144442                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              457524996                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 247116                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                 235920                       # Simulator instruction rate (inst/s)
+host_op_rate                                   427054                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1352150005                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 266824                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        5381                       # Number of instructions simulated
 sim_ops                                          9748                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -161,8 +161,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           55                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           55                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           79                       # number of WriteReq MSHR misses
@@ -195,7 +193,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        61000
 system.cpu.dcache.demand_avg_mshr_miss_latency::total        61000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        61000                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        61000                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
 system.cpu.icache.tags.tagsinuse           105.267613                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs                6636                       # Total number of references to valid blocks.
@@ -253,8 +250,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          228                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          228                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          228                       # number of demand (read+write) MSHR misses
@@ -279,7 +274,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60791.666667
 system.cpu.icache.demand_avg_mshr_miss_latency::total 60791.666667                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60791.666667                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 60791.666667                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse          133.672095                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs                  1                       # Total number of references to valid blocks.
@@ -369,8 +363,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           79                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           79                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          227                       # number of ReadCleanReq MSHR misses
@@ -419,7 +411,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.385042
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49502.202643                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        49500                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.385042                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests          362                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests            1                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.