diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
| commit | 25e1b1c1f5f4e0ad3976c88998161700135f4aae (patch) | |
| tree | 36e668b99a36c3dfcfefc157d7bd6b102b8f8af6 /tests/quick/se/00.hello/ref | |
| parent | 7e711c98f8fcd949b9430bbf243d60348d0ef28b (diff) | |
| download | gem5-25e1b1c1f5f4e0ad3976c88998161700135f4aae.tar.xz | |
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Diffstat (limited to 'tests/quick/se/00.hello/ref')
25 files changed, 6240 insertions, 6066 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index 6eb08a8bc..b5554ceae 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000038 # Number of seconds simulated -sim_ticks 37930000 # Number of ticks simulated -final_tick 37930000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 37623000 # Number of ticks simulated +final_tick 37623000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 161486 # Simulator instruction rate (inst/s) -host_op_rate 161429 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 956403338 # Simulator tick rate (ticks/s) -host_mem_usage 294064 # Number of bytes of host memory used +host_inst_rate 152308 # Simulator instruction rate (inst/s) +host_op_rate 152258 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 894784408 # Simulator tick rate (ticks/s) +host_mem_usage 293572 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host sim_insts 6400 # Number of instructions simulated sim_ops 6400 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 23296 # Nu system.physmem.num_reads::cpu.inst 364 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory system.physmem.num_reads::total 533 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 614184023 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 285156868 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 899340891 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 614184023 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 614184023 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 614184023 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 285156868 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 899340891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 619195705 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 287483720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 906679425 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 619195705 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 619195705 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 619195705 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 287483720 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 906679425 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 533 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 37824500 # Total gap between requests +system.physmem.totGap 37518500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 442 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 443 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 85 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -187,32 +187,32 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 84 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 381.714286 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 247.680361 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.730884 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19 22.62% 22.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 20 23.81% 46.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 384 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 247.494057 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 333.812732 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 20 23.81% 23.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 22.62% 46.43% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 10 11.90% 58.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 11 13.10% 71.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 4.76% 76.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 3.57% 79.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 2.38% 82.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6 7.14% 89.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 10.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 2.38% 73.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 5 5.95% 79.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 3.57% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6 7.14% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8 9.52% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 84 # Bytes accessed per row activation -system.physmem.totQLat 3251500 # Total ticks spent queuing -system.physmem.totMemAccLat 13245250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3336750 # Total ticks spent queuing +system.physmem.totMemAccLat 13330500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6100.38 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6260.32 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24850.38 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 899.34 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25010.32 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 906.68 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 899.34 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 906.68 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.03 # Data bus utilization in percentage -system.physmem.busUtilRead 7.03 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.08 # Data bus utilization in percentage +system.physmem.busUtilRead 7.08 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,43 +220,43 @@ system.physmem.readRowHits 437 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 70965.29 # Average gap between requests +system.physmem.avgGap 70391.18 # Average gap between requests system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ) +system.physmem_0.actEnergy 226800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 123750 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 21404070 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25911645 # Total energy per rank (pJ) -system.physmem_0.averagePower 825.080242 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 372750 # Time in different power states +system.physmem_0.actBackEnergy 21178350 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 265500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25872240 # Total energy per rank (pJ) +system.physmem_0.averagePower 823.825505 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 435750 # Time in different power states system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 30362750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 30032750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 340200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 185625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1521000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 347760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 189750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1544400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 20293425 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1041750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 25416240 # Total energy per rank (pJ) -system.physmem_1.averagePower 809.305525 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1595750 # Time in different power states +system.physmem_1.actBackEnergy 20558475 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 809250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 25483875 # Total energy per rank (pJ) +system.physmem_1.averagePower 811.459163 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1209750 # Time in different power states system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 28783000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 29169000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1964 # Number of BP lookups -system.cpu.branchPred.condPredicted 1204 # Number of conditional branches predicted +system.cpu.branchPred.lookups 1965 # Number of BP lookups +system.cpu.branchPred.condPredicted 1205 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1555 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 1556 # Number of BTB lookups system.cpu.branchPred.BTBHits 382 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 24.565916 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 24.550129 # BTB Hit Percentage system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -276,10 +276,10 @@ system.cpu.dtb.data_hits 2255 # DT system.cpu.dtb.data_misses 14 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 2269 # DTB accesses -system.cpu.itb.fetch_hits 2638 # ITB hits +system.cpu.itb.fetch_hits 2639 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2655 # ITB accesses +system.cpu.itb.fetch_accesses 2656 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,26 +293,26 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 75860 # number of cpu cycles simulated +system.cpu.numCycles 75246 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6400 # Number of instructions committed system.cpu.committedOps 6400 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1116 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1115 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 11.853125 # CPI: cycles per instruction -system.cpu.ipc 0.084366 # IPC: instructions per cycle -system.cpu.tickCycles 12560 # Number of cycles that the object actually ticked -system.cpu.idleCycles 63300 # Total number of cycles that the object has spent stopped +system.cpu.cpi 11.757188 # CPI: cycles per instruction +system.cpu.ipc 0.085054 # IPC: instructions per cycle +system.cpu.tickCycles 12577 # Number of cycles that the object actually ticked +system.cpu.idleCycles 62669 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.899066 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1976 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 103.998872 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1975 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.692308 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.686391 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.899066 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025366 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025366 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.998872 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025390 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025390 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id @@ -321,28 +321,28 @@ system.cpu.dcache.tags.tag_accesses 4573 # Nu system.cpu.dcache.tags.data_accesses 4573 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 1235 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1235 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 741 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 741 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1976 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1976 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1976 # number of overall hits -system.cpu.dcache.overall_hits::total 1976 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1975 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1975 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1975 # number of overall hits +system.cpu.dcache.overall_hits::total 1975 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 102 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 124 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 124 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 226 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 226 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 226 # number of overall misses -system.cpu.dcache.overall_misses::total 226 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8144750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8144750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9233750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9233750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17378500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17378500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17378500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17378500 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 125 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 227 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 227 # number of overall misses +system.cpu.dcache.overall_misses::total 227 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8109500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8109500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9137500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9137500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17247000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17247000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17247000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17247000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1337 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1337 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -353,20 +353,20 @@ system.cpu.dcache.overall_accesses::cpu.data 2202 system.cpu.dcache.overall_accesses::total 2202 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076290 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.076290 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.143353 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.143353 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.102634 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.102634 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.102634 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.102634 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79850.490196 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 79850.490196 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74465.725806 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74465.725806 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 76896.017699 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 76896.017699 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 76896.017699 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 76896.017699 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.144509 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.103088 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.103088 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.103088 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.103088 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79504.901961 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 79504.901961 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73100 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73100 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75977.973568 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75977.973568 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 75977.973568 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 75977.973568 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -377,12 +377,12 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 51 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 51 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 57 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 57 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 57 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 58 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 58 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 96 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses @@ -391,14 +391,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 169 system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7564250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7564250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5364250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5364250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12928500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12928500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12928500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12928500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7616500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7616500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5372000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5372000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12988500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12988500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12988500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12988500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071803 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071803 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -407,66 +407,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076748 system.cpu.dcache.demand_mshr_miss_rate::total 0.076748 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076748 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.076748 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78794.270833 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78794.270833 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73482.876712 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73482.876712 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76500 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76500 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79338.541667 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79338.541667 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73589.041096 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73589.041096 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76855.029586 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76855.029586 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76855.029586 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76855.029586 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 175.739822 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2273 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 175.991805 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 2274 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.227397 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.230137 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 175.739822 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.085810 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.085810 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 175.991805 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.085933 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.085933 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 5641 # Number of tag accesses -system.cpu.icache.tags.data_accesses 5641 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 2273 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2273 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2273 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2273 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2273 # number of overall hits -system.cpu.icache.overall_hits::total 2273 # number of overall hits +system.cpu.icache.tags.tag_accesses 5643 # Number of tag accesses +system.cpu.icache.tags.data_accesses 5643 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 2274 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2274 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2274 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2274 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2274 # number of overall hits +system.cpu.icache.overall_hits::total 2274 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28333750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28333750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28333750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28333750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28333750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28333750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2638 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2638 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2638 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2638 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2638 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2638 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138362 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.138362 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.138362 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.138362 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.138362 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.138362 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77626.712329 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77626.712329 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77626.712329 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77626.712329 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77626.712329 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77626.712329 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28165000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28165000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28165000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28165000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28165000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28165000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2639 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2639 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2639 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2639 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2639 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2639 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138310 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.138310 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.138310 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.138310 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.138310 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.138310 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77164.383562 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77164.383562 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77164.383562 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77164.383562 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77164.383562 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77164.383562 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,103 +481,108 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365 system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27622750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27622750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27622750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27622750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27622750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27622750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138362 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138362 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138362 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.138362 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138362 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.138362 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75678.767123 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75678.767123 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75678.767123 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75678.767123 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75678.767123 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75678.767123 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27800000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27800000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27800000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27800000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27800000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27800000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138310 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.138310 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.138310 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76164.383562 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76164.383562 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76164.383562 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76164.383562 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76164.383562 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76164.383562 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 233.394654 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 233.662872 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.771828 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.622826 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005364 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001759 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007123 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 176.005347 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.657524 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005371 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001760 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007131 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014038 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4805 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4805 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 96 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 460 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 364 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 364 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 96 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 96 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 364 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 169 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 533 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 364 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses system.cpu.l2cache.overall_misses::total 533 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27246750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7466750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 34713500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5290250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5290250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27246750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12757000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 40003750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27246750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12757000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 40003750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 365 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 96 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5261500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5261500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27241500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 27241500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7471000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7471000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27241500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12732500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 39974000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27241500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12732500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 39974000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 365 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 365 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 96 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 96 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 365 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 169 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 534 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 365 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 169 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 534 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.997260 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997831 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.997260 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.997260 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.997260 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.998127 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997260 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74853.708791 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77778.645833 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75464.130435 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72469.178082 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72469.178082 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74853.708791 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75485.207101 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75053.939962 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74853.708791 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75485.207101 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75053.939962 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72075.342466 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72075.342466 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74839.285714 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74839.285714 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77822.916667 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77822.916667 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74839.285714 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75340.236686 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74998.123827 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74839.285714 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75340.236686 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74998.123827 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -586,55 +591,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 364 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 96 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 460 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 364 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 364 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 364 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 169 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 533 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22686750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6260250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28947000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4378250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4378250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22686750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10638500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 33325250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22686750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10638500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 33325250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4531500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4531500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23601500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23601500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6511000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6511000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23601500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11042500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 34644000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23601500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11042500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 34644000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.997260 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62326.236264 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65210.937500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62928.260870 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59976.027397 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59976.027397 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62326.236264 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62949.704142 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62523.921201 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62326.236264 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62949.704142 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62523.921201 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62075.342466 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62075.342466 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64839.285714 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64839.285714 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67822.916667 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67822.916667 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64839.285714 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65340.236686 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64998.123827 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64839.285714 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65340.236686 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64998.123827 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 365 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 96 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 1068 # Packet count per connected master and slave (bytes) @@ -655,14 +665,14 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 629250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 286000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.trans_dist::ReadReq 460 # Transaction distribution +system.cpu.toL2Bus.respLayer0.occupancy 547500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 253500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.membus.trans_dist::ReadResp 460 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 460 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes) @@ -678,9 +688,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 533 # Request fanout histogram -system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2833250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2833000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 7.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 4b8e35ff8..96f652b92 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 22074000 # Number of ticks simulated -final_tick 22074000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21947000 # Number of ticks simulated +final_tick 21947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 27311 # Simulator instruction rate (inst/s) -host_op_rate 27309 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 94600483 # Simulator tick rate (ticks/s) -host_mem_usage 225500 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host +host_inst_rate 95577 # Simulator instruction rate (inst/s) +host_op_rate 95558 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 329070081 # Simulator tick rate (ticks/s) +host_mem_usage 294868 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 20032 # Nu system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory system.physmem.num_reads::total 486 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 907492978 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 501585576 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1409078554 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 907492978 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 907492978 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 907492978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 501585576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1409078554 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 912744339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 504488085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1417232424 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 912744339 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 912744339 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 912744339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 504488085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1417232424 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 486 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 486 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21941500 # Total gap between requests +system.physmem.totGap 21815000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,8 +91,8 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 138 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 56 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -188,8 +188,8 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 81 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 332.641975 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 207.818416 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 321.662840 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 207.725130 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 321.981029 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 25 30.86% 30.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 18 22.22% 53.09% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 9 11.11% 64.20% # Bytes accessed per row activation @@ -199,19 +199,19 @@ system.physmem.bytesPerActivate::640-767 1 1.23% 83.95% # By system.physmem.bytesPerActivate::768-895 3 3.70% 87.65% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 12.35% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 81 # Bytes accessed per row activation -system.physmem.totQLat 4363750 # Total ticks spent queuing -system.physmem.totMemAccLat 13476250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 4379250 # Total ticks spent queuing +system.physmem.totMemAccLat 13491750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2430000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8978.91 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9010.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27728.91 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1409.08 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27760.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1417.23 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1409.08 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1417.23 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.01 # Data bus utilization in percentage -system.physmem.busUtilRead 11.01 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.07 # Data bus utilization in percentage +system.physmem.busUtilRead 11.07 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -219,7 +219,7 @@ system.physmem.readRowHits 390 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.25 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45147.12 # Average gap between requests +system.physmem.avgGap 44886.83 # Average gap between requests system.physmem.pageHitRate 80.25 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 219240 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 119625 # Energy for precharge commands per rank (pJ) @@ -230,55 +230,55 @@ system.physmem_0.actBackEnergy 10785825 # En system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 13833660 # Total energy per rank (pJ) system.physmem_0.averagePower 873.750829 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 118250 # Time in different power states +system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 325080 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 177375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1255800 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 1271400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10123200 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 619500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13518075 # Total energy per rank (pJ) -system.physmem_1.averagePower 853.818096 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 963500 # Time in different power states +system.physmem_1.actBackEnergy 10129185 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 614250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13534410 # Total energy per rank (pJ) +system.physmem_1.averagePower 854.849834 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 953500 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14362750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14372750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2808 # Number of BP lookups -system.cpu.branchPred.condPredicted 1660 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 479 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2112 # Number of BTB lookups -system.cpu.branchPred.BTBHits 676 # Number of BTB hits +system.cpu.branchPred.lookups 2810 # Number of BP lookups +system.cpu.branchPred.condPredicted 1662 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 478 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2116 # Number of BTB lookups +system.cpu.branchPred.BTBHits 679 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.007576 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 398 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 30 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 32.088847 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 396 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 29 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.read_hits 2105 # DTB read hits -system.cpu.dtb.read_misses 56 # DTB read misses +system.cpu.dtb.read_misses 55 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2161 # DTB read accesses +system.cpu.dtb.read_accesses 2160 # DTB read accesses system.cpu.dtb.write_hits 1074 # DTB write hits system.cpu.dtb.write_misses 30 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 1104 # DTB write accesses system.cpu.dtb.data_hits 3179 # DTB hits -system.cpu.dtb.data_misses 86 # DTB misses +system.cpu.dtb.data_misses 85 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3265 # DTB accesses -system.cpu.itb.fetch_hits 2195 # ITB hits +system.cpu.dtb.data_accesses 3264 # DTB accesses +system.cpu.itb.fetch_hits 2194 # ITB hits system.cpu.itb.fetch_misses 34 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2229 # ITB accesses +system.cpu.itb.fetch_accesses 2228 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -292,131 +292,131 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 44149 # number of cpu cycles simulated +system.cpu.numCycles 43895 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8603 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16272 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2808 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1074 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4302 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1040 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 8597 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16278 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2810 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1075 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4298 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1038 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 735 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2195 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 341 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14185 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.147127 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.556854 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 740 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2194 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14179 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.148036 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.557344 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11330 79.87% 79.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 287 2.02% 81.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 214 1.51% 83.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11320 79.84% 79.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 289 2.04% 81.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 216 1.52% 83.40% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 204 1.44% 84.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 242 1.71% 86.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 209 1.47% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 241 1.70% 89.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 178 1.25% 90.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1280 9.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 243 1.71% 86.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 208 1.47% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 242 1.71% 89.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 175 1.23% 90.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1282 9.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14185 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.063603 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.368570 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8626 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2504 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2413 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 199 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 443 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 14179 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.064016 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.370840 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8623 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2500 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2414 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 200 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 442 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 227 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14877 # Number of instructions handled by decode +system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14886 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 224 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 443 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8799 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1077 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 424 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2422 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1020 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14259 # Number of instructions processed by rename +system.cpu.rename.SquashCycles 442 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8796 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1074 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 427 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2425 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1015 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14276 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 15 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 32 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 922 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 10782 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17904 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17895 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 33 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 937 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 10794 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17927 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17918 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6212 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6224 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 32 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 534 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 538 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 2680 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1315 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12936 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 12940 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10742 # Number of instructions issued +system.cpu.iq.iqInstsIssued 10735 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6591 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3553 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 6595 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3561 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14185 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.757279 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.490412 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14179 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.757106 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.490778 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10181 71.77% 71.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1265 8.92% 80.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 910 6.42% 87.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 677 4.77% 91.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 530 3.74% 95.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 330 2.33% 97.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 213 1.50% 99.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 54 0.38% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 25 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10173 71.75% 71.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1278 9.01% 80.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 898 6.33% 87.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 679 4.79% 91.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 528 3.72% 95.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 333 2.35% 97.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 209 1.47% 99.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.39% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 26 0.18% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14185 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14179 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 29 19.86% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 74 50.68% 70.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 43 29.45% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 29 20.14% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 20.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 73 50.69% 70.83% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 42 29.17% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7248 67.47% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7243 67.47% 67.49% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.50% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.52% # Type of FU issued @@ -445,23 +445,23 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.52% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2358 21.95% 89.47% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1131 10.53% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2356 21.95% 89.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1131 10.54% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10742 # Type of FU issued -system.cpu.iq.rate 0.243312 # Inst issue rate -system.cpu.iq.fu_busy_cnt 146 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013592 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 35814 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19563 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9787 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10735 # Type of FU issued +system.cpu.iq.rate 0.244561 # Inst issue rate +system.cpu.iq.fu_busy_cnt 144 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013414 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 35792 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19571 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9784 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10875 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10866 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 70 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 71 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 1497 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed @@ -472,57 +472,57 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 65 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 443 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1035 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13050 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 442 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1033 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 13054 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 109 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2680 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1315 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 22 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 20 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 81 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 391 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 472 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10248 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2164 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 494 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 395 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 476 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 10242 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2163 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 493 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 86 # number of nop insts executed -system.cpu.iew.exec_refs 3270 # number of memory reference insts executed -system.cpu.iew.exec_branches 1599 # Number of branches executed +system.cpu.iew.exec_refs 3269 # number of memory reference insts executed +system.cpu.iew.exec_branches 1598 # Number of branches executed system.cpu.iew.exec_stores 1106 # Number of stores executed -system.cpu.iew.exec_rate 0.232123 # Inst execution rate -system.cpu.iew.wb_sent 9960 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9797 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5308 # num instructions producing a value -system.cpu.iew.wb_consumers 7306 # num instructions consuming a value +system.cpu.iew.exec_rate 0.233330 # Inst execution rate +system.cpu.iew.wb_sent 9957 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9794 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5300 # num instructions producing a value +system.cpu.iew.wb_consumers 7297 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.221908 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.726526 # average fanout of values written-back +system.cpu.iew.wb_rate 0.223123 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.726326 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6660 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6664 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 402 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12983 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.492105 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.404730 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 401 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.492295 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.405132 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10525 81.07% 81.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1166 8.98% 90.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 505 3.89% 93.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10520 81.06% 81.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1167 8.99% 90.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 504 3.88% 93.94% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 209 1.61% 95.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 137 1.06% 96.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 75 0.58% 97.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 136 1.05% 96.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 76 0.59% 97.18% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 89 0.69% 97.87% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 87 0.67% 98.54% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 190 1.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12983 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12978 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -569,101 +569,101 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 6389 # Class of committed instruction system.cpu.commit.bw_lim_events 190 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 25491 # The number of ROB reads -system.cpu.rob.rob_writes 27316 # The number of ROB writes -system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29964 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 25490 # The number of ROB reads +system.cpu.rob.rob_writes 27321 # The number of ROB writes +system.cpu.timesIdled 258 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29716 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.928594 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.928594 # CPI: Total CPI of All Threads -system.cpu.ipc 0.144329 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.144329 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13019 # number of integer regfile reads -system.cpu.int_regfile_writes 7461 # number of integer regfile writes +system.cpu.cpi 6.888732 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.888732 # CPI: Total CPI of All Threads +system.cpu.ipc 0.145165 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.145165 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13013 # number of integer regfile reads +system.cpu.int_regfile_writes 7460 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 107.596270 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2347 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 107.548347 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2343 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.566474 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.543353 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 107.596270 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026269 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026269 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 107.548347 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026257 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026257 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5893 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5893 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1838 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1838 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 509 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 509 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2347 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2347 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2347 # number of overall hits -system.cpu.dcache.overall_hits::total 2347 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 157 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 157 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 356 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 356 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 513 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 513 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 513 # number of overall misses -system.cpu.dcache.overall_misses::total 513 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12056250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12056250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24043225 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24043225 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 36099475 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 36099475 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 36099475 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 36099475 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1995 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1995 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 5891 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5891 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1835 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1835 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 508 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 508 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2343 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2343 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2343 # number of overall hits +system.cpu.dcache.overall_hits::total 2343 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 159 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 159 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 357 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 357 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 516 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 516 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 516 # number of overall misses +system.cpu.dcache.overall_misses::total 516 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11993500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11993500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24175975 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24175975 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36169475 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36169475 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36169475 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36169475 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1994 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1994 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2860 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2860 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2860 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2860 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078697 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.078697 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.179371 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.179371 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.179371 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.179371 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76791.401274 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 76791.401274 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67537.148876 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 67537.148876 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70369.346979 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70369.346979 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 70369.346979 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 70369.346979 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2245 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2859 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2859 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2859 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2859 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079739 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.079739 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412717 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.412717 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.180483 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.180483 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.180483 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.180483 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75430.817610 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75430.817610 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67719.817927 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67719.817927 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70095.881783 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70095.881783 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 70095.881783 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70095.881783 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2284 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 38 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 41 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.078947 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.707317 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 340 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 340 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 340 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 340 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 285 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 285 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 343 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 343 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 343 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 343 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses @@ -672,82 +672,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 173 system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8557250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8557250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5645250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5645250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14202500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14202500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14202500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14202500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050627 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050627 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8588000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8588000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5911000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5911000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14499000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14499000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14499000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14499000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050652 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050652 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.060490 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.060490 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.060490 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.060490 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84725.247525 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84725.247525 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78406.250000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78406.250000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82095.375723 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 82095.375723 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82095.375723 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 82095.375723 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.060511 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.060511 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.060511 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.060511 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85029.702970 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85029.702970 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82097.222222 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82097.222222 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83809.248555 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 83809.248555 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83809.248555 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 83809.248555 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 158.400693 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1716 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 158.228991 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1714 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.464968 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.458599 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 158.400693 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077344 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077344 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 158.228991 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077260 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077260 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4704 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4704 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1716 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1716 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1716 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1716 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1716 # number of overall hits -system.cpu.icache.overall_hits::total 1716 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 479 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 479 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 479 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 479 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 479 # number of overall misses -system.cpu.icache.overall_misses::total 479 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34067500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34067500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34067500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34067500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34067500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34067500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2195 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2195 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2195 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2195 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2195 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2195 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.218223 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.218223 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.218223 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.218223 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.218223 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.218223 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71122.129436 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71122.129436 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71122.129436 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71122.129436 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71122.129436 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71122.129436 # average overall miss latency +system.cpu.icache.tags.tag_accesses 4702 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4702 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1714 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1714 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1714 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1714 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1714 # number of overall hits +system.cpu.icache.overall_hits::total 1714 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 480 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 480 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 480 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 480 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 480 # number of overall misses +system.cpu.icache.overall_misses::total 480 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 33574500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 33574500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 33574500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 33574500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 33574500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 33574500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2194 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2194 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2194 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2194 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2194 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2194 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.218778 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.218778 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.218778 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.218778 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.218778 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.218778 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69946.875000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69946.875000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69946.875000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69946.875000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69946.875000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69946.875000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -756,115 +756,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 165 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 165 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 165 # number of overall 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of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 314 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24276250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24276250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24276250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24276250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24276250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24276250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143052 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143052 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143052 # mshr miss rate for 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system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64002.396166 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71170.792079 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65751.207729 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64920.138889 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64920.138889 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64002.396166 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68569.364162 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65628.086420 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64002.396166 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68569.364162 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65628.086420 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70555.555556 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70555.555556 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65575.079872 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65575.079872 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73450.495050 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73450.495050 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65575.079872 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72245.664740 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67949.588477 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65575.079872 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72245.664740 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67949.588477 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 415 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 314 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 101 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 974 # Packet count per connected master and slave (bytes) @@ -942,14 +952,14 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 487 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 243500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 535750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 285500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 414 # Transaction distribution +system.cpu.toL2Bus.respLayer0.occupancy 471000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) system.membus.trans_dist::ReadResp 414 # Transaction distribution system.membus.trans_dist::ReadExReq 72 # Transaction distribution system.membus.trans_dist::ReadExResp 72 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 414 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 972 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 972 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31104 # Cumulative packet size per connected master and slave (bytes) @@ -965,9 +975,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 486 # Request fanout histogram -system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 594500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 2581250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 2585500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt index aeda1c330..88733611d 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000139 # Number of seconds simulated -sim_ticks 138637 # Number of ticks simulated -final_tick 138637 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 138724 # Number of ticks simulated +final_tick 138724 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 45640 # Simulator instruction rate (inst/s) -host_op_rate 45635 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 990010 # Simulator tick rate (ticks/s) -host_mem_usage 451208 # Number of bytes of host memory used +host_inst_rate 45032 # Simulator instruction rate (inst/s) +host_op_rate 45028 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 977453 # Simulator tick rate (ticks/s) +host_mem_usage 451780 # Number of bytes of host memory used host_seconds 0.14 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated @@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1460 # system.mem_ctrls.num_reads::total 1460 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 277 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 277 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 673990349 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 673990349 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 127873511 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 127873511 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 801863860 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 801863860 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 673567660 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 673567660 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 127793316 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 127793316 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 801360976 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 801360976 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1460 # Number of read requests accepted system.mem_ctrls.writeReqs 277 # Number of write requests accepted system.mem_ctrls.readBursts 1460 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 277 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 74880 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 18560 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 6400 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 75008 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 18432 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 6464 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 93440 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 17728 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 290 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.servicedByWrQ 288 # Number of DRAM read bursts serviced by the write queue system.mem_ctrls.mergedWrBursts 155 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 102 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 61 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 90 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 90 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 103 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 22 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 105 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 21 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::7 4 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 84 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 87 # Per bank write bursts system.mem_ctrls.perBankRdBursts::11 75 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 26 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 396 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 394 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 67 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 48 # Per bank write bursts system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 29 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 30 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 6 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 5 # Per bank write bursts system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 19 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 16 # Per bank write bursts system.mem_ctrls.perBankWrBursts::14 43 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 138534 # Total gap between requests +system.mem_ctrls.totGap 138621 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 277 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 1170 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 1172 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -136,12 +136,12 @@ system.mem_ctrls.wrQLenPdf::12 1 # Wh system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 3 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 4 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::17 7 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::18 7 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::19 7 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::20 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 7 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::22 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::23 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::24 6 # What write queue length does an incoming req see @@ -184,86 +184,88 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 224 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 353.142857 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 223.489977 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 324.415911 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 59 26.34% 26.34% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 55 24.55% 50.89% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 31 13.84% 64.73% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 15 6.70% 71.43% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 13 5.80% 77.23% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 14 6.25% 83.48% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 7 3.12% 86.61% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 9 4.02% 90.62% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 21 9.38% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 224 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 233 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 343.622318 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 215.641138 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 323.027267 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 63 27.04% 27.04% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 61 26.18% 53.22% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 29 12.45% 65.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 14 6.01% 71.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 15 6.44% 78.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 14 6.01% 84.12% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 7 3.00% 87.12% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 7 3.00% 90.13% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 23 9.87% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 233 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 178 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 127.889331 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 115.157284 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 179.333333 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 129.319022 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 112.290100 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::16-31 1 16.67% 16.67% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::64-79 1 16.67% 33.33% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::192-207 2 33.33% 66.67% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::192-207 1 16.67% 50.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::208-223 1 16.67% 66.67% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::240-255 1 16.67% 83.33% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::336-351 1 16.67% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::320-335 1 16.67% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 6 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.666667 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.640671 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.032796 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 4 66.67% 66.67% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.833333 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.809662 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.983192 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 3 50.00% 50.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 1 16.67% 66.67% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::18 2 33.33% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 6 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 7999 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 30229 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 5850 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 6.84 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 8028 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 30296 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 5860 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 6.85 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 25.84 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 540.12 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 46.16 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 673.99 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 127.87 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 25.85 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 540.70 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 46.60 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 673.57 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 127.79 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 4.58 # Data bus utilization in percentage +system.mem_ctrls.busUtil 4.59 # Data bus utilization in percentage system.mem_ctrls.busUtilRead 4.22 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.36 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 23.33 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 948 # Number of row buffer hits during reads +system.mem_ctrls.avgWrQLen 22.86 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 943 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 92 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 81.03 # Row buffer hit rate for reads +system.mem_ctrls.readRowHitRate 80.46 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 75.41 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 79.75 # Average gap between requests -system.mem_ctrls.pageHitRate 80.50 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 559440 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 310800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 5828160 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 362880 # Energy for write commands per rank (pJ) +system.mem_ctrls.avgGap 79.80 # Average gap between requests +system.mem_ctrls.pageHitRate 79.98 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 604800 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 336000 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5840640 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 383616 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 8645520 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 75338496 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 13486800 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 104532096 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 788.195744 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 25869 # Time in different power states +system.mem_ctrls_0.actBackEnergy 75398688 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 13434000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 104643264 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 789.033976 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 25868 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 4420 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 106214 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 106302 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 1103760 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 613200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 8112000 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 673920 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.actEnergy 1118880 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 621600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 8087040 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 663552 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 8645520 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 89081424 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 1431600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 109661424 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 826.872042 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 1728 # Time in different power states +system.mem_ctrls_1.actBackEnergy 89353656 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 1192800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 109683048 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 827.035092 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1330 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 4420 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 126488 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 126886 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -299,7 +301,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 138637 # number of cpu cycles simulated +system.cpu.numCycles 138724 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6390 # Number of instructions committed @@ -318,7 +320,7 @@ system.cpu.num_mem_refs 2058 # nu system.cpu.num_load_insts 1190 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 138637 # Number of busy cycles +system.cpu.num_busy_cycles 138724 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched @@ -361,9 +363,9 @@ system.ruby.clk_domain.clock 1 # Cl system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 9645 # delay histogram for all message -system.ruby.delayHist::mean 0.162779 # delay histogram for all message -system.ruby.delayHist::stdev 1.010338 # delay histogram for all message -system.ruby.delayHist | 9295 96.37% 96.37% | 0 0.00% 96.37% | 205 2.13% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 145 1.50% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::mean 0.162571 # delay histogram for all message +system.ruby.delayHist::stdev 1.010166 # delay histogram for all message +system.ruby.delayHist | 9296 96.38% 96.38% | 0 0.00% 96.38% | 204 2.12% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 145 1.50% 100.00% | 0 0.00% 100.00% # delay histogram for all message system.ruby.delayHist::total 9645 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 @@ -375,10 +377,10 @@ system.ruby.outstanding_req_hist::total 8449 system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8448 -system.ruby.latency_hist::mean 15.410630 -system.ruby.latency_hist::gmean 5.220490 -system.ruby.latency_hist::stdev 29.556532 -system.ruby.latency_hist | 7278 86.15% 86.15% | 1151 13.62% 99.78% | 3 0.04% 99.81% | 2 0.02% 99.83% | 6 0.07% 99.91% | 8 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::mean 15.420928 +system.ruby.latency_hist::gmean 5.221828 +system.ruby.latency_hist::stdev 29.495379 +system.ruby.latency_hist | 7276 86.13% 86.13% | 1152 13.64% 99.76% | 4 0.05% 99.81% | 4 0.05% 99.86% | 4 0.05% 99.91% | 8 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8448 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 @@ -390,10 +392,10 @@ system.ruby.hit_latency_hist::total 6958 system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1490 -system.ruby.miss_latency_hist::mean 73.365772 -system.ruby.miss_latency_hist::gmean 69.377440 -system.ruby.miss_latency_hist::stdev 29.580633 -system.ruby.miss_latency_hist | 320 21.48% 21.48% | 1151 77.25% 98.72% | 3 0.20% 98.93% | 2 0.13% 99.06% | 6 0.40% 99.46% | 8 0.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::mean 73.424161 +system.ruby.miss_latency_hist::gmean 69.478292 +system.ruby.miss_latency_hist::stdev 29.116195 +system.ruby.miss_latency_hist | 318 21.34% 21.34% | 1152 77.32% 98.66% | 4 0.27% 98.93% | 4 0.27% 99.19% | 4 0.27% 99.46% | 8 0.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1490 system.ruby.l1_cntrl0.L1Dcache.demand_hits 1249 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 799 # Number of cache demand misses @@ -414,7 +416,7 @@ system.ruby.l2_cntrl0.L2cache.demand_hits 30 # N system.ruby.l2_cntrl0.L2cache.demand_misses 1460 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 1490 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 3.776229 +system.ruby.network.routers0.percent_links_utilized 3.773860 system.ruby.network.routers0.msg_count.Control::0 1490 system.ruby.network.routers0.msg_count.Request_Control::2 1041 system.ruby.network.routers0.msg_count.Response_Data::1 1490 @@ -431,7 +433,7 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2 6392 system.ruby.network.routers0.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers0.msg_bytes.Writeback_Data::1 10152 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 2328 -system.ruby.network.routers1.percent_links_utilized 7.332278 +system.ruby.network.routers1.percent_links_utilized 7.327679 system.ruby.network.routers1.msg_count.Control::0 2950 system.ruby.network.routers1.msg_count.Request_Control::2 1041 system.ruby.network.routers1.msg_count.Response_Data::1 3227 @@ -448,14 +450,14 @@ system.ruby.network.routers1.msg_bytes.Response_Control::2 6392 system.ruby.network.routers1.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers1.msg_bytes.Writeback_Data::1 10152 system.ruby.network.routers1.msg_bytes.Writeback_Control::0 2328 -system.ruby.network.routers2.percent_links_utilized 3.556049 +system.ruby.network.routers2.percent_links_utilized 3.553819 system.ruby.network.routers2.msg_count.Control::0 1460 system.ruby.network.routers2.msg_count.Response_Data::1 1737 system.ruby.network.routers2.msg_count.Response_Control::1 2627 system.ruby.network.routers2.msg_bytes.Control::0 11680 system.ruby.network.routers2.msg_bytes.Response_Data::1 125064 system.ruby.network.routers2.msg_bytes.Response_Control::1 21016 -system.ruby.network.routers3.percent_links_utilized 4.888185 +system.ruby.network.routers3.percent_links_utilized 4.885120 system.ruby.network.routers3.msg_count.Control::0 2950 system.ruby.network.routers3.msg_count.Request_Control::2 1041 system.ruby.network.routers3.msg_count.Response_Data::1 3227 @@ -484,14 +486,14 @@ system.ruby.network.msg_byte.Response_Data 697032 system.ruby.network.msg_byte.Response_Control 114288 system.ruby.network.msg_byte.Writeback_Data 61776 system.ruby.network.msg_byte.Writeback_Control 6984 -system.ruby.network.routers0.throttle0.link_utilization 5.369057 +system.ruby.network.routers0.throttle0.link_utilization 5.365690 system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 1041 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 1490 system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 436 system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 8328 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 107280 system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 3488 -system.ruby.network.routers0.throttle1.link_utilization 2.183400 +system.ruby.network.routers0.throttle1.link_utilization 2.182031 system.ruby.network.routers0.throttle1.msg_count.Control::0 1490 system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 900 system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 799 @@ -504,7 +506,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 639 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 10152 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 2328 -system.ruby.network.routers1.throttle0.link_utilization 7.446064 +system.ruby.network.routers1.throttle0.link_utilization 7.441394 system.ruby.network.routers1.throttle0.msg_count.Control::0 1490 system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 1460 system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 2352 @@ -519,7 +521,7 @@ system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 639 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 10152 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 2328 -system.ruby.network.routers1.throttle1.link_utilization 7.218491 +system.ruby.network.routers1.throttle1.link_utilization 7.213964 system.ruby.network.routers1.throttle1.msg_count.Control::0 1460 system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 1041 system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1767 @@ -528,26 +530,26 @@ system.ruby.network.routers1.throttle1.msg_bytes.Control::0 11680 system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 8328 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 127224 system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 12888 -system.ruby.network.routers2.throttle0.link_utilization 1.849434 +system.ruby.network.routers2.throttle0.link_utilization 1.848274 system.ruby.network.routers2.throttle0.msg_count.Control::0 1460 system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 277 system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 1175 system.ruby.network.routers2.throttle0.msg_bytes.Control::0 11680 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 19944 system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 9400 -system.ruby.network.routers2.throttle1.link_utilization 5.262664 +system.ruby.network.routers2.throttle1.link_utilization 5.259364 system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 1460 system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1452 system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 105120 system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 11616 -system.ruby.network.routers3.throttle0.link_utilization 5.369057 +system.ruby.network.routers3.throttle0.link_utilization 5.365690 system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 1041 system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 1490 system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 436 system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 8328 system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 107280 system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 3488 -system.ruby.network.routers3.throttle1.link_utilization 7.446064 +system.ruby.network.routers3.throttle1.link_utilization 7.441394 system.ruby.network.routers3.throttle1.msg_count.Control::0 1490 system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 1460 system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 2352 @@ -562,7 +564,7 @@ system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 639 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 10152 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 2328 -system.ruby.network.routers3.throttle2.link_utilization 1.849434 +system.ruby.network.routers3.throttle2.link_utilization 1.848274 system.ruby.network.routers3.throttle2.msg_count.Control::0 1460 system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 277 system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 1175 @@ -579,9 +581,9 @@ system.ruby.delayVCHist.vnet_0::total 2725 # de system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::samples 5879 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.069740 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 0.366932 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 5674 96.51% 96.51% | 0 0.00% 96.51% | 205 3.49% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.069400 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 0.366068 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 5675 96.53% 96.53% | 0 0.00% 96.53% | 204 3.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::total 5879 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 @@ -591,10 +593,10 @@ system.ruby.delayVCHist.vnet_2::total 1041 # de system.ruby.LD.latency_hist::bucket_size 64 system.ruby.LD.latency_hist::max_bucket 639 system.ruby.LD.latency_hist::samples 1183 -system.ruby.LD.latency_hist::mean 35.343195 -system.ruby.LD.latency_hist::gmean 13.647233 -system.ruby.LD.latency_hist::stdev 36.940945 -system.ruby.LD.latency_hist | 797 67.37% 67.37% | 383 32.38% 99.75% | 1 0.08% 99.83% | 0 0.00% 99.83% | 1 0.08% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::mean 35.984784 +system.ruby.LD.latency_hist::gmean 13.718106 +system.ruby.LD.latency_hist::stdev 39.109328 +system.ruby.LD.latency_hist | 793 67.03% 67.03% | 384 32.46% 99.49% | 1 0.08% 99.58% | 1 0.08% 99.66% | 2 0.17% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist::total 1183 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 @@ -606,18 +608,18 @@ system.ruby.LD.hit_latency_hist::total 600 system.ruby.LD.miss_latency_hist::bucket_size 64 system.ruby.LD.miss_latency_hist::max_bucket 639 system.ruby.LD.miss_latency_hist::samples 583 -system.ruby.LD.miss_latency_hist::mean 68.629503 -system.ruby.LD.miss_latency_hist::gmean 64.886248 -system.ruby.LD.miss_latency_hist::stdev 24.148594 -system.ruby.LD.miss_latency_hist | 197 33.79% 33.79% | 383 65.69% 99.49% | 1 0.17% 99.66% | 0 0.00% 99.66% | 1 0.17% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::mean 69.931389 +system.ruby.LD.miss_latency_hist::gmean 65.571846 +system.ruby.LD.miss_latency_hist::stdev 28.816437 +system.ruby.LD.miss_latency_hist | 193 33.10% 33.10% | 384 65.87% 98.97% | 1 0.17% 99.14% | 1 0.17% 99.31% | 2 0.34% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 583 system.ruby.ST.latency_hist::bucket_size 64 system.ruby.ST.latency_hist::max_bucket 639 system.ruby.ST.latency_hist::samples 865 -system.ruby.ST.latency_hist::mean 17.890173 -system.ruby.ST.latency_hist::gmean 6.261514 -system.ruby.ST.latency_hist::stdev 30.772511 -system.ruby.ST.latency_hist | 767 88.67% 88.67% | 95 10.98% 99.65% | 1 0.12% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::mean 18.053179 +system.ruby.ST.latency_hist::gmean 6.262232 +system.ruby.ST.latency_hist::stdev 31.945584 +system.ruby.ST.latency_hist | 769 88.90% 88.90% | 92 10.64% 99.54% | 1 0.12% 99.65% | 0 0.00% 99.65% | 1 0.12% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist::total 865 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 @@ -629,18 +631,18 @@ system.ruby.ST.hit_latency_hist::total 649 system.ruby.ST.miss_latency_hist::bucket_size 64 system.ruby.ST.miss_latency_hist::max_bucket 639 system.ruby.ST.miss_latency_hist::samples 216 -system.ruby.ST.miss_latency_hist::mean 62.629630 -system.ruby.ST.miss_latency_hist::gmean 57.125913 -system.ruby.ST.miss_latency_hist::stdev 33.544027 -system.ruby.ST.miss_latency_hist | 118 54.63% 54.63% | 95 43.98% 98.61% | 1 0.46% 99.07% | 0 0.00% 99.07% | 0 0.00% 99.07% | 2 0.93% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::mean 63.282407 +system.ruby.ST.miss_latency_hist::gmean 57.152160 +system.ruby.ST.miss_latency_hist::stdev 36.903379 +system.ruby.ST.miss_latency_hist | 120 55.56% 55.56% | 92 42.59% 98.15% | 1 0.46% 98.61% | 0 0.00% 98.61% | 1 0.46% 99.07% | 2 0.93% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 216 system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6400 -system.ruby.IFETCH.latency_hist::mean 11.391094 -system.ruby.IFETCH.latency_hist::gmean 4.264782 -system.ruby.IFETCH.latency_hist::stdev 26.130654 -system.ruby.IFETCH.latency_hist | 5714 89.28% 89.28% | 673 10.52% 99.80% | 1 0.02% 99.81% | 2 0.03% 99.84% | 5 0.08% 99.92% | 5 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::mean 11.264062 +system.ruby.IFETCH.latency_hist::gmean 4.262075 +system.ruby.IFETCH.latency_hist::stdev 25.133535 +system.ruby.IFETCH.latency_hist | 5714 89.28% 89.28% | 676 10.56% 99.84% | 2 0.03% 99.88% | 3 0.05% 99.92% | 1 0.02% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6400 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 @@ -652,10 +654,10 @@ system.ruby.IFETCH.hit_latency_hist::total 5709 system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 691 -system.ruby.IFETCH.miss_latency_hist::mean 80.717800 -system.ruby.IFETCH.miss_latency_hist::gmean 78.004389 -system.ruby.IFETCH.miss_latency_hist::stdev 30.603968 -system.ruby.IFETCH.miss_latency_hist | 5 0.72% 0.72% | 673 97.40% 98.12% | 1 0.14% 98.26% | 2 0.29% 98.55% | 5 0.72% 99.28% | 5 0.72% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::mean 79.541245 +system.ruby.IFETCH.miss_latency_hist::gmean 77.547127 +system.ruby.IFETCH.miss_latency_hist::stdev 24.993726 +system.ruby.IFETCH.miss_latency_hist | 5 0.72% 0.72% | 676 97.83% 98.55% | 2 0.29% 98.84% | 3 0.43% 99.28% | 1 0.14% 99.42% | 4 0.58% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 691 system.ruby.Directory_Controller.Fetch 1460 0.00% 0.00% system.ruby.Directory_Controller.Data 277 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index d5c587675..216848fe0 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000126 # Number of seconds simulated -sim_ticks 126195 # Number of ticks simulated -final_tick 126195 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 126343 # Number of ticks simulated +final_tick 126343 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 43805 # Simulator instruction rate (inst/s) -host_op_rate 43801 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 864948 # Simulator tick rate (ticks/s) -host_mem_usage 454088 # Number of bytes of host memory used +host_inst_rate 43834 # Simulator instruction rate (inst/s) +host_op_rate 43830 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 866526 # Simulator tick rate (ticks/s) +host_mem_usage 454420 # Number of bytes of host memory used host_seconds 0.15 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated @@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1182 # system.mem_ctrls.num_reads::total 1182 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 194 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 194 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 599453227 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 599453227 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 98387416 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 98387416 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 697840643 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 697840643 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 598751019 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 598751019 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 98272164 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 98272164 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 697023183 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 697023183 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1182 # Number of read requests accepted system.mem_ctrls.writeReqs 194 # Number of write requests accepted system.mem_ctrls.readBursts 1182 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 194 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 64576 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 11072 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 5248 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 64512 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 11136 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 5376 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 75648 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 12416 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 173 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 83 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 174 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 78 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 83 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 51 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 81 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 75 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 91 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 18 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 99 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 20 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 2 # Per bank write bursts system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 56 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 51 # Per bank write bursts system.mem_ctrls.perBankRdBursts::11 51 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 21 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 365 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 71 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 363 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 67 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 40 # Per bank write bursts system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 15 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 3 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 21 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 9 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 2 # Per bank write bursts system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 18 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 43 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 15 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 37 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 126127 # Total gap between requests +system.mem_ctrls.totGap 126275 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 194 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 1009 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 1008 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -135,8 +135,8 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 3 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::17 5 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see @@ -149,9 +149,9 @@ system.mem_ctrls.wrQLenPdf::25 6 # Wh system.mem_ctrls.wrQLenPdf::26 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::27 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::28 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::32 5 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see @@ -184,86 +184,86 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 211 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 327.582938 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 201.542711 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 321.278601 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 66 31.28% 31.28% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 57 27.01% 58.29% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 21 9.95% 68.25% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 10 4.74% 72.99% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 14 6.64% 79.62% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 12 5.69% 85.31% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 5 2.37% 87.68% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 3 1.42% 89.10% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 23 10.90% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 211 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 212 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 326.339623 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 200.746581 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 319.329567 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 67 31.60% 31.60% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 54 25.47% 57.08% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 23 10.85% 67.92% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 13 6.13% 74.06% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 12 5.66% 79.72% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 12 5.66% 85.38% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 6 2.83% 88.21% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 3 1.42% 89.62% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 22 10.38% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 212 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 141 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 106.525720 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 81.341871 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 136.800000 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 103.930082 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 78.649221 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::120-127 1 20.00% 40.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::112-119 1 20.00% 40.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::128-135 1 20.00% 60.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::208-215 1 20.00% 80.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::192-199 1 20.00% 80.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.400000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.381380 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.894427 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 4 80.00% 80.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 1 20.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.800000 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.771851 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.095445 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 3 60.00% 60.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 2 40.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 7775 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 26946 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 5045 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 7.71 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 7952 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 27104 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 5040 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 7.89 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 26.71 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 511.72 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 41.59 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 599.45 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 98.39 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 26.89 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 510.61 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 42.55 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 598.75 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 98.27 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrls.busUtil 4.32 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.00 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.32 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtilRead 3.99 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.33 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 22.42 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 799 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 76 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 79.19 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 68.47 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 91.66 # Average gap between requests -system.mem_ctrls.pageHitRate 78.12 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 551880 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 306600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 4992000 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 186624 # Energy for write commands per rank (pJ) +system.mem_ctrls.avgWrQLen 22.50 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 801 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 74 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 79.46 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 63.79 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 91.77 # Average gap between requests +system.mem_ctrls.pageHitRate 77.85 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 567000 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 315000 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5116800 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 311040 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 8136960 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 64142784 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 18636000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 96952848 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 776.641738 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 31414 # Time in different power states +system.mem_ctrls_0.actBackEnergy 63365076 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 19318200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 97130076 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 778.061425 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 32699 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 4160 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 90106 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 88969 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 1035720 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 575400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 7450560 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 663552 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.actEnergy 1028160 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 571200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 7300800 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 559872 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 8136960 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 84064968 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 1160400 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 103087560 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 825.783908 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 1262 # Time in different power states +system.mem_ctrls_1.actBackEnergy 84071808 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 1154400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 102823200 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 823.666250 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1294 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 4160 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 119428 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 119396 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -299,7 +299,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 126195 # number of cpu cycles simulated +system.cpu.numCycles 126343 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6390 # Number of instructions committed @@ -318,7 +318,7 @@ system.cpu.num_mem_refs 2058 # nu system.cpu.num_load_insts 1190 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 126195 # Number of busy cycles +system.cpu.num_busy_cycles 126343 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched @@ -368,10 +368,10 @@ system.ruby.outstanding_req_hist::total 8449 system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8448 -system.ruby.latency_hist::mean 13.937855 -system.ruby.latency_hist::gmean 4.957827 -system.ruby.latency_hist::stdev 28.413153 -system.ruby.latency_hist | 7438 88.04% 88.04% | 992 11.74% 99.79% | 2 0.02% 99.81% | 1 0.01% 99.82% | 11 0.13% 99.95% | 3 0.04% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::mean 13.955374 +system.ruby.latency_hist::gmean 4.957459 +system.ruby.latency_hist::stdev 28.739433 +system.ruby.latency_hist | 7439 88.06% 88.06% | 992 11.74% 99.80% | 2 0.02% 99.82% | 0 0.00% 99.82% | 4 0.05% 99.87% | 10 0.12% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8448 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 @@ -383,10 +383,10 @@ system.ruby.hit_latency_hist::total 7027 system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1421 -system.ruby.miss_latency_hist::mean 68.026742 -system.ruby.miss_latency_hist::gmean 59.451968 -system.ruby.miss_latency_hist::stdev 35.813966 -system.ruby.miss_latency_hist | 411 28.92% 28.92% | 992 69.81% 98.73% | 2 0.14% 98.87% | 1 0.07% 98.94% | 11 0.77% 99.72% | 3 0.21% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::mean 68.130894 +system.ruby.miss_latency_hist::gmean 59.425748 +system.ruby.miss_latency_hist::stdev 37.179084 +system.ruby.miss_latency_hist | 412 28.99% 28.99% | 992 69.81% 98.80% | 2 0.14% 98.94% | 0 0.00% 98.94% | 4 0.28% 99.23% | 10 0.70% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1421 system.ruby.l1_cntrl0.L1Dcache.demand_hits 1273 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 775 # Number of cache demand misses @@ -398,7 +398,7 @@ system.ruby.l2_cntrl0.L2cache.demand_hits 239 # N system.ruby.l2_cntrl0.L2cache.demand_misses 1182 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 1421 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 5.974286 +system.ruby.network.routers0.percent_links_utilized 5.967287 system.ruby.network.routers0.msg_count.Request_Control::0 1421 system.ruby.network.routers0.msg_count.Response_Data::2 1182 system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 239 @@ -411,7 +411,7 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 17208 system.ruby.network.routers0.msg_bytes.Writeback_Data::2 94176 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 21664 system.ruby.network.routers0.msg_bytes.Unblock_Control::2 11736 -system.ruby.network.routers1.percent_links_utilized 8.972820 +system.ruby.network.routers1.percent_links_utilized 8.962309 system.ruby.network.routers1.msg_count.Request_Control::0 1421 system.ruby.network.routers1.msg_count.Request_Control::1 1182 system.ruby.network.routers1.msg_count.Response_Data::2 2364 @@ -428,7 +428,7 @@ system.ruby.network.routers1.msg_bytes.Writeback_Data::2 108144 system.ruby.network.routers1.msg_bytes.Writeback_Control::0 21664 system.ruby.network.routers1.msg_bytes.Writeback_Control::1 3104 system.ruby.network.routers1.msg_bytes.Unblock_Control::2 21192 -system.ruby.network.routers2.percent_links_utilized 2.998534 +system.ruby.network.routers2.percent_links_utilized 2.995021 system.ruby.network.routers2.msg_count.Request_Control::1 1182 system.ruby.network.routers2.msg_count.Response_Data::2 1182 system.ruby.network.routers2.msg_count.Writeback_Data::2 194 @@ -439,7 +439,7 @@ system.ruby.network.routers2.msg_bytes.Response_Data::2 85104 system.ruby.network.routers2.msg_bytes.Writeback_Data::2 13968 system.ruby.network.routers2.msg_bytes.Writeback_Control::1 3104 system.ruby.network.routers2.msg_bytes.Unblock_Control::2 9456 -system.ruby.network.routers3.percent_links_utilized 5.981880 +system.ruby.network.routers3.percent_links_utilized 5.974873 system.ruby.network.routers3.msg_count.Request_Control::0 1421 system.ruby.network.routers3.msg_count.Request_Control::1 1182 system.ruby.network.routers3.msg_count.Response_Data::2 2364 @@ -468,14 +468,14 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 51624 system.ruby.network.msg_byte.Writeback_Data 324432 system.ruby.network.msg_byte.Writeback_Control 74304 system.ruby.network.msg_byte.Unblock_Control 63576 -system.ruby.network.routers0.throttle0.link_utilization 5.603629 +system.ruby.network.routers0.throttle0.link_utilization 5.597065 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 1182 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 239 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 1354 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 85104 system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 17208 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 10832 -system.ruby.network.routers0.throttle1.link_utilization 6.344942 +system.ruby.network.routers0.throttle1.link_utilization 6.337510 system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 1421 system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 1308 system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 1354 @@ -484,7 +484,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 11368 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 94176 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 10832 system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 11736 -system.ruby.network.routers1.throttle0.link_utilization 10.636713 +system.ruby.network.routers1.throttle0.link_utilization 10.624253 system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 1421 system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 1182 system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 1308 @@ -497,7 +497,7 @@ system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 94176 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 10832 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 1552 system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 11736 -system.ruby.network.routers1.throttle1.link_utilization 7.308927 +system.ruby.network.routers1.throttle1.link_utilization 7.300365 system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 1182 system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 1182 system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 239 @@ -512,7 +512,7 @@ system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 13968 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 10832 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 1552 system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 9456 -system.ruby.network.routers2.throttle0.link_utilization 1.705297 +system.ruby.network.routers2.throttle0.link_utilization 1.703300 system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 1182 system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 194 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 194 @@ -521,19 +521,19 @@ system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 9456 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 13968 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 1552 system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 9456 -system.ruby.network.routers2.throttle1.link_utilization 4.291771 +system.ruby.network.routers2.throttle1.link_utilization 4.286743 system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 1182 system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 194 system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 85104 system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 1552 -system.ruby.network.routers3.throttle0.link_utilization 5.603629 +system.ruby.network.routers3.throttle0.link_utilization 5.597065 system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 1182 system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 239 system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 1354 system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 85104 system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 17208 system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 10832 -system.ruby.network.routers3.throttle1.link_utilization 10.636713 +system.ruby.network.routers3.throttle1.link_utilization 10.624253 system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 1421 system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 1182 system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 1308 @@ -546,7 +546,7 @@ system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 94176 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 10832 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 1552 system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 11736 -system.ruby.network.routers3.throttle2.link_utilization 1.705297 +system.ruby.network.routers3.throttle2.link_utilization 1.703300 system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 1182 system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 194 system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 194 @@ -558,10 +558,10 @@ system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 9456 system.ruby.LD.latency_hist::bucket_size 64 system.ruby.LD.latency_hist::max_bucket 639 system.ruby.LD.latency_hist::samples 1183 -system.ruby.LD.latency_hist::mean 29.370245 -system.ruby.LD.latency_hist::gmean 10.775321 -system.ruby.LD.latency_hist::stdev 36.738545 -system.ruby.LD.latency_hist | 860 72.70% 72.70% | 320 27.05% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 2 0.17% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::mean 29.639053 +system.ruby.LD.latency_hist::gmean 10.782209 +system.ruby.LD.latency_hist::stdev 38.418359 +system.ruby.LD.latency_hist | 863 72.95% 72.95% | 315 26.63% 99.58% | 1 0.08% 99.66% | 0 0.00% 99.66% | 1 0.08% 99.75% | 3 0.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist::total 1183 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 @@ -573,18 +573,18 @@ system.ruby.LD.hit_latency_hist::total 658 system.ruby.LD.miss_latency_hist::bucket_size 64 system.ruby.LD.miss_latency_hist::max_bucket 639 system.ruby.LD.miss_latency_hist::samples 525 -system.ruby.LD.miss_latency_hist::mean 62.420952 -system.ruby.LD.miss_latency_hist::gmean 53.507846 -system.ruby.LD.miss_latency_hist::stdev 32.816863 -system.ruby.LD.miss_latency_hist | 202 38.48% 38.48% | 320 60.95% 99.43% | 0 0.00% 99.43% | 0 0.00% 99.43% | 2 0.38% 99.81% | 1 0.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::mean 63.026667 +system.ruby.LD.miss_latency_hist::gmean 53.584951 +system.ruby.LD.miss_latency_hist::stdev 36.351224 +system.ruby.LD.miss_latency_hist | 205 39.05% 39.05% | 315 60.00% 99.05% | 1 0.19% 99.24% | 0 0.00% 99.24% | 1 0.19% 99.43% | 3 0.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 525 system.ruby.ST.latency_hist::bucket_size 64 system.ruby.ST.latency_hist::max_bucket 639 system.ruby.ST.latency_hist::samples 865 -system.ruby.ST.latency_hist::mean 19.187283 -system.ruby.ST.latency_hist::gmean 6.808148 -system.ruby.ST.latency_hist::stdev 31.171451 -system.ruby.ST.latency_hist | 753 87.05% 87.05% | 108 12.49% 99.54% | 2 0.23% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::mean 18.927168 +system.ruby.ST.latency_hist::gmean 6.798661 +system.ruby.ST.latency_hist::stdev 29.816693 +system.ruby.ST.latency_hist | 751 86.82% 86.82% | 112 12.95% 99.77% | 1 0.12% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist::total 865 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 @@ -596,18 +596,18 @@ system.ruby.ST.hit_latency_hist::total 615 system.ruby.ST.miss_latency_hist::bucket_size 64 system.ruby.ST.miss_latency_hist::max_bucket 639 system.ruby.ST.miss_latency_hist::samples 250 -system.ruby.ST.miss_latency_hist::mean 59.008000 -system.ruby.ST.miss_latency_hist::gmean 51.116604 -system.ruby.ST.miss_latency_hist::stdev 33.649742 -system.ruby.ST.miss_latency_hist | 138 55.20% 55.20% | 108 43.20% 98.40% | 2 0.80% 99.20% | 0 0.00% 99.20% | 1 0.40% 99.60% | 1 0.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::mean 58.108000 +system.ruby.ST.miss_latency_hist::gmean 50.870585 +system.ruby.ST.miss_latency_hist::stdev 30.281947 +system.ruby.ST.miss_latency_hist | 136 54.40% 54.40% | 112 44.80% 99.20% | 1 0.40% 99.60% | 0 0.00% 99.60% | 0 0.00% 99.60% | 1 0.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 250 system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6400 -system.ruby.IFETCH.latency_hist::mean 10.375781 -system.ruby.IFETCH.latency_hist::gmean 4.114880 -system.ruby.IFETCH.latency_hist::stdev 24.994631 -system.ruby.IFETCH.latency_hist | 5825 91.02% 91.02% | 564 8.81% 99.83% | 0 0.00% 99.83% | 1 0.02% 99.84% | 8 0.12% 99.97% | 1 0.02% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::mean 10.384375 +system.ruby.IFETCH.latency_hist::gmean 4.114767 +system.ruby.IFETCH.latency_hist::stdev 25.220182 +system.ruby.IFETCH.latency_hist | 5825 91.02% 91.02% | 565 8.83% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 3 0.05% 99.89% | 6 0.09% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6400 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 @@ -619,10 +619,10 @@ system.ruby.IFETCH.hit_latency_hist::total 5754 system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 646 -system.ruby.IFETCH.miss_latency_hist::mean 76.072755 -system.ruby.IFETCH.miss_latency_hist::gmean 68.664868 -system.ruby.IFETCH.miss_latency_hist::stdev 37.280241 -system.ruby.IFETCH.miss_latency_hist | 71 10.99% 10.99% | 564 87.31% 98.30% | 0 0.00% 98.30% | 1 0.15% 98.45% | 8 1.24% 99.69% | 1 0.15% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::mean 76.157895 +system.ruby.IFETCH.miss_latency_hist::gmean 68.646090 +system.ruby.IFETCH.miss_latency_hist::stdev 38.613086 +system.ruby.IFETCH.miss_latency_hist | 71 10.99% 10.99% | 565 87.46% 98.45% | 0 0.00% 98.45% | 0 0.00% 98.45% | 3 0.46% 98.92% | 6 0.93% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 646 system.ruby.Directory_Controller.GETX 198 0.00% 0.00% system.ruby.Directory_Controller.GETS 984 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index 23f7e060f..ca7e00529 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000117 # Number of seconds simulated -sim_ticks 116770 # Number of ticks simulated -final_tick 116770 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000116 # Number of seconds simulated +sim_ticks 116369 # Number of ticks simulated +final_tick 116369 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 63656 # Simulator instruction rate (inst/s) -host_op_rate 63646 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1162909 # Simulator tick rate (ticks/s) -host_mem_usage 451252 # Number of bytes of host memory used +host_inst_rate 61340 # Simulator instruction rate (inst/s) +host_op_rate 61332 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1116785 # Simulator tick rate (ticks/s) +host_mem_usage 453376 # Number of bytes of host memory used host_seconds 0.10 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated @@ -21,35 +21,35 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1176 # system.mem_ctrls.num_reads::total 1176 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 228 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 228 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 644549114 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 644549114 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 124963604 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 124963604 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 769512717 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 769512717 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 646770188 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 646770188 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 125394220 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 125394220 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 772164408 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 772164408 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1176 # Number of read requests accepted system.mem_ctrls.writeReqs 228 # Number of write requests accepted system.mem_ctrls.readBursts 1176 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 228 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 64960 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 10304 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 6144 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 64320 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 10944 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 5120 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 75264 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 14592 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 109 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 171 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 116 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 86 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 52 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 82 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 77 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 92 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 87 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 18 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 61 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 56 # Per bank write bursts system.mem_ctrls.perBankRdBursts::11 53 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 22 # Per bank write bursts system.mem_ctrls.perBankRdBursts::13 361 # Per bank write bursts @@ -59,21 +59,21 @@ system.mem_ctrls.perBankWrBursts::0 0 # Pe system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 26 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 15 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 5 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 21 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 44 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 18 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 43 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 116679 # Total gap between requests +system.mem_ctrls.totGap 116278 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 228 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 1015 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 1005 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -137,12 +137,12 @@ system.mem_ctrls.wrQLenPdf::13 1 # Wh system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 7 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::23 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::24 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::25 6 # What write queue length does an incoming req see @@ -152,7 +152,7 @@ system.mem_ctrls.wrQLenPdf::28 6 # Wh system.mem_ctrls.wrQLenPdf::29 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::30 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 5 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -184,85 +184,84 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 202 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 339.643564 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 206.317034 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 334.142270 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 63 31.19% 31.19% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 47 23.27% 54.46% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 25 12.38% 66.83% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 13 6.44% 73.27% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 14 6.93% 80.20% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 7 3.47% 83.66% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 3 1.49% 85.15% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 5 2.48% 87.62% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 25 12.38% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 202 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 155.833333 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 115.513983 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 90.977836 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-31 1 16.67% 16.67% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::80-95 1 16.67% 33.33% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::160-175 1 16.67% 50.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::192-207 1 16.67% 66.67% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::208-223 1 16.67% 83.33% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::256-271 1 16.67% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 6 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads +system.mem_ctrls.bytesPerActivate::samples 201 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 334.328358 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 202.953148 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 329.613215 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 65 32.34% 32.34% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 44 21.89% 54.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 26 12.94% 67.16% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 14 6.97% 74.13% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 13 6.47% 80.60% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 7 3.48% 84.08% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 4 1.99% 86.07% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 2.49% 88.56% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 23 11.44% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 201 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 135 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 98.212508 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 84.208076 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::80-87 1 20.00% 40.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::160-167 1 20.00% 60.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::192-199 1 20.00% 80.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 6 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 7533 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 26818 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 5075 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 7.42 # Average queueing delay per DRAM burst +system.mem_ctrls.wrPerTurnAround::16 5 100.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 7422 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 26517 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 5025 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 7.39 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 26.42 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 556.31 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 52.62 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 644.55 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 124.96 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 26.39 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 552.72 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 44.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 646.77 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 125.39 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 4.76 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.35 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.41 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 4.66 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.32 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.34 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 22.40 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 810 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 92 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 79.80 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 77.31 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 83.10 # Average gap between requests -system.mem_ctrls.pageHitRate 79.54 # Row buffer hit rate, read and write combined +system.mem_ctrls.avgWrQLen 22.99 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 804 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 74 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 80.00 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 66.07 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 82.82 # Average gap between requests +system.mem_ctrls.pageHitRate 78.60 # Row buffer hit rate, read and write combined system.mem_ctrls_0.actEnergy 514080 # Energy for activate commands per rank (pJ) system.mem_ctrls_0.preEnergy 285600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 5041920 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 269568 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.readEnergy 4992000 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 165888 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ) system.mem_ctrls_0.actBackEnergy 60923196 # Energy for active background per rank (pJ) system.mem_ctrls_0.preBackEnergy 12117000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 86271204 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 789.566591 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 22175 # Time in different power states +system.mem_ctrls_0.totalEnergy 86117604 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 788.160821 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 25118 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 3640 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT 85821 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrls_1.actEnergy 937440 # Energy for activate commands per rank (pJ) system.mem_ctrls_1.preEnergy 520800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 6764160 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 725760 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.readEnergy 6776640 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 663552 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 72391140 # Energy for active background per rank (pJ) +system.mem_ctrls_1.actBackEnergy 72408924 # Energy for active background per rank (pJ) system.mem_ctrls_1.preBackEnergy 2062800 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 90521940 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 828.401709 # Core power per rank (mW) +system.mem_ctrls_1.totalEnergy 90489996 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 827.912387 # Core power per rank (mW) system.mem_ctrls_1.memoryStateTime::IDLE 2878 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 102769 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 102795 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -298,7 +297,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 116770 # number of cpu cycles simulated +system.cpu.numCycles 116369 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6390 # Number of instructions committed @@ -317,7 +316,7 @@ system.cpu.num_mem_refs 2058 # nu system.cpu.num_load_insts 1190 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 116770 # Number of busy cycles +system.cpu.num_busy_cycles 116369 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched @@ -367,10 +366,10 @@ system.ruby.outstanding_req_hist::total 8449 system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8448 -system.ruby.latency_hist::mean 12.822206 -system.ruby.latency_hist::gmean 3.506830 -system.ruby.latency_hist::stdev 27.805292 -system.ruby.latency_hist | 7433 87.99% 87.99% | 995 11.78% 99.76% | 6 0.07% 99.83% | 2 0.02% 99.86% | 8 0.09% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::mean 12.774740 +system.ruby.latency_hist::gmean 3.504112 +system.ruby.latency_hist::stdev 27.744497 +system.ruby.latency_hist | 7443 88.10% 88.10% | 986 11.67% 99.78% | 5 0.06% 99.83% | 2 0.02% 99.86% | 7 0.08% 99.94% | 5 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8448 system.ruby.hit_latency_hist::bucket_size 4 system.ruby.hit_latency_hist::max_bucket 39 @@ -383,10 +382,10 @@ system.ruby.hit_latency_hist::total 7272 system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1176 -system.ruby.miss_latency_hist::mean 75.774660 -system.ruby.miss_latency_hist::gmean 72.686009 -system.ruby.miss_latency_hist::stdev 29.375504 -system.ruby.miss_latency_hist | 161 13.69% 13.69% | 995 84.61% 98.30% | 6 0.51% 98.81% | 2 0.17% 98.98% | 8 0.68% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::mean 75.433673 +system.ruby.miss_latency_hist::gmean 72.282303 +system.ruby.miss_latency_hist::stdev 29.690242 +system.ruby.miss_latency_hist | 171 14.54% 14.54% | 986 83.84% 98.38% | 5 0.43% 98.81% | 2 0.17% 98.98% | 7 0.60% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1176 system.ruby.Directory.incomplete_times 1175 system.ruby.l1_cntrl0.L1Dcache.demand_hits 1311 # Number of cache demand hits @@ -399,7 +398,7 @@ system.ruby.l2_cntrl0.L2cache.demand_hits 189 # N system.ruby.l2_cntrl0.L2cache.demand_misses 1194 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 1383 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 5.578702 +system.ruby.network.routers0.percent_links_utilized 5.597926 system.ruby.network.routers0.msg_count.Request_Control::1 1383 system.ruby.network.routers0.msg_count.Response_Data::4 1176 system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4 207 @@ -412,7 +411,7 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 14904 system.ruby.network.routers0.msg_bytes.Response_Control::4 8 system.ruby.network.routers0.msg_bytes.Writeback_Data::4 97488 system.ruby.network.routers0.msg_bytes.Persistent_Control::3 320 -system.ruby.network.routers1.percent_links_utilized 4.210200 +system.ruby.network.routers1.percent_links_utilized 4.224708 system.ruby.network.routers1.msg_count.Request_Control::1 1383 system.ruby.network.routers1.msg_count.Request_Control::2 1194 system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4 207 @@ -427,7 +426,7 @@ system.ruby.network.routers1.msg_bytes.Response_Control::4 8 system.ruby.network.routers1.msg_bytes.Writeback_Data::4 113904 system.ruby.network.routers1.msg_bytes.Writeback_Control::4 7728 system.ruby.network.routers1.msg_bytes.Persistent_Control::3 160 -system.ruby.network.routers2.percent_links_utilized 3.172048 +system.ruby.network.routers2.percent_links_utilized 3.182978 system.ruby.network.routers2.msg_count.Request_Control::2 1194 system.ruby.network.routers2.msg_count.Response_Data::4 1176 system.ruby.network.routers2.msg_count.Writeback_Data::4 228 @@ -438,7 +437,7 @@ system.ruby.network.routers2.msg_bytes.Response_Data::4 84672 system.ruby.network.routers2.msg_bytes.Writeback_Data::4 16416 system.ruby.network.routers2.msg_bytes.Writeback_Control::4 7728 system.ruby.network.routers2.msg_bytes.Persistent_Control::3 160 -system.ruby.network.routers3.percent_links_utilized 4.320316 +system.ruby.network.routers3.percent_links_utilized 4.335204 system.ruby.network.routers3.msg_count.Request_Control::1 1383 system.ruby.network.routers3.msg_count.Request_Control::2 1194 system.ruby.network.routers3.msg_count.Response_Data::4 1176 @@ -469,7 +468,7 @@ system.ruby.network.msg_byte.Response_Control 24 system.ruby.network.msg_byte.Writeback_Data 341712 system.ruby.network.msg_byte.Writeback_Control 23184 system.ruby.network.msg_byte.Persistent_Control 960 -system.ruby.network.routers0.throttle0.link_utilization 5.338700 +system.ruby.network.routers0.throttle0.link_utilization 5.357097 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1176 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 207 system.ruby.network.routers0.throttle0.msg_count.Response_Control::4 1 @@ -478,21 +477,21 @@ system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 84672 system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4 14904 system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4 8 system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3 160 -system.ruby.network.routers0.throttle1.link_utilization 5.818703 +system.ruby.network.routers0.throttle1.link_utilization 5.838754 system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 1383 system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 1354 system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 20 system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 11064 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 97488 system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 160 -system.ruby.network.routers1.throttle0.link_utilization 5.818703 +system.ruby.network.routers1.throttle0.link_utilization 5.838754 system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 1383 system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 1354 system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 20 system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 11064 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 97488 system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 160 -system.ruby.network.routers1.throttle1.link_utilization 2.601696 +system.ruby.network.routers1.throttle1.link_utilization 2.610661 system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 1194 system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4 207 system.ruby.network.routers1.throttle1.msg_count.Response_Control::4 1 @@ -503,7 +502,7 @@ system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4 14 system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4 8 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4 16416 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 7728 -system.ruby.network.routers2.throttle0.link_utilization 1.812109 +system.ruby.network.routers2.throttle0.link_utilization 1.818354 system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 1194 system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4 228 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 966 @@ -512,24 +511,24 @@ system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 9552 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4 16416 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 7728 system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 160 -system.ruby.network.routers2.throttle1.link_utilization 4.531986 +system.ruby.network.routers2.throttle1.link_utilization 4.547603 system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 1176 system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 84672 -system.ruby.network.routers3.throttle0.link_utilization 5.330136 +system.ruby.network.routers3.throttle0.link_utilization 5.348503 system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 1176 system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4 207 system.ruby.network.routers3.throttle0.msg_count.Response_Control::4 1 system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 84672 system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4 14904 system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4 8 -system.ruby.network.routers3.throttle1.link_utilization 5.818703 +system.ruby.network.routers3.throttle1.link_utilization 5.838754 system.ruby.network.routers3.throttle1.msg_count.Request_Control::1 1383 system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4 1354 system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3 20 system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1 11064 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4 97488 system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3 160 -system.ruby.network.routers3.throttle2.link_utilization 1.812109 +system.ruby.network.routers3.throttle2.link_utilization 1.818354 system.ruby.network.routers3.throttle2.msg_count.Request_Control::2 1194 system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4 228 system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4 966 @@ -541,10 +540,10 @@ system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 system.ruby.LD.latency_hist::bucket_size 64 system.ruby.LD.latency_hist::max_bucket 639 system.ruby.LD.latency_hist::samples 1183 -system.ruby.LD.latency_hist::mean 29.646661 -system.ruby.LD.latency_hist::gmean 8.889029 -system.ruby.LD.latency_hist::stdev 37.195991 -system.ruby.LD.latency_hist | 844 71.34% 71.34% | 335 28.32% 99.66% | 0 0.00% 99.66% | 2 0.17% 99.83% | 1 0.08% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::mean 29.333897 +system.ruby.LD.latency_hist::gmean 8.854915 +system.ruby.LD.latency_hist::stdev 36.549796 +system.ruby.LD.latency_hist | 850 71.85% 71.85% | 330 27.90% 99.75% | 0 0.00% 99.75% | 1 0.08% 99.83% | 1 0.08% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist::total 1183 system.ruby.LD.hit_latency_hist::bucket_size 4 system.ruby.LD.hit_latency_hist::max_bucket 39 @@ -557,18 +556,18 @@ system.ruby.LD.hit_latency_hist::total 760 system.ruby.LD.miss_latency_hist::bucket_size 64 system.ruby.LD.miss_latency_hist::max_bucket 639 system.ruby.LD.miss_latency_hist::samples 423 -system.ruby.LD.miss_latency_hist::mean 73.808511 -system.ruby.LD.miss_latency_hist::gmean 70.625115 -system.ruby.LD.miss_latency_hist::stdev 26.886169 -system.ruby.LD.miss_latency_hist | 84 19.86% 19.86% | 335 79.20% 99.05% | 0 0.00% 99.05% | 2 0.47% 99.53% | 1 0.24% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::mean 72.933806 +system.ruby.LD.miss_latency_hist::gmean 69.869692 +system.ruby.LD.miss_latency_hist::stdev 25.813501 +system.ruby.LD.miss_latency_hist | 90 21.28% 21.28% | 330 78.01% 99.29% | 0 0.00% 99.29% | 1 0.24% 99.53% | 1 0.24% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 423 system.ruby.ST.latency_hist::bucket_size 64 system.ruby.ST.latency_hist::max_bucket 639 system.ruby.ST.latency_hist::samples 865 -system.ruby.ST.latency_hist::mean 15.620809 -system.ruby.ST.latency_hist::gmean 4.414027 -system.ruby.ST.latency_hist::stdev 30.143438 -system.ruby.ST.latency_hist | 774 89.48% 89.48% | 87 10.06% 99.54% | 2 0.23% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::mean 15.470520 +system.ruby.ST.latency_hist::gmean 4.402566 +system.ruby.ST.latency_hist::stdev 29.923272 +system.ruby.ST.latency_hist | 778 89.94% 89.94% | 83 9.60% 99.54% | 2 0.23% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist::total 865 system.ruby.ST.hit_latency_hist::bucket_size 4 system.ruby.ST.hit_latency_hist::max_bucket 39 @@ -581,18 +580,18 @@ system.ruby.ST.hit_latency_hist::total 697 system.ruby.ST.miss_latency_hist::bucket_size 64 system.ruby.ST.miss_latency_hist::max_bucket 639 system.ruby.ST.miss_latency_hist::samples 168 -system.ruby.ST.miss_latency_hist::mean 66.535714 -system.ruby.ST.miss_latency_hist::gmean 61.950283 -system.ruby.ST.miss_latency_hist::stdev 36.753409 -system.ruby.ST.miss_latency_hist | 77 45.83% 45.83% | 87 51.79% 97.62% | 2 1.19% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 2 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::mean 65.761905 +system.ruby.ST.miss_latency_hist::gmean 61.126570 +system.ruby.ST.miss_latency_hist::stdev 36.894126 +system.ruby.ST.miss_latency_hist | 81 48.21% 48.21% | 83 49.40% 97.62% | 2 1.19% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 2 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 168 system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6400 -system.ruby.IFETCH.latency_hist::mean 9.334062 -system.ruby.IFETCH.latency_hist::gmean 2.862491 -system.ruby.IFETCH.latency_hist::stdev 24.016058 -system.ruby.IFETCH.latency_hist | 5815 90.86% 90.86% | 573 8.95% 99.81% | 4 0.06% 99.87% | 0 0.00% 99.87% | 7 0.11% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::mean 9.349531 +system.ruby.IFETCH.latency_hist::gmean 2.862602 +system.ruby.IFETCH.latency_hist::stdev 24.187807 +system.ruby.IFETCH.latency_hist | 5815 90.86% 90.86% | 573 8.95% 99.81% | 3 0.05% 99.86% | 1 0.02% 99.87% | 6 0.09% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6400 system.ruby.IFETCH.hit_latency_hist::bucket_size 4 system.ruby.IFETCH.hit_latency_hist::max_bucket 39 @@ -605,10 +604,10 @@ system.ruby.IFETCH.hit_latency_hist::total 5815 system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 585 -system.ruby.IFETCH.miss_latency_hist::mean 79.849573 -system.ruby.IFETCH.miss_latency_hist::gmean 77.699044 -system.ruby.IFETCH.miss_latency_hist::stdev 27.992378 -system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 573 97.95% 97.95% | 4 0.68% 98.63% | 0 0.00% 98.63% | 7 1.20% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::mean 80.018803 +system.ruby.IFETCH.miss_latency_hist::gmean 77.731964 +system.ruby.IFETCH.miss_latency_hist::stdev 29.160832 +system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 573 97.95% 97.95% | 3 0.51% 98.46% | 1 0.17% 98.63% | 6 1.03% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 585 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9 @@ -628,10 +627,10 @@ system.ruby.L2Cache.hit_mach_latency_hist::total 207 system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1176 -system.ruby.Directory.miss_mach_latency_hist::mean 75.774660 -system.ruby.Directory.miss_mach_latency_hist::gmean 72.686009 -system.ruby.Directory.miss_mach_latency_hist::stdev 29.375504 -system.ruby.Directory.miss_mach_latency_hist | 161 13.69% 13.69% | 995 84.61% 98.30% | 6 0.51% 98.81% | 2 0.17% 98.98% | 8 0.68% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::mean 75.433673 +system.ruby.Directory.miss_mach_latency_hist::gmean 72.282303 +system.ruby.Directory.miss_mach_latency_hist::stdev 29.690242 +system.ruby.Directory.miss_mach_latency_hist | 171 14.54% 14.54% | 986 83.84% 98.38% | 5 0.43% 98.81% | 2 0.17% 98.98% | 7 0.60% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1176 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 @@ -677,10 +676,10 @@ system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 102 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 423 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 73.808511 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 70.625115 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 26.886169 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 84 19.86% 19.86% | 335 79.20% 99.05% | 0 0.00% 99.05% | 2 0.47% 99.53% | 1 0.24% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 72.933806 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 69.869692 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 25.813501 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 90 21.28% 21.28% | 330 78.01% 99.29% | 0 0.00% 99.29% | 1 0.24% 99.53% | 1 0.24% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 423 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9 @@ -700,10 +699,10 @@ system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 44 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 168 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 66.535714 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 61.950283 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 36.753409 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 77 45.83% 45.83% | 87 51.79% 97.62% | 2 1.19% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 2 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 65.761905 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 61.126570 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 36.894126 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 81 48.21% 48.21% | 83 49.40% 97.62% | 2 1.19% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 2 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist::total 168 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket 9 @@ -723,10 +722,10 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total 61 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 585 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 79.849573 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 77.699044 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 27.992378 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 573 97.95% 97.95% | 4 0.68% 98.63% | 0 0.00% 98.63% | 7 1.20% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 80.018803 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 77.731964 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 29.160832 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 573 97.95% 97.95% | 3 0.51% 98.46% | 1 0.17% 98.63% | 6 1.03% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 585 system.ruby.Directory_Controller.GETX 209 0.00% 0.00% system.ruby.Directory_Controller.GETS 1013 0.00% 0.00% @@ -773,7 +772,7 @@ system.ruby.L1Cache_Controller.S.Ifetch 331 0.00% 0.00% system.ruby.L1Cache_Controller.S.Store 21 0.00% 0.00% system.ruby.L1Cache_Controller.S.L1_Replacement 142 0.00% 0.00% system.ruby.L1Cache_Controller.M.Load 184 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 3298 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 3297 0.00% 0.00% system.ruby.L1Cache_Controller.M.Store 32 0.00% 0.00% system.ruby.L1Cache_Controller.M.L1_Replacement 944 0.00% 0.00% system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock 9 0.00% 0.00% @@ -782,7 +781,7 @@ system.ruby.L1Cache_Controller.MM.Store 330 0.00% 0.00% system.ruby.L1Cache_Controller.MM.L1_Replacement 268 0.00% 0.00% system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock 1 0.00% 0.00% system.ruby.L1Cache_Controller.M_W.Load 80 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Ifetch 2125 0.00% 0.00% +system.ruby.L1Cache_Controller.M_W.Ifetch 2126 0.00% 0.00% system.ruby.L1Cache_Controller.M_W.Store 25 0.00% 0.00% system.ruby.L1Cache_Controller.M_W.L1_Replacement 6 0.00% 0.00% system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 982 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index 4d5f2d93a..3b710633b 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000096 # Number of seconds simulated -sim_ticks 96381 # Number of ticks simulated -final_tick 96381 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 96151 # Number of ticks simulated +final_tick 96151 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 66831 # Simulator instruction rate (inst/s) -host_op_rate 66821 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1007748 # Simulator tick rate (ticks/s) -host_mem_usage 449612 # Number of bytes of host memory used +host_inst_rate 62758 # Simulator instruction rate (inst/s) +host_op_rate 62749 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 944082 # Simulator tick rate (ticks/s) +host_mem_usage 451988 # Number of bytes of host memory used host_seconds 0.10 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated @@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1159 # system.mem_ctrls.num_reads::total 1159 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 220 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 220 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 769612268 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 769612268 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 146086884 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 146086884 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 915699152 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 915699152 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 771453235 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 771453235 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 146436335 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 146436335 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 917889570 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 917889570 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1159 # Number of read requests accepted system.mem_ctrls.writeReqs 220 # Number of write requests accepted system.mem_ctrls.readBursts 1159 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 220 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 64192 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 9984 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 5568 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 63936 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 10240 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 5504 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 74176 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 14080 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 156 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.servicedByWrQ 160 # Number of DRAM read bursts serviced by the write queue system.mem_ctrls.mergedWrBursts 104 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 86 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 52 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 82 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 77 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 96 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 98 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 18 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 59 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 54 # Per bank write bursts system.mem_ctrls.perBankRdBursts::11 47 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 22 # Per bank write bursts system.mem_ctrls.perBankRdBursts::13 358 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 61 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 60 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 40 # Per bank write bursts system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 21 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 2 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 23 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 5 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 18 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 43 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 17 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 41 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 96301 # Total gap between requests +system.mem_ctrls.totGap 96071 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 220 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 1003 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 999 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -136,7 +136,7 @@ system.mem_ctrls.wrQLenPdf::12 1 # Wh system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::15 4 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 4 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::17 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see @@ -149,7 +149,7 @@ system.mem_ctrls.wrQLenPdf::25 6 # Wh system.mem_ctrls.wrQLenPdf::26 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::27 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::28 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::30 5 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::31 5 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::32 5 # What write queue length does an incoming req see @@ -184,87 +184,86 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 194 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 352.659794 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 217.534506 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 333.874690 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 55 28.35% 28.35% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 50 25.77% 54.12% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 18 9.28% 63.40% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 17 8.76% 72.16% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 12 6.19% 78.35% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 7 3.61% 81.96% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 7 3.61% 85.57% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 5 2.58% 88.14% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 23 11.86% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 194 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 191 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 356.858639 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 222.990773 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 333.933268 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 49 25.65% 25.65% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 54 28.27% 53.93% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 20 10.47% 64.40% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 14 7.33% 71.73% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 12 6.28% 78.01% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 7 3.66% 81.68% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 8 4.19% 85.86% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 4 2.09% 87.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 23 12.04% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 191 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 140 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 105.715654 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 81.473922 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 140.600000 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 106.599883 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 79.767161 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::120-127 1 20.00% 40.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::128-135 1 20.00% 60.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::208-215 1 20.00% 80.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::136-143 1 20.00% 60.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::200-207 1 20.00% 80.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 17.400000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 17.358321 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.341641 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 17.200000 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 17.171629 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.095445 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::16 2 40.00% 40.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 2 40.00% 80.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 1 20.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 3 60.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 6850 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 25907 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 5015 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 6.83 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 6736 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 25717 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 4995 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 6.74 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 25.83 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 666.02 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 57.77 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 769.61 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 146.09 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 25.74 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 664.95 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 57.24 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 771.45 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 146.44 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 5.65 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 5.20 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtil 5.64 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 5.19 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.45 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 21.24 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 808 # Number of row buffer hits during reads +system.mem_ctrls.avgWrQLen 21.88 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 806 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 82 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 80.56 # Row buffer hit rate for reads +system.mem_ctrls.readRowHitRate 80.68 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 70.69 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 69.83 # Average gap between requests -system.mem_ctrls.pageHitRate 79.54 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 476280 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 264600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 5104320 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 238464 # Energy for write commands per rank (pJ) +system.mem_ctrls.avgGap 69.67 # Average gap between requests +system.mem_ctrls.pageHitRate 79.64 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 483840 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 268800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5129280 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 290304 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 54887580 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 8068200 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 75142164 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 802.012594 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 14237 # Time in different power states +system.mem_ctrls_0.actBackEnergy 54680328 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 8250000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 75205272 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 802.686163 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 14296 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 3120 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 77447 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 77144 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 975240 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 541800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 7063680 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 663552 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.actEnergy 945000 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 525000 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 7026240 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 601344 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 61908840 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 1909200 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 79165032 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 844.949750 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 2762 # Time in different power states +system.mem_ctrls_1.actBackEnergy 61762464 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 2037600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 79000368 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 843.192247 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 2976 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 3120 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 87824 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 87610 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -300,7 +299,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 96381 # number of cpu cycles simulated +system.cpu.numCycles 96151 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6390 # Number of instructions committed @@ -319,7 +318,7 @@ system.cpu.num_mem_refs 2058 # nu system.cpu.num_load_insts 1190 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 96381 # Number of busy cycles +system.cpu.num_busy_cycles 96151 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched @@ -369,10 +368,10 @@ system.ruby.outstanding_req_hist::total 8449 system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8448 -system.ruby.latency_hist::mean 10.408736 -system.ruby.latency_hist::gmean 3.320047 -system.ruby.latency_hist::stdev 22.995606 -system.ruby.latency_hist | 8209 97.17% 97.17% | 227 2.69% 99.86% | 0 0.00% 99.86% | 0 0.00% 99.86% | 7 0.08% 99.94% | 5 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::mean 10.381510 +system.ruby.latency_hist::gmean 3.318518 +system.ruby.latency_hist::stdev 22.902466 +system.ruby.latency_hist | 8210 97.18% 97.18% | 226 2.68% 99.86% | 0 0.00% 99.86% | 0 0.00% 99.86% | 7 0.08% 99.94% | 5 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8448 system.ruby.hit_latency_hist::bucket_size 2 system.ruby.hit_latency_hist::max_bucket 19 @@ -385,10 +384,10 @@ system.ruby.hit_latency_hist::total 7289 system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1159 -system.ruby.miss_latency_hist::mean 61.364970 -system.ruby.miss_latency_hist::gmean 57.952099 -system.ruby.miss_latency_hist::stdev 28.717200 -system.ruby.miss_latency_hist | 920 79.38% 79.38% | 227 19.59% 98.96% | 0 0.00% 98.96% | 0 0.00% 98.96% | 7 0.60% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::mean 61.166523 +system.ruby.miss_latency_hist::gmean 57.757809 +system.ruby.miss_latency_hist::stdev 28.525461 +system.ruby.miss_latency_hist | 921 79.47% 79.47% | 226 19.50% 98.96% | 0 0.00% 98.96% | 0 0.00% 98.96% | 7 0.60% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1159 system.ruby.Directory.incomplete_times 1158 system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits @@ -404,7 +403,7 @@ system.ruby.l1_cntrl0.L2cache.demand_hits 203 # N system.ruby.l1_cntrl0.L2cache.demand_misses 1159 # Number of cache demand misses system.ruby.l1_cntrl0.L2cache.demand_accesses 1362 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 4.652888 +system.ruby.network.routers0.percent_links_utilized 4.664018 system.ruby.network.routers0.msg_count.Request_Control::2 1159 system.ruby.network.routers0.msg_count.Response_Data::4 1159 system.ruby.network.routers0.msg_count.Writeback_Data::5 220 @@ -419,7 +418,7 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::2 9144 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 9144 system.ruby.network.routers0.msg_bytes.Writeback_Control::5 7384 system.ruby.network.routers0.msg_bytes.Unblock_Control::5 9272 -system.ruby.network.routers1.percent_links_utilized 4.652888 +system.ruby.network.routers1.percent_links_utilized 4.664018 system.ruby.network.routers1.msg_count.Request_Control::2 1159 system.ruby.network.routers1.msg_count.Response_Data::4 1159 system.ruby.network.routers1.msg_count.Writeback_Data::5 220 @@ -434,7 +433,7 @@ system.ruby.network.routers1.msg_bytes.Writeback_Control::2 9144 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 9144 system.ruby.network.routers1.msg_bytes.Writeback_Control::5 7384 system.ruby.network.routers1.msg_bytes.Unblock_Control::5 9272 -system.ruby.network.routers2.percent_links_utilized 4.652888 +system.ruby.network.routers2.percent_links_utilized 4.664018 system.ruby.network.routers2.msg_count.Request_Control::2 1159 system.ruby.network.routers2.msg_count.Response_Data::4 1159 system.ruby.network.routers2.msg_count.Writeback_Data::5 220 @@ -459,12 +458,12 @@ system.ruby.network.msg_byte.Response_Data 250344 system.ruby.network.msg_byte.Writeback_Data 47520 system.ruby.network.msg_byte.Writeback_Control 77016 system.ruby.network.msg_byte.Unblock_Control 27816 -system.ruby.network.routers0.throttle0.link_utilization 6.004295 +system.ruby.network.routers0.throttle0.link_utilization 6.018658 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1159 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1143 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 83448 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 9144 -system.ruby.network.routers0.throttle1.link_utilization 3.301481 +system.ruby.network.routers0.throttle1.link_utilization 3.309378 system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 1159 system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 220 system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 1143 @@ -475,7 +474,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 15840 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 9144 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 7384 system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 9272 -system.ruby.network.routers1.throttle0.link_utilization 3.301481 +system.ruby.network.routers1.throttle0.link_utilization 3.309378 system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 1159 system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5 220 system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 1143 @@ -486,17 +485,17 @@ system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5 15840 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 9144 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 7384 system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 9272 -system.ruby.network.routers1.throttle1.link_utilization 6.004295 +system.ruby.network.routers1.throttle1.link_utilization 6.018658 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1159 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1143 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 83448 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 9144 -system.ruby.network.routers2.throttle0.link_utilization 6.004295 +system.ruby.network.routers2.throttle0.link_utilization 6.018658 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1159 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1143 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 83448 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 9144 -system.ruby.network.routers2.throttle1.link_utilization 3.301481 +system.ruby.network.routers2.throttle1.link_utilization 3.309378 system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 1159 system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 220 system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 1143 @@ -507,13 +506,13 @@ system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 15840 system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 9144 system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 7384 system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 9272 -system.ruby.LD.latency_hist::bucket_size 32 -system.ruby.LD.latency_hist::max_bucket 319 +system.ruby.LD.latency_hist::bucket_size 64 +system.ruby.LD.latency_hist::max_bucket 639 system.ruby.LD.latency_hist::samples 1183 -system.ruby.LD.latency_hist::mean 22.819949 -system.ruby.LD.latency_hist::gmean 7.633765 -system.ruby.LD.latency_hist::stdev 29.454181 -system.ruby.LD.latency_hist | 845 71.43% 71.43% | 248 20.96% 92.39% | 86 7.27% 99.66% | 2 0.17% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::mean 22.845309 +system.ruby.LD.latency_hist::gmean 7.610394 +system.ruby.LD.latency_hist::stdev 30.590449 +system.ruby.LD.latency_hist | 1093 92.39% 92.39% | 87 7.35% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 2 0.17% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist::total 1183 system.ruby.LD.hit_latency_hist::bucket_size 2 system.ruby.LD.hit_latency_hist::max_bucket 19 @@ -523,21 +522,21 @@ system.ruby.LD.hit_latency_hist::gmean 2.587610 system.ruby.LD.hit_latency_hist::stdev 3.791932 system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 658 86.24% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 105 13.76% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.hit_latency_hist::total 763 -system.ruby.LD.miss_latency_hist::bucket_size 32 -system.ruby.LD.miss_latency_hist::max_bucket 319 +system.ruby.LD.miss_latency_hist::bucket_size 64 +system.ruby.LD.miss_latency_hist::max_bucket 639 system.ruby.LD.miss_latency_hist::samples 420 -system.ruby.LD.miss_latency_hist::mean 57.892857 -system.ruby.LD.miss_latency_hist::gmean 54.485563 -system.ruby.LD.miss_latency_hist::stdev 22.570398 -system.ruby.LD.miss_latency_hist | 82 19.52% 19.52% | 248 59.05% 78.57% | 86 20.48% 99.05% | 2 0.48% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 2 0.48% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::mean 57.964286 +system.ruby.LD.miss_latency_hist::gmean 54.017024 +system.ruby.LD.miss_latency_hist::stdev 26.398202 +system.ruby.LD.miss_latency_hist | 330 78.57% 78.57% | 87 20.71% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 2 0.48% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 420 system.ruby.ST.latency_hist::bucket_size 16 system.ruby.ST.latency_hist::max_bucket 159 system.ruby.ST.latency_hist::samples 865 -system.ruby.ST.latency_hist::mean 11.716763 -system.ruby.ST.latency_hist::gmean 3.868197 -system.ruby.ST.latency_hist::stdev 20.732802 -system.ruby.ST.latency_hist | 707 81.73% 81.73% | 44 5.09% 86.82% | 0 0.00% 86.82% | 74 8.55% 95.38% | 36 4.16% 99.54% | 4 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::mean 11.801156 +system.ruby.ST.latency_hist::gmean 3.876538 +system.ruby.ST.latency_hist::stdev 20.845047 +system.ruby.ST.latency_hist | 707 81.73% 81.73% | 41 4.74% 86.47% | 0 0.00% 86.47% | 78 9.02% 95.49% | 35 4.05% 99.54% | 4 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist::total 865 system.ruby.ST.hit_latency_hist::bucket_size 2 system.ruby.ST.hit_latency_hist::max_bucket 19 @@ -550,18 +549,18 @@ system.ruby.ST.hit_latency_hist::total 707 system.ruby.ST.miss_latency_hist::bucket_size 16 system.ruby.ST.miss_latency_hist::max_bucket 159 system.ruby.ST.miss_latency_hist::samples 158 -system.ruby.ST.miss_latency_hist::mean 52.898734 -system.ruby.ST.miss_latency_hist::gmean 50.075344 -system.ruby.ST.miss_latency_hist::stdev 15.909453 -system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 44 27.85% 27.85% | 0 0.00% 27.85% | 74 46.84% 74.68% | 36 22.78% 97.47% | 4 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::mean 53.360759 +system.ruby.ST.miss_latency_hist::gmean 50.669354 +system.ruby.ST.miss_latency_hist::stdev 15.502298 +system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 41 25.95% 25.95% | 0 0.00% 25.95% | 78 49.37% 75.32% | 35 22.15% 97.47% | 4 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 158 system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6400 -system.ruby.IFETCH.latency_hist::mean 7.937812 -system.ruby.IFETCH.latency_hist::gmean 2.788278 -system.ruby.IFETCH.latency_hist::stdev 21.093490 -system.ruby.IFETCH.latency_hist | 6291 98.30% 98.30% | 99 1.55% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 5 0.08% 99.92% | 5 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::mean 7.885781 +system.ruby.IFETCH.latency_hist::gmean 2.787351 +system.ruby.IFETCH.latency_hist::stdev 20.631367 +system.ruby.IFETCH.latency_hist | 6291 98.30% 98.30% | 100 1.56% 99.86% | 0 0.00% 99.86% | 0 0.00% 99.86% | 5 0.08% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6400 system.ruby.IFETCH.hit_latency_hist::bucket_size 2 system.ruby.IFETCH.hit_latency_hist::max_bucket 19 @@ -574,10 +573,10 @@ system.ruby.IFETCH.hit_latency_hist::total 5819 system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 581 -system.ruby.IFETCH.miss_latency_hist::mean 66.177281 -system.ruby.IFETCH.miss_latency_hist::gmean 63.050334 -system.ruby.IFETCH.miss_latency_hist::stdev 34.037169 -system.ruby.IFETCH.miss_latency_hist | 472 81.24% 81.24% | 99 17.04% 98.28% | 0 0.00% 98.28% | 0 0.00% 98.28% | 5 0.86% 99.14% | 5 0.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::mean 65.604131 +system.ruby.IFETCH.miss_latency_hist::gmean 62.819819 +system.ruby.IFETCH.miss_latency_hist::stdev 31.817772 +system.ruby.IFETCH.miss_latency_hist | 472 81.24% 81.24% | 100 17.21% 98.45% | 0 0.00% 98.45% | 0 0.00% 98.45% | 5 0.86% 99.31% | 4 0.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 581 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9 @@ -596,10 +595,10 @@ system.ruby.L2Cache.hit_mach_latency_hist::total 203 system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1159 -system.ruby.Directory.miss_mach_latency_hist::mean 61.364970 -system.ruby.Directory.miss_mach_latency_hist::gmean 57.952099 -system.ruby.Directory.miss_mach_latency_hist::stdev 28.717200 -system.ruby.Directory.miss_mach_latency_hist | 920 79.38% 79.38% | 227 19.59% 98.96% | 0 0.00% 98.96% | 0 0.00% 98.96% | 7 0.60% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::mean 61.166523 +system.ruby.Directory.miss_mach_latency_hist::gmean 57.757809 +system.ruby.Directory.miss_mach_latency_hist::stdev 28.525461 +system.ruby.Directory.miss_mach_latency_hist | 921 79.47% 79.47% | 226 19.50% 98.96% | 0 0.00% 98.96% | 0 0.00% 98.96% | 7 0.60% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1159 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 @@ -641,13 +640,13 @@ system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 13 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 13.000000 system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 105 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 105 -system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32 -system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319 +system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 420 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 57.892857 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 54.485563 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 22.570398 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 82 19.52% 19.52% | 248 59.05% 78.57% | 86 20.48% 99.05% | 2 0.48% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 2 0.48% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 57.964286 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 54.017024 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 26.398202 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 330 78.57% 78.57% | 87 20.71% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 2 0.48% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 420 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9 @@ -666,10 +665,10 @@ system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 33 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 16 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 159 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 158 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 52.898734 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 50.075344 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 15.909453 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 44 27.85% 27.85% | 0 0.00% 27.85% | 74 46.84% 74.68% | 36 22.78% 97.47% | 4 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 53.360759 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 50.669354 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 15.502298 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 41 25.95% 25.95% | 0 0.00% 25.95% | 78 49.37% 75.32% | 35 22.15% 97.47% | 4 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist::total 158 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist::max_bucket 9 @@ -688,10 +687,10 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist::total 65 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 581 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 66.177281 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 63.050334 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.037169 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 472 81.24% 81.24% | 99 17.04% 98.28% | 0 0.00% 98.28% | 0 0.00% 98.28% | 5 0.86% 99.14% | 5 0.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 65.604131 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 62.819819 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 31.817772 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 472 81.24% 81.24% | 100 17.21% 98.45% | 0 0.00% 98.45% | 0 0.00% 98.45% | 5 0.86% 99.31% | 4 0.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 581 system.ruby.Directory_Controller.GETX 185 0.00% 0.00% system.ruby.Directory_Controller.GETS 1020 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index e18c35fff..8d98e090f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000124 # Number of seconds simulated -sim_ticks 123564 # Number of ticks simulated -final_tick 123564 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 123531 # Number of ticks simulated +final_tick 123531 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 69668 # Simulator instruction rate (inst/s) -host_op_rate 69633 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1346306 # Simulator tick rate (ticks/s) -host_mem_usage 450680 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 63521 # Simulator instruction rate (inst/s) +host_op_rate 63513 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1227662 # Simulator tick rate (ticks/s) +host_mem_usage 451804 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1730 # system.mem_ctrls.num_reads::total 1730 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 1726 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 1726 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 896053867 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 896053867 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 893982066 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 893982066 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1790035933 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1790035933 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 896293238 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 896293238 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 894220884 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 894220884 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1790514122 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1790514122 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1730 # Number of read requests accepted system.mem_ctrls.writeReqs 1726 # Number of write requests accepted system.mem_ctrls.readBursts 1730 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 1726 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 56704 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 54016 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 57536 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 56832 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 53888 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 56512 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 110720 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 110464 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 844 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 803 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 842 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 814 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 85 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 44 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 71 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 65 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 112 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 22 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 82 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 51 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 81 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 66 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 118 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 25 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 55 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 32 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 20 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 276 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 80 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 19 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 84 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 44 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 73 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 62 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 130 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 23 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 52 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 33 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 18 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 264 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 73 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 20 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 81 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 51 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 85 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 63 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 127 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 25 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 3 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 53 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 48 # Per bank write bursts system.mem_ctrls.perBankWrBursts::11 32 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 15 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 277 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 81 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 12 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 260 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 74 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 20 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 123476 # Total gap between requests +system.mem_ctrls.totGap 123443 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 1726 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 886 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 888 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -135,24 +135,24 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 7 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 9 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::16 12 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 52 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 59 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 56 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 51 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 55 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 55 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::24 55 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::25 55 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::26 55 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::27 55 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::28 55 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 55 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 55 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 55 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 55 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 54 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 54 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 54 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 54 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -184,87 +184,88 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 258 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 429.147287 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 269.046347 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 361.589640 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 63 24.42% 24.42% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 51 19.77% 44.19% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 24 9.30% 53.49% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 27 10.47% 63.95% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 14 5.43% 69.38% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 11 4.26% 73.64% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 12 4.65% 78.29% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 14 5.43% 83.72% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 42 16.28% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 258 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 55 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 15.927273 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.760356 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 2.949291 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 29 52.73% 52.73% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 21 38.18% 90.91% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 4 7.27% 98.18% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::36-37 1 1.82% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 55 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 55 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.345455 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.329469 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.750757 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 44 80.00% 80.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 4 7.27% 87.27% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 6 10.91% 98.18% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 1 1.82% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 55 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 10464 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 27298 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 4430 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 11.81 # Average queueing delay per DRAM burst +system.mem_ctrls.bytesPerActivate::samples 268 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 416.477612 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 263.436899 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 359.508293 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 60 22.39% 22.39% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 57 21.27% 43.66% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 40 14.93% 58.58% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 20 7.46% 66.04% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 10 3.73% 69.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 14 5.22% 75.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 11 4.10% 79.10% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 12 4.48% 83.58% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 44 16.42% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 268 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 54 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 16.203704 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.997541 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 3.176444 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 2 3.70% 3.70% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 22 40.74% 44.44% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 22 40.74% 85.19% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 6 11.11% 96.30% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::22-23 1 1.85% 98.15% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 1.85% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 54 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 54 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.351852 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.333537 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.804642 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 45 83.33% 83.33% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 8 14.81% 98.15% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 1 1.85% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 54 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 10373 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 27245 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 4440 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 11.68 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 30.81 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 458.90 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 465.64 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 896.05 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 893.98 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 30.68 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 460.06 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 457.47 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 896.29 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 894.22 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 7.22 # Data bus utilization in percentage +system.mem_ctrls.busUtil 7.17 # Data bus utilization in percentage system.mem_ctrls.busUtilRead 3.59 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 3.64 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtilWrite 3.57 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 26.06 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 665 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 854 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 75.06 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 92.52 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 35.73 # Average gap between requests -system.mem_ctrls.pageHitRate 83.97 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 771120 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 428400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 4879680 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 4281984 # Energy for write commands per rank (pJ) +system.mem_ctrls.avgWrQLen 25.91 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 672 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 824 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 75.68 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 90.35 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 35.72 # Average gap between requests +system.mem_ctrls.pageHitRate 83.11 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 824040 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 457800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5229120 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 4520448 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 69480720 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 9282000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 96752304 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 826.589526 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 15125 # Time in different power states +system.mem_ctrls_0.actBackEnergy 66802176 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 11631600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 97093584 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 829.505203 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 19845 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 3900 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 98100 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 94170 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 1081080 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 600600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 5466240 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 4323456 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.actEnergy 1118880 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 621600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 5191680 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 4136832 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 69027912 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 9680400 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 97808088 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 835.595188 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 15368 # Time in different power states +system.mem_ctrls_1.actBackEnergy 69356232 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 9391800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 97445424 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 832.503985 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 15122 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 3900 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 97798 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 98043 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -300,7 +301,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 123564 # number of cpu cycles simulated +system.cpu.numCycles 123531 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6390 # Number of instructions committed @@ -319,7 +320,7 @@ system.cpu.num_mem_refs 2058 # nu system.cpu.num_load_insts 1190 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 123564 # Number of busy cycles +system.cpu.num_busy_cycles 123531 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched @@ -374,10 +375,10 @@ system.ruby.outstanding_req_hist::total 8449 system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8448 -system.ruby.latency_hist::mean 13.626420 -system.ruby.latency_hist::gmean 5.329740 -system.ruby.latency_hist::stdev 25.242996 -system.ruby.latency_hist | 8195 97.01% 97.01% | 199 2.36% 99.36% | 43 0.51% 99.87% | 2 0.02% 99.89% | 5 0.06% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::mean 13.622514 +system.ruby.latency_hist::gmean 5.329433 +system.ruby.latency_hist::stdev 25.311843 +system.ruby.latency_hist | 8197 97.03% 97.03% | 202 2.39% 99.42% | 36 0.43% 99.85% | 3 0.04% 99.88% | 8 0.09% 99.98% | 1 0.01% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8448 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 @@ -389,17 +390,17 @@ system.ruby.hit_latency_hist::total 6718 system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1730 -system.ruby.miss_latency_hist::mean 54.891329 -system.ruby.miss_latency_hist::gmean 49.648144 -system.ruby.miss_latency_hist::stdev 31.153546 -system.ruby.miss_latency_hist | 1477 85.38% 85.38% | 199 11.50% 96.88% | 43 2.49% 99.36% | 2 0.12% 99.48% | 5 0.29% 99.77% | 4 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::mean 54.872254 +system.ruby.miss_latency_hist::gmean 49.634160 +system.ruby.miss_latency_hist::stdev 31.450318 +system.ruby.miss_latency_hist | 1479 85.49% 85.49% | 202 11.68% 97.17% | 36 2.08% 99.25% | 3 0.17% 99.42% | 8 0.46% 99.88% | 1 0.06% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1730 system.ruby.Directory.incomplete_times 1729 system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.992328 +system.ruby.network.routers0.percent_links_utilized 6.994196 system.ruby.network.routers0.msg_count.Control::2 1730 system.ruby.network.routers0.msg_count.Data::2 1726 system.ruby.network.routers0.msg_count.Response_Data::4 1730 @@ -408,7 +409,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 13840 system.ruby.network.routers0.msg_bytes.Data::2 124272 system.ruby.network.routers0.msg_bytes.Response_Data::4 124560 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.routers1.percent_links_utilized 6.992328 +system.ruby.network.routers1.percent_links_utilized 6.994196 system.ruby.network.routers1.msg_count.Control::2 1730 system.ruby.network.routers1.msg_count.Data::2 1726 system.ruby.network.routers1.msg_count.Response_Data::4 1730 @@ -417,7 +418,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 13840 system.ruby.network.routers1.msg_bytes.Data::2 124272 system.ruby.network.routers1.msg_bytes.Response_Data::4 124560 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.routers2.percent_links_utilized 6.992328 +system.ruby.network.routers2.percent_links_utilized 6.994196 system.ruby.network.routers2.msg_count.Control::2 1730 system.ruby.network.routers2.msg_count.Data::2 1726 system.ruby.network.routers2.msg_count.Response_Data::4 1730 @@ -434,32 +435,32 @@ system.ruby.network.msg_byte.Control 41520 system.ruby.network.msg_byte.Data 372816 system.ruby.network.msg_byte.Response_Data 373680 system.ruby.network.msg_byte.Writeback_Control 41424 -system.ruby.network.routers0.throttle0.link_utilization 6.998802 +system.ruby.network.routers0.throttle0.link_utilization 7.000672 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1730 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1726 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 124560 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.routers0.throttle1.link_utilization 6.985853 +system.ruby.network.routers0.throttle1.link_utilization 6.987720 system.ruby.network.routers0.throttle1.msg_count.Control::2 1730 system.ruby.network.routers0.throttle1.msg_count.Data::2 1726 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 13840 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 124272 -system.ruby.network.routers1.throttle0.link_utilization 6.985853 +system.ruby.network.routers1.throttle0.link_utilization 6.987720 system.ruby.network.routers1.throttle0.msg_count.Control::2 1730 system.ruby.network.routers1.throttle0.msg_count.Data::2 1726 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 13840 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 124272 -system.ruby.network.routers1.throttle1.link_utilization 6.998802 +system.ruby.network.routers1.throttle1.link_utilization 7.000672 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1730 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1726 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 124560 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.routers2.throttle0.link_utilization 6.998802 +system.ruby.network.routers2.throttle0.link_utilization 7.000672 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1730 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1726 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 124560 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.routers2.throttle1.link_utilization 6.985853 +system.ruby.network.routers2.throttle1.link_utilization 6.987720 system.ruby.network.routers2.throttle1.msg_count.Control::2 1730 system.ruby.network.routers2.throttle1.msg_count.Data::2 1726 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 13840 @@ -477,10 +478,10 @@ system.ruby.delayVCHist.vnet_2::total 1726 # de system.ruby.LD.latency_hist::bucket_size 64 system.ruby.LD.latency_hist::max_bucket 639 system.ruby.LD.latency_hist::samples 1183 -system.ruby.LD.latency_hist::mean 33.711750 -system.ruby.LD.latency_hist::gmean 16.462445 -system.ruby.LD.latency_hist::stdev 33.973523 -system.ruby.LD.latency_hist | 1077 91.04% 91.04% | 86 7.27% 98.31% | 15 1.27% 99.58% | 2 0.17% 99.75% | 2 0.17% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::mean 32.793745 +system.ruby.LD.latency_hist::gmean 16.273400 +system.ruby.LD.latency_hist::stdev 32.397171 +system.ruby.LD.latency_hist | 1086 91.80% 91.80% | 85 7.19% 98.99% | 8 0.68% 99.66% | 1 0.08% 99.75% | 2 0.17% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist::total 1183 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 @@ -492,18 +493,18 @@ system.ruby.LD.hit_latency_hist::total 456 system.ruby.LD.miss_latency_hist::bucket_size 64 system.ruby.LD.miss_latency_hist::max_bucket 639 system.ruby.LD.miss_latency_hist::samples 727 -system.ruby.LD.miss_latency_hist::mean 52.975241 -system.ruby.LD.miss_latency_hist::gmean 47.891138 -system.ruby.LD.miss_latency_hist::stdev 30.251097 -system.ruby.LD.miss_latency_hist | 621 85.42% 85.42% | 86 11.83% 97.25% | 15 2.06% 99.31% | 2 0.28% 99.59% | 2 0.28% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::mean 51.481431 +system.ruby.LD.miss_latency_hist::gmean 46.999464 +system.ruby.LD.miss_latency_hist::stdev 28.311858 +system.ruby.LD.miss_latency_hist | 630 86.66% 86.66% | 85 11.69% 98.35% | 8 1.10% 99.45% | 1 0.14% 99.59% | 2 0.28% 99.86% | 0 0.00% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 727 system.ruby.ST.latency_hist::bucket_size 64 system.ruby.ST.latency_hist::max_bucket 639 system.ruby.ST.latency_hist::samples 865 -system.ruby.ST.latency_hist::mean 18.557225 -system.ruby.ST.latency_hist::gmean 7.162336 -system.ruby.ST.latency_hist::stdev 28.547301 -system.ruby.ST.latency_hist | 834 96.42% 96.42% | 21 2.43% 98.84% | 9 1.04% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::mean 18.649711 +system.ruby.ST.latency_hist::gmean 7.153271 +system.ruby.ST.latency_hist::stdev 30.101235 +system.ruby.ST.latency_hist | 832 96.18% 96.18% | 24 2.77% 98.96% | 6 0.69% 99.65% | 1 0.12% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist::total 865 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 @@ -515,18 +516,18 @@ system.ruby.ST.hit_latency_hist::total 592 system.ruby.ST.miss_latency_hist::bucket_size 64 system.ruby.ST.miss_latency_hist::max_bucket 639 system.ruby.ST.miss_latency_hist::samples 273 -system.ruby.ST.miss_latency_hist::mean 52.293040 -system.ruby.ST.miss_latency_hist::gmean 47.271858 -system.ruby.ST.miss_latency_hist::stdev 30.324989 -system.ruby.ST.miss_latency_hist | 242 88.64% 88.64% | 21 7.69% 96.34% | 9 3.30% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::mean 52.586081 +system.ruby.ST.miss_latency_hist::gmean 47.082552 +system.ruby.ST.miss_latency_hist::stdev 34.484663 +system.ruby.ST.miss_latency_hist | 240 87.91% 87.91% | 24 8.79% 96.70% | 6 2.20% 98.90% | 1 0.37% 99.27% | 1 0.37% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 273 -system.ruby.IFETCH.latency_hist::bucket_size 64 -system.ruby.IFETCH.latency_hist::max_bucket 639 +system.ruby.IFETCH.latency_hist::bucket_size 32 +system.ruby.IFETCH.latency_hist::max_bucket 319 system.ruby.IFETCH.latency_hist::samples 6400 -system.ruby.IFETCH.latency_hist::mean 9.247344 -system.ruby.IFETCH.latency_hist::gmean 4.157427 -system.ruby.IFETCH.latency_hist::stdev 20.515003 -system.ruby.IFETCH.latency_hist | 6284 98.19% 98.19% | 92 1.44% 99.63% | 19 0.30% 99.92% | 0 0.00% 99.92% | 3 0.05% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::mean 9.399375 +system.ruby.IFETCH.latency_hist::gmean 4.166708 +system.ruby.IFETCH.latency_hist::stdev 20.983950 +system.ruby.IFETCH.latency_hist | 5670 88.59% 88.59% | 609 9.52% 98.11% | 88 1.38% 99.48% | 5 0.08% 99.56% | 5 0.08% 99.64% | 17 0.27% 99.91% | 1 0.02% 99.92% | 0 0.00% 99.92% | 1 0.02% 99.94% | 4 0.06% 100.00% system.ruby.IFETCH.latency_hist::total 6400 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 @@ -535,21 +536,21 @@ system.ruby.IFETCH.hit_latency_hist::mean 3 system.ruby.IFETCH.hit_latency_hist::gmean 3.000000 system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5670 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.hit_latency_hist::total 5670 -system.ruby.IFETCH.miss_latency_hist::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist::bucket_size 32 +system.ruby.IFETCH.miss_latency_hist::max_bucket 319 system.ruby.IFETCH.miss_latency_hist::samples 730 -system.ruby.IFETCH.miss_latency_hist::mean 57.771233 -system.ruby.IFETCH.miss_latency_hist::gmean 52.414605 -system.ruby.IFETCH.miss_latency_hist::stdev 32.138819 -system.ruby.IFETCH.miss_latency_hist | 614 84.11% 84.11% | 92 12.60% 96.71% | 19 2.60% 99.32% | 0 0.00% 99.32% | 3 0.41% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::mean 59.104110 +system.ruby.IFETCH.miss_latency_hist::gmean 53.449398 +system.ruby.IFETCH.miss_latency_hist::stdev 32.750880 +system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 609 83.42% 83.42% | 88 12.05% 95.48% | 5 0.68% 96.16% | 5 0.68% 96.85% | 17 2.33% 99.18% | 1 0.14% 99.32% | 0 0.00% 99.32% | 1 0.14% 99.45% | 4 0.55% 100.00% system.ruby.IFETCH.miss_latency_hist::total 730 system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1730 -system.ruby.Directory.miss_mach_latency_hist::mean 54.891329 -system.ruby.Directory.miss_mach_latency_hist::gmean 49.648144 -system.ruby.Directory.miss_mach_latency_hist::stdev 31.153546 -system.ruby.Directory.miss_mach_latency_hist | 1477 85.38% 85.38% | 199 11.50% 96.88% | 43 2.49% 99.36% | 2 0.12% 99.48% | 5 0.29% 99.77% | 4 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::mean 54.872254 +system.ruby.Directory.miss_mach_latency_hist::gmean 49.634160 +system.ruby.Directory.miss_mach_latency_hist::stdev 31.450318 +system.ruby.Directory.miss_mach_latency_hist | 1479 85.49% 85.49% | 202 11.68% 97.17% | 36 2.08% 99.25% | 3 0.17% 99.42% | 8 0.46% 99.88% | 1 0.06% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1730 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 @@ -580,26 +581,26 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::total system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 727 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 52.975241 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 47.891138 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 30.251097 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 621 85.42% 85.42% | 86 11.83% 97.25% | 15 2.06% 99.31% | 2 0.28% 99.59% | 2 0.28% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 51.481431 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 46.999464 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 28.311858 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 630 86.66% 86.66% | 85 11.69% 98.35% | 8 1.10% 99.45% | 1 0.14% 99.59% | 2 0.28% 99.86% | 0 0.00% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 727 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 273 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 52.293040 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 47.271858 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 30.324989 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 242 88.64% 88.64% | 21 7.69% 96.34% | 9 3.30% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 52.586081 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 47.082552 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 34.484663 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 240 87.91% 87.91% | 24 8.79% 96.70% | 6 2.20% 98.90% | 1 0.37% 99.27% | 1 0.37% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist::total 273 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 32 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 730 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 57.771233 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 52.414605 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 32.138819 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 614 84.11% 84.11% | 92 12.60% 96.71% | 19 2.60% 99.32% | 0 0.00% 99.32% | 3 0.41% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 59.104110 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 53.449398 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 32.750880 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 609 83.42% 83.42% | 88 12.05% 95.48% | 5 0.68% 96.16% | 5 0.68% 96.85% | 17 2.33% 99.18% | 1 0.14% 99.32% | 0 0.00% 99.32% | 1 0.14% 99.45% | 4 0.55% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 730 system.ruby.Directory_Controller.GETX 1730 0.00% 0.00% system.ruby.Directory_Controller.PUTX 1726 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index 95d6f5391..2c1174c59 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000033 # Nu sim_ticks 32544500 # Number of ticks simulated final_tick 32544500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 643051 # Simulator instruction rate (inst/s) -host_op_rate 642147 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3266208350 # Simulator tick rate (ticks/s) -host_mem_usage 291356 # Number of bytes of host memory used +host_inst_rate 619666 # Simulator instruction rate (inst/s) +host_op_rate 618826 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3148046044 # Simulator tick rate (ticks/s) +host_mem_usage 291528 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated @@ -122,14 +122,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6400 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.757933 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.755352 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.757933 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025332 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025332 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.755352 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025331 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025331 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id @@ -200,14 +200,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5082500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5082500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3905500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3905500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8988000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8988000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8988000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8988000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5130000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5130000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3942000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3942000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9072000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9072000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9072000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9072000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -216,24 +216,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 127.992738 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 127.988451 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 127.992738 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.062496 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.062496 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 127.988451 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.062494 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.062494 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id @@ -290,97 +290,102 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 279 system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14885000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14885000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14885000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14885000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14885000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14885000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15024500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15024500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15024500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15024500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15024500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15024500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53351.254480 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53351.254480 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53351.254480 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53351.254480 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53351.254480 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53351.254480 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53851.254480 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53851.254480 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53851.254480 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53851.254480 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53851.254480 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53851.254480 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 184.488660 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 184.465722 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.011543 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.477117 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.994443 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.471279 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003906 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001723 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005629 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011383 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 373 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 278 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 278 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 95 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 95 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14595500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4987500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19583000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3832500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3832500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14595500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 14595500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4987500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4987500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 14595500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 8820000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 23415500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 14595500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 8820000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 23415500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 279 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 374 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 279 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 279 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 95 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 95 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997326 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996416 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.997763 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.340483 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.798561 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52501.121076 # average overall miss latency @@ -395,55 +400,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 373 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 95 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 95 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11259000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3847500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15106500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2956500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2956500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11259000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6804000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18063000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11259000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6804000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18063000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997326 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3102500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3102500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11815500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11815500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4037500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4037500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11815500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7140000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18955500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11815500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7140000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18955500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996416 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.798561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.798561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.121076 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.121076 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 374 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 279 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 95 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 894 # Packet count per connected master and slave (bytes) @@ -468,10 +478,10 @@ system.cpu.toL2Bus.respLayer0.occupancy 418500 # La system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.trans_dist::ReadReq 373 # Transaction distribution system.membus.trans_dist::ReadResp 373 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 373 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index 7408970f9..7c57b2554 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20287000 # Number of ticks simulated -final_tick 20287000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20091000 # Number of ticks simulated +final_tick 20091000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 140405 # Simulator instruction rate (inst/s) -host_op_rate 140306 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1100341704 # Simulator tick rate (ticks/s) -host_mem_usage 292772 # Number of bytes of host memory used +host_inst_rate 125803 # Simulator instruction rate (inst/s) +host_op_rate 125723 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 976523768 # Simulator tick rate (ticks/s) +host_mem_usage 293292 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 14272 # Nu system.physmem.num_reads::cpu.inst 223 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 308 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 703504707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 268152019 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 971656726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 703504707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 703504707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 703504707 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 268152019 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 971656726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 710367826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 270768006 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 981135832 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 710367826 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 710367826 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 710367826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 270768006 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 981135832 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 308 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 308 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20198000 # Total gap between requests +system.physmem.totGap 20003000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 62 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -187,77 +187,77 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 41 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 427.707317 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 281.056415 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.596590 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 430.829268 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 282.802413 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.088769 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 10 24.39% 24.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 6 14.63% 39.02% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 4 9.76% 48.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 2 4.88% 53.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 7 17.07% 70.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 4.88% 75.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 9.76% 85.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 6 14.63% 68.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4 9.76% 78.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 7.32% 85.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 3 7.32% 92.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 3 7.32% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation -system.physmem.totQLat 1763250 # Total ticks spent queuing -system.physmem.totMemAccLat 7538250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1567250 # Total ticks spent queuing +system.physmem.totMemAccLat 7342250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5724.84 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5088.47 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24474.84 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 971.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23838.47 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 981.14 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 971.66 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 981.14 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.59 # Data bus utilization in percentage -system.physmem.busUtilRead 7.59 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.67 # Data bus utilization in percentage +system.physmem.busUtilRead 7.67 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 258 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.77 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 65577.92 # Average gap between requests +system.physmem.avgGap 64944.81 # Average gap between requests system.physmem.pageHitRate 83.77 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 83160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 45375 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 780000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10555830 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 240000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 12721485 # Total energy per rank (pJ) -system.physmem_0.averagePower 803.504500 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 765250 # Time in different power states +system.physmem_0.actBackEnergy 10605420 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 196500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12727575 # Total energy per rank (pJ) +system.physmem_0.averagePower 803.889152 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 536250 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 14968250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15041250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 189000 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1185600 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 1201200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10492560 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 300000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13287405 # Total energy per rank (pJ) -system.physmem_1.averagePower 838.851326 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 458000 # Time in different power states +system.physmem_1.actBackEnergy 10489995 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 299250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13299690 # Total energy per rank (pJ) +system.physmem_1.averagePower 839.892011 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 457000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14875250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14871250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 791 # Number of BP lookups +system.cpu.branchPred.lookups 793 # Number of BP lookups system.cpu.branchPred.condPredicted 397 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 168 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 563 # Number of BTB lookups system.cpu.branchPred.BTBHits 58 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 10.301954 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 136 # Number of times the RAS was used to get a target. +system.cpu.branchPred.usedRAS 138 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -276,10 +276,10 @@ system.cpu.dtb.data_hits 816 # DT system.cpu.dtb.data_misses 13 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations system.cpu.dtb.data_accesses 829 # DTB accesses -system.cpu.itb.fetch_hits 969 # ITB hits +system.cpu.itb.fetch_hits 971 # ITB hits system.cpu.itb.fetch_misses 13 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 982 # ITB accesses +system.cpu.itb.fetch_accesses 984 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,26 +293,26 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 40574 # number of cpu cycles simulated +system.cpu.numCycles 40182 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2585 # Number of instructions committed system.cpu.committedOps 2585 # Number of ops (including micro ops) committed system.cpu.discardedOps 594 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 15.695938 # CPI: cycles per instruction -system.cpu.ipc 0.063711 # IPC: instructions per cycle -system.cpu.tickCycles 5391 # Number of cycles that the object actually ticked -system.cpu.idleCycles 35183 # Total number of cycles that the object has spent stopped +system.cpu.cpi 15.544294 # CPI: cycles per instruction +system.cpu.ipc 0.064332 # IPC: instructions per cycle +system.cpu.tickCycles 5392 # Number of cycles that the object actually ticked +system.cpu.idleCycles 34790 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 48.342007 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 48.329975 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.141176 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 48.342007 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011802 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011802 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 48.329975 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011799 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011799 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id @@ -335,14 +335,14 @@ system.cpu.dcache.demand_misses::cpu.data 104 # n system.cpu.dcache.demand_misses::total 104 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 104 # number of overall misses system.cpu.dcache.overall_misses::total 104 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4962000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4962000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3282500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3282500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8244500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8244500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8244500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8244500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4723000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4723000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3258500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3258500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7981500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7981500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7981500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7981500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 502 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 502 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -359,14 +359,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.130653 system.cpu.dcache.demand_miss_rate::total 0.130653 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.130653 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130653 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81344.262295 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 81344.262295 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76337.209302 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76337.209302 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 79274.038462 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 79274.038462 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 79274.038462 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 79274.038462 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77426.229508 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 77426.229508 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75779.069767 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75779.069767 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76745.192308 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76745.192308 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76745.192308 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76745.192308 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -391,14 +391,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4628250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4628250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2009000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2009000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6637250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6637250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6637250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6637250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4442000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4442000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2017500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2017500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6459500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6459500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6459500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6459500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.115538 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.115538 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses @@ -407,66 +407,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.106784 system.cpu.dcache.demand_mshr_miss_rate::total 0.106784 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.106784 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.106784 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79797.413793 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79797.413793 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74407.407407 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74407.407407 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78085.294118 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78085.294118 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78085.294118 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78085.294118 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76586.206897 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76586.206897 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74722.222222 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74722.222222 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75994.117647 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75994.117647 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75994.117647 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75994.117647 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 117.949271 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 746 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 117.935175 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 748 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 223 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.345291 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.354260 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 117.949271 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057592 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057592 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 117.935175 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057586 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057586 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 223 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2161 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2161 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 746 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 746 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 746 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 746 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 746 # number of overall hits -system.cpu.icache.overall_hits::total 746 # number of overall hits +system.cpu.icache.tags.tag_accesses 2165 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2165 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 748 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 748 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 748 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 748 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 748 # number of overall hits +system.cpu.icache.overall_hits::total 748 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 223 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 223 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 223 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 223 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 223 # number of overall misses system.cpu.icache.overall_misses::total 223 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17117250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17117250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17117250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17117250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17117250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17117250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 969 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 969 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 969 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 969 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 969 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 969 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230134 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.230134 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.230134 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.230134 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.230134 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.230134 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76758.968610 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76758.968610 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76758.968610 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76758.968610 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76758.968610 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76758.968610 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16978500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16978500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16978500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16978500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16978500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16978500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 971 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 971 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 971 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 971 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 971 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 971 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229660 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.229660 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.229660 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.229660 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.229660 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.229660 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76136.771300 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76136.771300 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76136.771300 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76136.771300 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76136.771300 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76136.771300 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,97 +481,102 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 223 system.cpu.icache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 223 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16684250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16684250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16684250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16684250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16684250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16684250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.230134 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.230134 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.230134 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.230134 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.230134 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.230134 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74817.264574 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74817.264574 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74817.264574 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74817.264574 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74817.264574 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74817.264574 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16755500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16755500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16755500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16755500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16755500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16755500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.229660 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.229660 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.229660 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.229660 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.229660 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.229660 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75136.771300 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75136.771300 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75136.771300 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75136.771300 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75136.771300 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75136.771300 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 145.900805 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 145.853573 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 281 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 118.086871 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 27.813934 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003604 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000849 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004453 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 118.051720 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 27.801853 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003603 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000848 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004451 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 281 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008575 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2772 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2772 # Number of data accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 223 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 58 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 281 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 223 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 223 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 58 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 58 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 223 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 308 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 223 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 308 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16461250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4569250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21030500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1982000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1982000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16461250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6551250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23012500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16461250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6551250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23012500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 223 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 58 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 281 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1977000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1977000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16421000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 16421000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4354000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4354000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16421000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6331000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22752000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16421000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6331000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22752000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 223 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 223 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 58 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 58 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 223 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 308 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 223 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 308 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73817.264574 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78780.172414 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74841.637011 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73407.407407 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73407.407407 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73817.264574 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77073.529412 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74715.909091 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73817.264574 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77073.529412 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74715.909091 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73222.222222 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73222.222222 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73636.771300 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73636.771300 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75068.965517 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75068.965517 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73636.771300 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74482.352941 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73870.129870 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73636.771300 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74482.352941 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73870.129870 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -580,55 +585,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 223 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 58 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 281 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 27 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 223 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 223 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 58 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 58 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 223 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 308 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 308 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13669750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3841250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17511000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1642000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1642000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13669750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5483250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19153000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13669750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5483250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19153000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1707000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1707000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14191000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14191000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3774000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3774000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14191000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5481000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19672000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14191000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5481000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19672000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61299.327354 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66228.448276 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62316.725979 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60814.814815 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60814.814815 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61299.327354 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64508.823529 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62185.064935 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61299.327354 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64508.823529 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62185.064935 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63222.222222 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63222.222222 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63636.771300 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63636.771300 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65068.965517 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65068.965517 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63636.771300 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64482.352941 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63870.129870 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63636.771300 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64482.352941 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63870.129870 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 223 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 58 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 446 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 616 # Packet count per connected master and slave (bytes) @@ -649,14 +659,14 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 308 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 154000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 383750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 143250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.trans_dist::ReadReq 281 # Transaction distribution +system.cpu.toL2Bus.respLayer0.occupancy 334500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) system.membus.trans_dist::ReadResp 281 # Transaction distribution system.membus.trans_dist::ReadExReq 27 # Transaction distribution system.membus.trans_dist::ReadExResp 27 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 281 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 616 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 616 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 19712 # Cumulative packet size per connected master and slave (bytes) @@ -672,9 +682,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 308 # Request fanout histogram -system.membus.reqLayer0.occupancy 360000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 359500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 1638500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 8.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 1638750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 8.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 493ed4968..ee80959b5 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 12774000 # Number of ticks simulated -final_tick 12774000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 12591500 # Number of ticks simulated +final_tick 12591500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 38054 # Simulator instruction rate (inst/s) -host_op_rate 38045 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 203548685 # Simulator tick rate (ticks/s) -host_mem_usage 224448 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 74456 # Simulator instruction rate (inst/s) +host_op_rate 74426 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 392441951 # Simulator tick rate (ticks/s) +host_mem_usage 293552 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 11968 # Nu system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 936903084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 425865038 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1362768123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 936903084 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 936903084 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 936903084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 425865038 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1362768123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 950482468 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 432037486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1382519954 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 950482468 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 950482468 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 950482468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 432037486 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1382519954 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 272 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 272 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 12677500 # Total gap between requests +system.physmem.totGap 12495000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -92,8 +92,8 @@ system.physmem.writePktSize::5 0 # Wr system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 156 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 82 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -187,9 +187,9 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 36 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 394.666667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 235.952583 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 357.320824 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 398.222222 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 237.741650 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 358.174986 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 12 33.33% 33.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 5 13.89% 47.22% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 3 8.33% 55.56% # Bytes accessed per row activation @@ -200,37 +200,37 @@ system.physmem.bytesPerActivate::768-895 2 5.56% 83.33% # By system.physmem.bytesPerActivate::896-1023 1 2.78% 86.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 13.89% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 36 # Bytes accessed per row activation -system.physmem.totQLat 1960500 # Total ticks spent queuing -system.physmem.totMemAccLat 7060500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1676750 # Total ticks spent queuing +system.physmem.totMemAccLat 6776750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7207.72 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6164.52 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25957.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1362.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24914.52 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1382.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1362.77 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1382.52 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.65 # Data bus utilization in percentage -system.physmem.busUtilRead 10.65 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.80 # Data bus utilization in percentage +system.physmem.busUtilRead 10.80 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.71 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 226 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 46608.46 # Average gap between requests +system.physmem.avgGap 45937.50 # Average gap between requests system.physmem.pageHitRate 83.09 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 68040 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 37125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 585000 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 592800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 5478840 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 21750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 6699315 # Total energy per rank (pJ) -system.physmem_0.averagePower 832.600901 # Core power per rank (mW) +system.physmem_0.totalEnergy 6707115 # Total energy per rank (pJ) +system.physmem_0.averagePower 833.570297 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states system.physmem_0.memoryStateTime::REF 260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states @@ -238,48 +238,48 @@ system.physmem_0.memoryStateTime::ACT 7777500 # Ti system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 787800 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 5200965 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 265500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 6961470 # Total energy per rank (pJ) -system.physmem_1.averagePower 865.181917 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 428500 # Time in different power states +system.physmem_1.totalEnergy 6969270 # Total energy per rank (pJ) +system.physmem_1.averagePower 866.151313 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 708000 # Time in different power states system.physmem_1.memoryStateTime::REF 260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 7371500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1106 # Number of BP lookups -system.cpu.branchPred.condPredicted 562 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 228 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 735 # Number of BTB lookups -system.cpu.branchPred.BTBHits 214 # Number of BTB hits +system.cpu.branchPred.lookups 1086 # Number of BP lookups +system.cpu.branchPred.condPredicted 546 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 229 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 723 # Number of BTB lookups +system.cpu.branchPred.BTBHits 206 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 29.115646 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 201 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 28.492393 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 197 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 9 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 705 # DTB read hits -system.cpu.dtb.read_misses 25 # DTB read misses +system.cpu.dtb.read_hits 688 # DTB read hits +system.cpu.dtb.read_misses 18 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 730 # DTB read accesses -system.cpu.dtb.write_hits 367 # DTB write hits -system.cpu.dtb.write_misses 19 # DTB write misses +system.cpu.dtb.read_accesses 706 # DTB read accesses +system.cpu.dtb.write_hits 353 # DTB write hits +system.cpu.dtb.write_misses 17 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 386 # DTB write accesses -system.cpu.dtb.data_hits 1072 # DTB hits -system.cpu.dtb.data_misses 44 # DTB misses +system.cpu.dtb.write_accesses 370 # DTB write accesses +system.cpu.dtb.data_hits 1041 # DTB hits +system.cpu.dtb.data_misses 35 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1116 # DTB accesses -system.cpu.itb.fetch_hits 947 # ITB hits +system.cpu.dtb.data_accesses 1076 # DTB accesses +system.cpu.itb.fetch_hits 931 # ITB hits system.cpu.itb.fetch_misses 26 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 973 # ITB accesses +system.cpu.itb.fetch_accesses 957 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,236 +293,236 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 25549 # number of cpu cycles simulated +system.cpu.numCycles 25184 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4412 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6683 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1106 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 415 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1538 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 502 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 4404 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6508 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1086 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 403 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1405 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 504 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1107 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1109 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 947 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 152 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7337 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.910863 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.331734 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 931 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 153 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7199 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.904014 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.325149 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6194 84.42% 84.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 50 0.68% 85.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 126 1.72% 86.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 86 1.17% 87.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 137 1.87% 89.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 59 0.80% 90.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 69 0.94% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 62 0.85% 92.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 554 7.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6086 84.54% 84.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 49 0.68% 85.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 124 1.72% 86.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 82 1.14% 88.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 134 1.86% 89.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 58 0.81% 90.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 66 0.92% 91.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 57 0.79% 92.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 543 7.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7337 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.043289 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.261576 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5200 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 911 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 995 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 54 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 177 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 159 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 7199 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.043123 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.258418 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5197 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 794 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 972 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 178 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 158 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 76 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 5779 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 271 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 177 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5279 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 611 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 960 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 20 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5531 # Number of instructions processed by rename +system.cpu.decode.DecodedInsts 5639 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 276 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 178 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5280 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 486 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 288 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 942 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 25 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5401 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu.rename.RenamedOperands 3966 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6277 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6270 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 13 # Number of times rename has blocked due to IQ full +system.cpu.rename.RenamedOperands 3881 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6093 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6086 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2198 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2113 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 117 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 895 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 472 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4768 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 109 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 882 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 453 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 4674 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 3966 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2386 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1238 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 3880 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2292 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1214 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7337 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.540548 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.288327 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7199 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.538964 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.280196 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5813 79.23% 79.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 503 6.86% 86.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 359 4.89% 90.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 255 3.48% 94.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 198 2.70% 97.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 113 1.54% 98.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 62 0.85% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 21 0.29% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 13 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5699 79.16% 79.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 500 6.95% 86.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 351 4.88% 90.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 251 3.49% 94.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 194 2.69% 97.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 116 1.61% 98.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 57 0.79% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 21 0.29% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7337 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7199 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11 18.97% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 22 37.93% 56.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 25 43.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 11.76% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 22 43.14% 54.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 45.10% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2817 71.03% 71.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.05% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 757 19.09% 90.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 391 9.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2765 71.26% 71.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 738 19.02% 90.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 376 9.69% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3966 # Type of FU issued -system.cpu.iq.rate 0.155231 # Inst issue rate -system.cpu.iq.fu_busy_cnt 58 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014624 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15337 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7157 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3670 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 3880 # Type of FU issued +system.cpu.iq.rate 0.154066 # Inst issue rate +system.cpu.iq.fu_busy_cnt 51 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013144 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15012 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 6969 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3584 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4017 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 3924 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 480 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 467 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 3 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 178 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 159 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 24 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 177 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 538 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5114 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 178 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 422 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5018 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 28 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 895 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 472 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 882 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 453 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 3 # Number of memory order violations +system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 21 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 167 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 188 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3845 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 731 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 121 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 168 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 189 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3751 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 707 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 129 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 340 # number of nop insts executed -system.cpu.iew.exec_refs 1117 # number of memory reference insts executed -system.cpu.iew.exec_branches 655 # Number of branches executed -system.cpu.iew.exec_stores 386 # Number of stores executed -system.cpu.iew.exec_rate 0.150495 # Inst execution rate -system.cpu.iew.wb_sent 3743 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3676 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1745 # num instructions producing a value -system.cpu.iew.wb_consumers 2262 # num instructions consuming a value +system.cpu.iew.exec_nop 338 # number of nop insts executed +system.cpu.iew.exec_refs 1077 # number of memory reference insts executed +system.cpu.iew.exec_branches 639 # Number of branches executed +system.cpu.iew.exec_stores 370 # Number of stores executed +system.cpu.iew.exec_rate 0.148944 # Inst execution rate +system.cpu.iew.wb_sent 3648 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3590 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1708 # num instructions producing a value +system.cpu.iew.wb_consumers 2182 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.143880 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.771441 # average fanout of values written-back +system.cpu.iew.wb_rate 0.142551 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.782768 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2526 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2428 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 154 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6873 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.374800 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.238011 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 155 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6748 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.381743 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.245988 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 6022 87.62% 87.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 192 2.79% 90.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 299 4.35% 94.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 111 1.62% 96.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 72 1.05% 97.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 55 0.80% 98.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 33 0.48% 98.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 20 0.29% 99.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69 1.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5894 87.34% 87.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193 2.86% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 303 4.49% 94.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 109 1.62% 96.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 72 1.07% 97.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 56 0.83% 98.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 33 0.49% 98.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 20 0.30% 98.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 68 1.01% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6873 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6748 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -568,101 +568,101 @@ system.cpu.commit.op_class_0::MemWrite 294 11.41% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 2576 # Class of committed instruction -system.cpu.commit.bw_lim_events 69 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 11659 # The number of ROB reads -system.cpu.rob.rob_writes 10686 # The number of ROB writes +system.cpu.commit.bw_lim_events 68 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 11437 # The number of ROB reads +system.cpu.rob.rob_writes 10476 # The number of ROB writes system.cpu.timesIdled 151 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18212 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 17985 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 10.703393 # CPI: Cycles Per Instruction -system.cpu.cpi_total 10.703393 # CPI: Total CPI of All Threads -system.cpu.ipc 0.093428 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.093428 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4655 # number of integer regfile reads -system.cpu.int_regfile_writes 2832 # number of integer regfile writes +system.cpu.cpi 10.550482 # CPI: Cycles Per Instruction +system.cpu.cpi_total 10.550482 # CPI: Total CPI of All Threads +system.cpu.ipc 0.094782 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.094782 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4532 # number of integer regfile reads +system.cpu.int_regfile_writes 2777 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 46.039302 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 743 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 45.864197 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 731 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.741176 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.600000 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 46.039302 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011240 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011240 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 45.864197 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011197 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011197 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1969 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1969 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 525 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 525 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 218 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 218 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 743 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 743 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 743 # number of overall hits -system.cpu.dcache.overall_hits::total 743 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 123 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 123 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 199 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 199 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 199 # number of overall misses -system.cpu.dcache.overall_misses::total 199 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8172750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8172750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5678000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5678000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13850750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13850750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13850750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13850750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 648 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 648 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1937 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1937 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 518 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 518 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 731 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 731 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 731 # number of overall hits +system.cpu.dcache.overall_hits::total 731 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 114 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 114 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 195 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 195 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 195 # number of overall misses +system.cpu.dcache.overall_misses::total 195 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7589500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7589500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5666500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5666500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13256000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13256000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13256000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13256000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 632 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 632 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 942 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 942 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 942 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 942 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.189815 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.189815 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.258503 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.258503 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.211253 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.211253 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.211253 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.211253 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66445.121951 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66445.121951 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74710.526316 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74710.526316 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69601.758794 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69601.758794 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69601.758794 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69601.758794 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 926 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 926 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 926 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 926 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180380 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.180380 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.210583 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.210583 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.210583 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.210583 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66574.561404 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66574.561404 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69956.790123 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69956.790123 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67979.487179 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67979.487179 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67979.487179 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67979.487179 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 139 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.500000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 114 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 114 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 114 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 114 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 53 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 110 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 110 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 110 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 110 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -671,193 +671,198 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4793500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4793500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1841500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1841500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6635000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6635000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6635000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6635000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094136 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094136 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4809500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4809500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1851000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1851000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6660500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6660500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6660500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6660500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.096519 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.096519 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090234 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090234 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090234 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090234 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78581.967213 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78581.967213 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76729.166667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76729.166667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78058.823529 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78058.823529 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78058.823529 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78058.823529 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091793 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091793 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091793 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091793 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78844.262295 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78844.262295 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77125 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77125 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78358.823529 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78358.823529 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78358.823529 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78358.823529 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 91.893913 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 694 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 91.507771 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 679 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.711230 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.631016 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 91.893913 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.044870 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.044870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 91.507771 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.044682 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.044682 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 187 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.091309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2081 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2081 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 694 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 694 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 694 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 694 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 694 # number of overall hits -system.cpu.icache.overall_hits::total 694 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 253 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 253 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 253 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 253 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 253 # number of overall misses -system.cpu.icache.overall_misses::total 253 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18914999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18914999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18914999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18914999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18914999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18914999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 947 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 947 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 947 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 947 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 947 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 947 # number of 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74288.770053 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76841.176471 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75086.397059 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -866,55 +871,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 248 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 187 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 187 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 61 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 61 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11881250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3969500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15850750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1520000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1520000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11881250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5489500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17370750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11881250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5489500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17370750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1573500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1573500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12022000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12022000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4108000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4108000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12022000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5681500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17703500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12022000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5681500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17703500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63536.096257 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65073.770492 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63914.314516 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63333.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63333.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63536.096257 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64582.352941 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63863.051471 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63536.096257 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64582.352941 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63863.051471 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65562.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65562.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64288.770053 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64288.770053 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67344.262295 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67344.262295 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64288.770053 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66841.176471 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65086.397059 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64288.770053 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66841.176471 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65086.397059 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 187 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 61 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 544 # Packet count per connected master and slave (bytes) @@ -935,14 +945,14 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 318750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 139500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 248 # Transaction distribution +system.cpu.toL2Bus.respLayer0.occupancy 280500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.membus.trans_dist::ReadResp 248 # Transaction distribution system.membus.trans_dist::ReadExReq 24 # Transaction distribution system.membus.trans_dist::ReadExResp 24 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 248 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 544 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 544 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17408 # Cumulative packet size per connected master and slave (bytes) @@ -958,9 +968,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 272 # Request fanout histogram -system.membus.reqLayer0.occupancy 341000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 337000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 1440250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1441250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index 19e3fb417..7e5bf1bcb 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000048 # Number of seconds simulated -sim_ticks 47840 # Number of ticks simulated -final_tick 47840 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000047 # Number of seconds simulated +sim_ticks 47487 # Number of ticks simulated +final_tick 47487 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 35814 # Simulator instruction rate (inst/s) -host_op_rate 35808 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 664620 # Simulator tick rate (ticks/s) -host_mem_usage 449364 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 68488 # Simulator instruction rate (inst/s) +host_op_rate 68466 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1261208 # Simulator tick rate (ticks/s) +host_mem_usage 449476 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,36 +21,36 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 626 # system.mem_ctrls.num_reads::total 626 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 622 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 622 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 837458194 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 837458194 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 832107023 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 832107023 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1669565217 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1669565217 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 843683534 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 843683534 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 838292585 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 838292585 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1681976120 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1681976120 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 626 # Number of read requests accepted system.mem_ctrls.writeReqs 622 # Number of write requests accepted system.mem_ctrls.readBursts 626 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 622 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 24704 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 15360 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 23360 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 24640 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 15424 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 23424 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 40064 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 39808 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 240 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 225 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 241 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 227 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 29 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 25 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 30 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 24 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 51 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 53 # Per bank write bursts system.mem_ctrls.perBankRdBursts::7 57 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 70 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 63 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 4 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 24 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 14 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 26 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 16 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 31 # Per bank write bursts system.mem_ctrls.perBankRdBursts::13 68 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 10 # Per bank write bursts @@ -58,22 +58,22 @@ system.mem_ctrls.perBankRdBursts::15 1 # Pe system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 29 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 24 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 30 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 23 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 51 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 46 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 73 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 4 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 20 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 14 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 33 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 58 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 52 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 63 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 3 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 22 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 16 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 32 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 61 # Per bank write bursts system.mem_ctrls.perBankWrBursts::14 10 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 47801 # Total gap between requests +system.mem_ctrls.totGap 47448 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 622 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 386 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 385 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -135,11 +135,11 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 21 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 24 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 24 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 22 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 25 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 25 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::20 25 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::21 23 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::22 23 # What write queue length does an incoming req see @@ -149,11 +149,11 @@ system.mem_ctrls.wrQLenPdf::25 23 # Wh system.mem_ctrls.wrQLenPdf::26 23 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::27 23 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::28 23 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 23 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 23 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 23 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 22 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 22 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 22 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::32 22 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -184,87 +184,88 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 109 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 438.605505 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 303.845174 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 335.937991 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 14 12.84% 12.84% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 30 27.52% 40.37% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 12 11.01% 51.38% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 11 10.09% 61.47% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 6 5.50% 66.97% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 9 8.26% 75.23% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 9 8.26% 83.49% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 4 3.67% 87.16% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 14 12.84% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 109 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 113 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 424.212389 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 291.141419 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 329.481775 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 17 15.04% 15.04% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 29 25.66% 40.71% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 14 12.39% 53.10% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 9 7.96% 61.06% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 9 7.96% 69.03% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 10 8.85% 77.88% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 8 7.08% 84.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 4 3.54% 88.50% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 13 11.50% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 113 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 22 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 16.863636 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 16.473921 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 4.443245 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 3 13.64% 13.64% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 5 22.73% 36.36% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 9 40.91% 77.27% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 4 18.18% 95.45% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 17 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 16.622974 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 4.396969 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 2 9.09% 9.09% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 7 31.82% 40.91% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 7 31.82% 72.73% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 5 22.73% 95.45% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::34-35 1 4.55% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 22 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 22 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.590909 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.555699 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.140555 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.636364 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.592012 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.292670 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::16 17 77.27% 77.27% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 2 9.09% 86.36% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 3 13.64% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 1 4.55% 81.82% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 3 13.64% 95.45% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 1 4.55% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 22 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 4080 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 11414 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 1930 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 10.57 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 3756 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 11071 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 1925 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 9.76 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 29.57 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 516.39 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 488.29 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 837.46 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 832.11 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 28.76 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 518.88 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 493.27 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 843.68 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 838.29 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 7.85 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.03 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 3.81 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 7.91 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.05 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 3.85 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 24.93 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 289 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 349 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 74.87 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 87.91 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 38.30 # Average gap between requests -system.mem_ctrls.pageHitRate 81.48 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 249480 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 138600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 2009280 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 1575936 # Energy for write commands per rank (pJ) +system.mem_ctrls.avgWrQLen 24.54 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 294 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 342 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 76.36 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 86.58 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 38.02 # Average gap between requests +system.mem_ctrls.pageHitRate 81.54 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 257040 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 142800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 2046720 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 1638144 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 30369600 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 1545600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 38939856 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 828.930858 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 2928 # Time in different power states +system.mem_ctrls_0.actBackEnergy 30869604 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 1107000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 39112668 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 832.609588 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 1942 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 43008 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 43739 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 574560 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 319200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 2758080 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 2208384 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.actEnergy 597240 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 331800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2733120 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 2156544 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 31087116 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 916200 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 40914900 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 870.974540 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 1359 # Time in different power states +system.mem_ctrls_1.actBackEnergy 31287528 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 740400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 40897992 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 870.614612 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1080 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 1560 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 44071 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 44350 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -300,7 +301,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 47840 # number of cpu cycles simulated +system.cpu.numCycles 47487 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -319,7 +320,7 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 47840 # Number of busy cycles +system.cpu.num_busy_cycles 47487 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched @@ -374,10 +375,10 @@ system.ruby.outstanding_req_hist::total 3295 system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 3294 -system.ruby.latency_hist::mean 13.523376 -system.ruby.latency_hist::gmean 5.183572 -system.ruby.latency_hist::stdev 25.409311 -system.ruby.latency_hist | 3181 96.57% 96.57% | 93 2.82% 99.39% | 16 0.49% 99.88% | 1 0.03% 99.91% | 2 0.06% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::mean 13.416211 +system.ruby.latency_hist::gmean 5.177559 +system.ruby.latency_hist::stdev 25.037672 +system.ruby.latency_hist | 3186 96.72% 96.72% | 90 2.73% 99.45% | 15 0.46% 99.91% | 0 0.00% 99.91% | 2 0.06% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 3294 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 @@ -389,17 +390,17 @@ system.ruby.hit_latency_hist::total 2668 system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 626 -system.ruby.miss_latency_hist::mean 58.373802 -system.ruby.miss_latency_hist::gmean 53.319163 -system.ruby.miss_latency_hist::stdev 30.235728 -system.ruby.miss_latency_hist | 513 81.95% 81.95% | 93 14.86% 96.81% | 16 2.56% 99.36% | 1 0.16% 99.52% | 2 0.32% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::mean 57.809904 +system.ruby.miss_latency_hist::gmean 52.994493 +system.ruby.miss_latency_hist::stdev 29.424898 +system.ruby.miss_latency_hist | 518 82.75% 82.75% | 90 14.38% 97.12% | 15 2.40% 99.52% | 0 0.00% 99.52% | 2 0.32% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 626 system.ruby.Directory.incomplete_times 625 system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.521739 +system.ruby.network.routers0.percent_links_utilized 6.570219 system.ruby.network.routers0.msg_count.Control::2 626 system.ruby.network.routers0.msg_count.Data::2 622 system.ruby.network.routers0.msg_count.Response_Data::4 626 @@ -408,7 +409,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 5008 system.ruby.network.routers0.msg_bytes.Data::2 44784 system.ruby.network.routers0.msg_bytes.Response_Data::4 45072 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers1.percent_links_utilized 6.521739 +system.ruby.network.routers1.percent_links_utilized 6.570219 system.ruby.network.routers1.msg_count.Control::2 626 system.ruby.network.routers1.msg_count.Data::2 622 system.ruby.network.routers1.msg_count.Response_Data::4 626 @@ -417,7 +418,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 5008 system.ruby.network.routers1.msg_bytes.Data::2 44784 system.ruby.network.routers1.msg_bytes.Response_Data::4 45072 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers2.percent_links_utilized 6.521739 +system.ruby.network.routers2.percent_links_utilized 6.570219 system.ruby.network.routers2.msg_count.Control::2 626 system.ruby.network.routers2.msg_count.Data::2 622 system.ruby.network.routers2.msg_count.Response_Data::4 626 @@ -434,32 +435,32 @@ system.ruby.network.msg_byte.Control 15024 system.ruby.network.msg_byte.Data 134352 system.ruby.network.msg_byte.Response_Data 135216 system.ruby.network.msg_byte.Writeback_Control 14928 -system.ruby.network.routers0.throttle0.link_utilization 6.538462 +system.ruby.network.routers0.throttle0.link_utilization 6.587066 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 626 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 622 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 45072 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers0.throttle1.link_utilization 6.505017 +system.ruby.network.routers0.throttle1.link_utilization 6.553373 system.ruby.network.routers0.throttle1.msg_count.Control::2 626 system.ruby.network.routers0.throttle1.msg_count.Data::2 622 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 5008 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 44784 -system.ruby.network.routers1.throttle0.link_utilization 6.505017 +system.ruby.network.routers1.throttle0.link_utilization 6.553373 system.ruby.network.routers1.throttle0.msg_count.Control::2 626 system.ruby.network.routers1.throttle0.msg_count.Data::2 622 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 5008 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 44784 -system.ruby.network.routers1.throttle1.link_utilization 6.538462 +system.ruby.network.routers1.throttle1.link_utilization 6.587066 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 626 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 622 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 45072 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers2.throttle0.link_utilization 6.538462 +system.ruby.network.routers2.throttle0.link_utilization 6.587066 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 626 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 622 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 45072 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers2.throttle1.link_utilization 6.505017 +system.ruby.network.routers2.throttle1.link_utilization 6.553373 system.ruby.network.routers2.throttle1.msg_count.Control::2 626 system.ruby.network.routers2.throttle1.msg_count.Data::2 622 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 5008 @@ -477,10 +478,10 @@ system.ruby.delayVCHist.vnet_2::total 622 # de system.ruby.LD.latency_hist::bucket_size 64 system.ruby.LD.latency_hist::max_bucket 639 system.ruby.LD.latency_hist::samples 415 -system.ruby.LD.latency_hist::mean 33.055422 -system.ruby.LD.latency_hist::gmean 15.599823 -system.ruby.LD.latency_hist::stdev 34.047272 -system.ruby.LD.latency_hist | 375 90.36% 90.36% | 33 7.95% 98.31% | 6 1.45% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::mean 33.036145 +system.ruby.LD.latency_hist::gmean 15.653569 +system.ruby.LD.latency_hist::stdev 33.343638 +system.ruby.LD.latency_hist | 375 90.36% 90.36% | 35 8.43% 98.80% | 4 0.96% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist::total 415 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 @@ -492,18 +493,18 @@ system.ruby.LD.hit_latency_hist::total 170 system.ruby.LD.miss_latency_hist::bucket_size 64 system.ruby.LD.miss_latency_hist::max_bucket 639 system.ruby.LD.miss_latency_hist::samples 245 -system.ruby.LD.miss_latency_hist::mean 53.910204 -system.ruby.LD.miss_latency_hist::gmean 48.970543 -system.ruby.LD.miss_latency_hist::stdev 30.013250 -system.ruby.LD.miss_latency_hist | 205 83.67% 83.67% | 33 13.47% 97.14% | 6 2.45% 99.59% | 0 0.00% 99.59% | 0 0.00% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::mean 53.877551 +system.ruby.LD.miss_latency_hist::gmean 49.256670 +system.ruby.LD.miss_latency_hist::stdev 28.665419 +system.ruby.LD.miss_latency_hist | 205 83.67% 83.67% | 35 14.29% 97.96% | 4 1.63% 99.59% | 0 0.00% 99.59% | 0 0.00% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 245 system.ruby.ST.latency_hist::bucket_size 32 system.ruby.ST.latency_hist::max_bucket 319 system.ruby.ST.latency_hist::samples 294 -system.ruby.ST.latency_hist::mean 17.248299 -system.ruby.ST.latency_hist::gmean 6.615603 -system.ruby.ST.latency_hist::stdev 28.817235 -system.ruby.ST.latency_hist | 210 71.43% 71.43% | 74 25.17% 96.60% | 8 2.72% 99.32% | 0 0.00% 99.32% | 1 0.34% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% +system.ruby.ST.latency_hist::mean 17.955782 +system.ruby.ST.latency_hist::gmean 6.677068 +system.ruby.ST.latency_hist::stdev 30.544793 +system.ruby.ST.latency_hist | 210 71.43% 71.43% | 73 24.83% 96.26% | 7 2.38% 98.64% | 0 0.00% 98.64% | 3 1.02% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% system.ruby.ST.latency_hist::total 294 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 @@ -515,18 +516,18 @@ system.ruby.ST.hit_latency_hist::total 210 system.ruby.ST.miss_latency_hist::bucket_size 32 system.ruby.ST.miss_latency_hist::max_bucket 319 system.ruby.ST.miss_latency_hist::samples 84 -system.ruby.ST.miss_latency_hist::mean 52.869048 -system.ruby.ST.miss_latency_hist::gmean 47.773810 -system.ruby.ST.miss_latency_hist::stdev 33.671260 -system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 74 88.10% 88.10% | 8 9.52% 97.62% | 0 0.00% 97.62% | 1 1.19% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1 1.19% 100.00% +system.ruby.ST.miss_latency_hist::mean 55.345238 +system.ruby.ST.miss_latency_hist::gmean 49.345449 +system.ruby.ST.miss_latency_hist::stdev 36.232680 +system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 73 86.90% 86.90% | 7 8.33% 95.24% | 0 0.00% 95.24% | 3 3.57% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1 1.19% 100.00% system.ruby.ST.miss_latency_hist::total 84 system.ruby.IFETCH.latency_hist::bucket_size 32 system.ruby.IFETCH.latency_hist::max_bucket 319 system.ruby.IFETCH.latency_hist::samples 2585 -system.ruby.IFETCH.latency_hist::mean 9.964023 -system.ruby.IFETCH.latency_hist::gmean 4.224377 -system.ruby.IFETCH.latency_hist::stdev 21.618756 -system.ruby.IFETCH.latency_hist | 2288 88.51% 88.51% | 234 9.05% 97.56% | 49 1.90% 99.46% | 3 0.12% 99.57% | 2 0.08% 99.65% | 7 0.27% 99.92% | 1 0.04% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 1 0.04% 100.00% +system.ruby.IFETCH.latency_hist::mean 9.750097 +system.ruby.IFETCH.latency_hist::gmean 4.211373 +system.ruby.IFETCH.latency_hist::stdev 20.913083 +system.ruby.IFETCH.latency_hist | 2288 88.51% 88.51% | 240 9.28% 97.79% | 46 1.78% 99.57% | 2 0.08% 99.65% | 2 0.08% 99.73% | 6 0.23% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 1 0.04% 100.00% system.ruby.IFETCH.latency_hist::total 2585 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 @@ -538,18 +539,18 @@ system.ruby.IFETCH.hit_latency_hist::total 2288 system.ruby.IFETCH.miss_latency_hist::bucket_size 32 system.ruby.IFETCH.miss_latency_hist::max_bucket 319 system.ruby.IFETCH.miss_latency_hist::samples 297 -system.ruby.IFETCH.miss_latency_hist::mean 63.612795 -system.ruby.IFETCH.miss_latency_hist::gmean 58.999958 -system.ruby.IFETCH.miss_latency_hist::stdev 28.587258 -system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 234 78.79% 78.79% | 49 16.50% 95.29% | 3 1.01% 96.30% | 2 0.67% 96.97% | 7 2.36% 99.33% | 1 0.34% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% +system.ruby.IFETCH.miss_latency_hist::mean 61.750842 +system.ruby.IFETCH.miss_latency_hist::gmean 57.437802 +system.ruby.IFETCH.miss_latency_hist::stdev 27.433554 +system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 240 80.81% 80.81% | 46 15.49% 96.30% | 2 0.67% 96.97% | 2 0.67% 97.64% | 6 2.02% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% system.ruby.IFETCH.miss_latency_hist::total 297 system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 626 -system.ruby.Directory.miss_mach_latency_hist::mean 58.373802 -system.ruby.Directory.miss_mach_latency_hist::gmean 53.319163 -system.ruby.Directory.miss_mach_latency_hist::stdev 30.235728 -system.ruby.Directory.miss_mach_latency_hist | 513 81.95% 81.95% | 93 14.86% 96.81% | 16 2.56% 99.36% | 1 0.16% 99.52% | 2 0.32% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::mean 57.809904 +system.ruby.Directory.miss_mach_latency_hist::gmean 52.994493 +system.ruby.Directory.miss_mach_latency_hist::stdev 29.424898 +system.ruby.Directory.miss_mach_latency_hist | 518 82.75% 82.75% | 90 14.38% 97.12% | 15 2.40% 99.52% | 0 0.00% 99.52% | 2 0.32% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 626 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 @@ -580,26 +581,26 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::total system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 245 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 53.910204 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 48.970543 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 30.013250 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 205 83.67% 83.67% | 33 13.47% 97.14% | 6 2.45% 99.59% | 0 0.00% 99.59% | 0 0.00% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 53.877551 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 49.256670 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 28.665419 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 205 83.67% 83.67% | 35 14.29% 97.96% | 4 1.63% 99.59% | 0 0.00% 99.59% | 0 0.00% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 245 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 84 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 52.869048 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 47.773810 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 33.671260 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 74 88.10% 88.10% | 8 9.52% 97.62% | 0 0.00% 97.62% | 1 1.19% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1 1.19% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 55.345238 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 49.345449 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 36.232680 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 73 86.90% 86.90% | 7 8.33% 95.24% | 0 0.00% 95.24% | 3 3.57% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1 1.19% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist::total 84 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 32 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 297 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 63.612795 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 58.999958 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 28.587258 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 234 78.79% 78.79% | 49 16.50% 95.29% | 3 1.01% 96.30% | 2 0.67% 96.97% | 7 2.36% 99.33% | 1 0.34% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 61.750842 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 57.437802 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 27.433554 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 240 80.81% 80.81% | 46 15.49% 96.30% | 2 0.67% 96.97% | 2 0.67% 97.64% | 6 2.02% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 297 system.ruby.Directory_Controller.GETX 626 0.00% 0.00% system.ruby.Directory_Controller.PUTX 622 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 364bc6f05..7411927e4 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000017 # Nu sim_ticks 16524500 # Number of ticks simulated final_tick 16524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 396950 # Simulator instruction rate (inst/s) -host_op_rate 396157 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2535599202 # Simulator tick rate (ticks/s) -host_mem_usage 290048 # Number of bytes of host memory used +host_inst_rate 374183 # Simulator instruction rate (inst/s) +host_op_rate 373424 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2390351512 # Simulator tick rate (ticks/s) +host_mem_usage 291260 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated @@ -122,14 +122,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 47.433873 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 47.431392 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 47.433873 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011581 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 47.431392 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011580 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011580 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 82 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id @@ -200,14 +200,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 82 system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2942500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2942500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1444500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1444500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4387000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4387000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4387000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4387000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2970000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2970000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1458000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1458000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4428000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4428000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4428000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4428000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses @@ -216,24 +216,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 80.042941 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 80.038009 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 80.042941 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.039083 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.039083 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 80.038009 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.039081 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.039081 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 163 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id @@ -290,91 +290,96 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 163 system.cpu.icache.demand_mshr_misses::total 163 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 163 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 8721000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 8721000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 8721000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 8721000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8721000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 8721000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 8802500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 8802500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 8802500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 8802500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8802500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 8802500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53503.067485 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53503.067485 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53503.067485 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53503.067485 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53503.067485 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53503.067485 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54003.067485 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54003.067485 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54003.067485 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54003.067485 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54003.067485 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54003.067485 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 107.153052 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 107.126637 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 218 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.161341 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 26.991711 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.141583 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 26.985054 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002446 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003270 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003269 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 218 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.006653 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2205 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2205 # Number of data accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 218 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 163 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 163 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 55 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 163 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 82 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 245 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 82 # number of overall misses system.cpu.l2cache.overall_misses::total 245 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8558000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2887500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 11445500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1417500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1417500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 8558000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 8558000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2887500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2887500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 8558000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 4305000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 12863000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 8558000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 4305000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 12863000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 163 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 218 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 163 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 163 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 55 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 55 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 163 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 82 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 245 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 163 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 82 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 245 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52503.067485 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52502.293578 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52503.067485 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52503.067485 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52503.067485 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52502.040816 # average overall miss latency @@ -389,55 +394,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 163 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 218 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 27 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 163 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 163 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 55 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 245 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 245 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6601500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2227500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8829000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1093500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1093500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6601500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3321000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9922500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6601500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3321000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9922500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1147500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1147500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 6928000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 6928000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2337500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2337500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6928000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3485000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10413000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6928000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3485000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10413000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42503.067485 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42503.067485 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42503.067485 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42502.040816 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.067485 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42502.040816 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 218 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 163 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 326 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 164 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 490 # Packet count per connected master and slave (bytes) @@ -462,10 +472,10 @@ system.cpu.toL2Bus.respLayer0.occupancy 244500 # La system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 123000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.trans_dist::ReadReq 218 # Transaction distribution system.membus.trans_dist::ReadResp 218 # Transaction distribution system.membus.trans_dist::ReadExReq 27 # Transaction distribution system.membus.trans_dist::ReadExResp 27 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 218 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 490 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 490 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index b37232811..e5ff065c1 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 30323500 # Number of ticks simulated -final_tick 30323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 29934500 # Number of ticks simulated +final_tick 29934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 117134 # Simulator instruction rate (inst/s) -host_op_rate 137081 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 770805796 # Simulator tick rate (ticks/s) -host_mem_usage 310084 # Number of bytes of host memory used +host_inst_rate 115469 # Simulator instruction rate (inst/s) +host_op_rate 135130 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 750106498 # Simulator tick rate (ticks/s) +host_mem_usage 310152 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host sim_insts 4605 # Number of instructions simulated sim_ops 5391 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory system.physmem.num_reads::total 421 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 643725164 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 244826620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 888551783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 643725164 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 643725164 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 643725164 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 244826620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 888551783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 652090397 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 248008151 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 900098548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 652090397 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 652090397 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 652090397 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 248008151 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 900098548 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 421 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 30232000 # Total gap between requests +system.physmem.totGap 29844000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -186,51 +186,51 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 402.285714 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 286.758489 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.986232 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19 30.16% 41.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13 20.63% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 5 7.94% 69.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.76% 74.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4 6.35% 80.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 3.17% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.59% 85.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 2542750 # Total ticks spent queuing -system.physmem.totMemAccLat 10436500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 408.774194 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 286.680005 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.685266 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18 29.03% 41.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11 17.74% 59.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4 6.45% 66.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5 8.06% 74.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 4.84% 79.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 4.84% 83.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.61% 85.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation +system.physmem.totQLat 2214000 # Total ticks spent queuing +system.physmem.totMemAccLat 10107750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6039.79 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5258.91 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24789.79 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 888.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24008.91 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 900.10 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 888.55 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 900.10 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.94 # Data bus utilization in percentage -system.physmem.busUtilRead 6.94 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.03 # Data bus utilization in percentage +system.physmem.busUtilRead 7.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 349 # Number of row buffer hits during reads +system.physmem.readRowHits 350 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.90 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 71809.98 # Average gap between requests -system.physmem.pageHitRate 82.90 # Row buffer hit rate, read and write combined +system.physmem.avgGap 70888.36 # Average gap between requests +system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1942200 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 1973400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 20036940 # Total energy per rank (pJ) -system.physmem_0.averagePower 848.348875 # Core power per rank (mW) +system.physmem_0.totalEnergy 20068140 # Total energy per rank (pJ) +system.physmem_0.averagePower 849.669860 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 12500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states @@ -241,14 +241,14 @@ system.physmem_1.preEnergy 70125 # En system.physmem_1.readEnergy 694200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15437025 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 630000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 18485550 # Total energy per rank (pJ) -system.physmem_1.averagePower 782.664197 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2433750 # Time in different power states +system.physmem_1.actBackEnergy 15748245 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 357000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 18523770 # Total energy per rank (pJ) +system.physmem_1.averagePower 784.282403 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1650750 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 21873250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 22328250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 1918 # Number of BP lookups system.cpu.branchPred.condPredicted 1150 # Number of conditional branches predicted @@ -377,26 +377,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 60647 # number of cpu cycles simulated +system.cpu.numCycles 59869 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4605 # Number of instructions committed system.cpu.committedOps 5391 # Number of ops (including micro ops) committed system.cpu.discardedOps 1116 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 13.169815 # CPI: cycles per instruction -system.cpu.ipc 0.075931 # IPC: instructions per cycle -system.cpu.tickCycles 10567 # Number of cycles that the object actually ticked -system.cpu.idleCycles 50080 # Total number of cycles that the object has spent stopped +system.cpu.cpi 13.000869 # CPI: cycles per instruction +system.cpu.ipc 0.076918 # IPC: instructions per cycle +system.cpu.tickCycles 10574 # Number of cycles that the object actually ticked +system.cpu.idleCycles 49295 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.373507 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 86.493580 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.373507 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021087 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021087 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.493580 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021117 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021117 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id @@ -423,14 +423,14 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7248241 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7248241 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5053500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5053500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12301741 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12301741 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12301741 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12301741 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6956000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6956000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5019500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5019500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 11975500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 11975500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 11975500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 11975500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1165 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1165 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -451,14 +451,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.087584 system.cpu.dcache.demand_miss_rate::total 0.087584 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.087584 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.087584 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63028.182609 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63028.182609 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75425.373134 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75425.373134 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67591.983516 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67591.983516 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67591.983516 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67591.983516 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60486.956522 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60486.956522 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74917.910448 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74917.910448 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65799.450549 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65799.450549 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65799.450549 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65799.450549 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -483,14 +483,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6562258 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6562258 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3179250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3179250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9741508 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9741508 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9741508 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9741508 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6353000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6353000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3198000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3198000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9551000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9551000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9551000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9551000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088412 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088412 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses @@ -499,27 +499,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070260 system.cpu.dcache.demand_mshr_miss_rate::total 0.070260 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070260 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.070260 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63711.242718 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63711.242718 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73936.046512 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73936.046512 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66722.657534 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66722.657534 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66722.657534 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66722.657534 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61679.611650 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61679.611650 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74372.093023 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74372.093023 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65417.808219 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65417.808219 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65417.808219 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 65417.808219 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 161.448164 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 161.765243 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1909 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 5.928571 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 161.448164 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078832 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078832 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 161.765243 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078987 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078987 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4784 # Number of tag accesses system.cpu.icache.tags.data_accesses 4784 # Number of data accesses @@ -535,12 +535,12 @@ system.cpu.icache.demand_misses::cpu.inst 322 # n system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses system.cpu.icache.overall_misses::total 322 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23879500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23879500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23879500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23879500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23879500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23879500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23594000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23594000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23594000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23594000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23594000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23594000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2231 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2231 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2231 # number of demand (read+write) accesses @@ -553,12 +553,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.144330 system.cpu.icache.demand_miss_rate::total 0.144330 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.144330 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.144330 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74159.937888 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74159.937888 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74159.937888 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74159.937888 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74159.937888 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74159.937888 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73273.291925 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73273.291925 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 73273.291925 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73273.291925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 73273.291925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73273.291925 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -573,106 +573,112 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 322 system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23261500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23261500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23261500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23261500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23261500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23261500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23272000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23272000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23272000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23272000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23272000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23272000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.144330 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.144330 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.144330 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.144330 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.144330 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.144330 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72240.683230 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72240.683230 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72240.683230 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72240.683230 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72240.683230 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72240.683230 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72273.291925 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72273.291925 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72273.291925 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72273.291925 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72273.291925 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72273.291925 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 195.068888 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 195.411120 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 41 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.103175 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.108466 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.992766 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 41.076122 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004699 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001254 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005953 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.281002 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 41.130118 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004708 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005963 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4165 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4165 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 22 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 4181 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4181 # Number of data accesses +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 17 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 22 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 22 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits system.cpu.l2cache.overall_hits::total 39 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 305 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 81 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 386 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 305 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 305 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 81 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 81 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 305 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 124 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 429 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses system.cpu.l2cache.overall_misses::total 429 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22761000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6225250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28986250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3136250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3136250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22761000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9361500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32122500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22761000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9361500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32122500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 322 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 103 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 425 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3133500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3133500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22610500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 22610500 # number of ReadCleanReq miss cycles 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+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 322 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 322 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 468 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 322 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 468 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.947205 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.786408 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.908235 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947205 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947205 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.786408 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.786408 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947205 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.849315 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.916667 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74626.229508 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76854.938272 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75093.911917 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72936.046512 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72936.046512 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74626.229508 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75495.967742 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74877.622378 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74626.229508 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75495.967742 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74877.622378 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72872.093023 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72872.093023 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74132.786885 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74132.786885 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73586.419753 # average ReadSharedReq miss latency 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system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 305 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 73 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 378 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 305 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 305 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 73 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 73 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 116 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 421 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18938500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4780750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23719250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2598750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2598750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18938500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7379500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26318000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18938500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7379500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26318000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889412 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2703500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2703500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19560500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19560500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4700500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4700500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19560500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7404000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26964500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19560500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7404000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26964500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947205 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.708738 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62093.442623 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65489.726027 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62749.338624 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60436.046512 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60436.046512 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62093.442623 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63616.379310 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62513.064133 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62093.442623 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63616.379310 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62513.064133 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62872.093023 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62872.093023 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64132.786885 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64132.786885 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64390.410959 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64390.410959 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64132.786885 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63827.586207 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64048.693587 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64132.786885 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63827.586207 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64048.693587 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 425 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 644 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 936 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 938 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20608 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 471 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 468 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 471 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 234000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 471 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 235500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 550500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 240992 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.trans_dist::ReadReq 378 # Transaction distribution +system.cpu.toL2Bus.respLayer0.occupancy 483000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.membus.trans_dist::ReadResp 378 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 378 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 842 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26944 # Cumulative packet size per connected master and slave (bytes) @@ -779,9 +791,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 421 # Request fanout histogram -system.membus.reqLayer0.occupancy 490500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 491000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2238000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 7.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 2236500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 725976bdf..80e232875 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17398000 # Number of ticks simulated -final_tick 17398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 17226500 # Number of ticks simulated +final_tick 17226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57922 # Simulator instruction rate (inst/s) -host_op_rate 67825 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 219380871 # Simulator tick rate (ticks/s) -host_mem_usage 310080 # Number of bytes of host memory used +host_inst_rate 55427 # Simulator instruction rate (inst/s) +host_op_rate 64904 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 207866253 # Simulator tick rate (ticks/s) +host_mem_usage 311436 # Number of bytes of host memory used host_seconds 0.08 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory system.physmem.bytes_read::total 25344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 120 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory system.physmem.num_reads::total 396 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1015289114 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 441430049 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1456719163 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1015289114 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1015289114 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1015289114 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 441430049 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1456719163 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1021681711 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 449539953 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1471221664 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1021681711 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1021681711 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1021681711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 449539953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1471221664 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 396 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 17318000 # Total gap between requests +system.physmem.totGap 17159000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 208 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see @@ -186,78 +186,78 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 59 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 410.033898 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 279.539573 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 339.305882 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 9 15.25% 15.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 27.12% 42.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8 13.56% 55.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 9 15.25% 71.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 3.39% 74.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.39% 77.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 3.39% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 3.39% 84.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 15.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation -system.physmem.totQLat 3886750 # Total ticks spent queuing -system.physmem.totMemAccLat 11311750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 395.354839 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 263.720067 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 338.958245 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 11 17.74% 17.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 30.65% 48.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6 9.68% 58.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8 12.90% 70.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.84% 75.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 3.23% 79.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 3.23% 82.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 3.23% 85.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation +system.physmem.totQLat 3039250 # Total ticks spent queuing +system.physmem.totMemAccLat 10464250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9815.03 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7674.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28565.03 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1456.72 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26424.87 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1471.22 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1456.72 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1471.22 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.38 # Data bus utilization in percentage -system.physmem.busUtilRead 11.38 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.49 # Data bus utilization in percentage +system.physmem.busUtilRead 11.49 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.88 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 331 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.59 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43732.32 # Average gap between requests +system.physmem.avgGap 43330.81 # Average gap between requests system.physmem.pageHitRate 83.59 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 287280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 156750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2051400 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 302400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 165000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10748205 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 71250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14332005 # Total energy per rank (pJ) -system.physmem_0.averagePower 905.226907 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 62750 # Time in different power states +system.physmem_0.actBackEnergy 10797795 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14404965 # Total energy per rank (pJ) +system.physmem_0.averagePower 909.404356 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 69250 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15263500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16109250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 143640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 78375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 741000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 748800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10299330 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 465000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12744465 # Total energy per rank (pJ) -system.physmem_1.averagePower 804.955945 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 732000 # Time in different power states +system.physmem_1.actBackEnergy 10359180 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 412500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12771300 # Total energy per rank (pJ) +system.physmem_1.averagePower 806.650876 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 820250 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14594250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14680750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2567 # Number of BP lookups -system.cpu.branchPred.condPredicted 1598 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2576 # Number of BP lookups +system.cpu.branchPred.condPredicted 1602 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 469 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2080 # Number of BTB lookups -system.cpu.branchPred.BTBHits 778 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2087 # Number of BTB lookups +system.cpu.branchPred.BTBHits 781 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 37.403846 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 334 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 37.422137 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 336 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -496,178 +496,178 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 34797 # number of cpu cycles simulated +system.cpu.numCycles 34454 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7703 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12168 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2567 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1112 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4777 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 7709 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12205 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2576 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1117 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4748 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 987 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 2007 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 300 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13242 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.084202 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.460827 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2016 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13219 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.088585 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.463952 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10620 80.20% 80.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 274 2.07% 82.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 209 1.58% 83.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 222 1.68% 85.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 233 1.76% 87.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 323 2.44% 89.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 137 1.03% 90.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 162 1.22% 91.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1062 8.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10589 80.10% 80.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 274 2.07% 82.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 212 1.60% 83.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 221 1.67% 85.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 236 1.79% 87.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 324 2.45% 89.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 139 1.05% 90.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 161 1.22% 91.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1063 8.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13242 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.073771 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.349685 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6338 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4330 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2103 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 133 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 13219 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.074766 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.354240 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6369 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4276 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2102 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 134 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 338 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11850 # Number of instructions handled by decode +system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 11852 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 468 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 338 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6554 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 6584 # Number of cycles rename is idle system.cpu.rename.BlockCycles 692 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2396 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2012 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1250 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11194 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 171 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 132 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1066 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 11323 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 51655 # Number of register rename lookups that rename has made +system.cpu.rename.serializeStallCycles 2356 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2013 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1236 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11200 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 168 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 130 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1064 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 11331 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 51672 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 12441 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5829 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 42 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 36 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 409 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2284 # Number of loads inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 5837 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 43 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 422 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2287 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1689 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 38 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 34 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10118 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 10125 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8189 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4786 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12366 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8202 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 55 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4793 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 12371 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13242 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.618411 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.365218 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13219 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.620471 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.365465 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10034 75.77% 75.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1166 8.81% 84.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 746 5.63% 90.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 448 3.38% 93.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 359 2.71% 96.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 279 2.11% 98.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10002 75.66% 75.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1166 8.82% 84.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 755 5.71% 90.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 451 3.41% 93.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 357 2.70% 96.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 278 2.10% 98.41% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 131 0.99% 99.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 62 0.47% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 17 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 63 0.48% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 16 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13242 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13219 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 5.20% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.20% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 84 48.55% 53.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 80 46.24% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 5.26% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 84 49.12% 54.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78 45.61% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4931 60.21% 60.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1952 23.84% 84.16% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1297 15.84% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4937 60.19% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1959 23.88% 84.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1297 15.81% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8189 # Type of FU issued -system.cpu.iq.rate 0.235336 # Inst issue rate -system.cpu.iq.fu_busy_cnt 173 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021126 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29748 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14841 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7422 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8202 # Type of FU issued +system.cpu.iq.rate 0.238057 # Inst issue rate +system.cpu.iq.fu_busy_cnt 171 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.020849 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29750 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14855 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7430 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8319 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8330 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 24 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1257 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1260 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 751 # Number of stores squashed @@ -677,56 +677,56 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 32 # system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 338 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 662 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10173 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 130 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2284 # Number of dispatched load instructions +system.cpu.iew.iewBlockCycles 660 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10180 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 127 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2287 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1689 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 111 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 233 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 344 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7858 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1841 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 331 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 234 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 345 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7868 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1843 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 334 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 9 # number of nop insts executed -system.cpu.iew.exec_refs 3070 # number of memory reference insts executed -system.cpu.iew.exec_branches 1431 # Number of branches executed +system.cpu.iew.exec_refs 3072 # number of memory reference insts executed +system.cpu.iew.exec_branches 1434 # Number of branches executed system.cpu.iew.exec_stores 1229 # Number of stores executed -system.cpu.iew.exec_rate 0.225824 # Inst execution rate -system.cpu.iew.wb_sent 7567 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7454 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3520 # num instructions producing a value -system.cpu.iew.wb_consumers 6887 # num instructions consuming a value +system.cpu.iew.exec_rate 0.228362 # Inst execution rate +system.cpu.iew.wb_sent 7574 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7462 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3524 # num instructions producing a value +system.cpu.iew.wb_consumers 6897 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.214214 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.511108 # average fanout of values written-back +system.cpu.iew.wb_rate 0.216579 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.510947 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4794 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4801 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 314 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12404 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.433570 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.280415 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12382 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.434340 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.281233 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10350 83.44% 83.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 890 7.18% 90.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 420 3.39% 94.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 213 1.72% 95.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 118 0.95% 96.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 211 1.70% 98.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 49 0.40% 98.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 36 0.29% 99.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 117 0.94% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10327 83.40% 83.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 891 7.20% 90.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 421 3.40% 94.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 214 1.73% 95.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 114 0.92% 96.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 212 1.71% 98.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 49 0.40% 98.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.31% 99.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 115 0.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12404 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12382 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -772,121 +772,121 @@ system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction -system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22302 # The number of ROB reads -system.cpu.rob.rob_writes 21197 # The number of ROB writes -system.cpu.timesIdled 195 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21555 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 115 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 22289 # The number of ROB reads +system.cpu.rob.rob_writes 21210 # The number of ROB writes +system.cpu.timesIdled 194 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 21235 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.577744 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.577744 # CPI: Total CPI of All Threads -system.cpu.ipc 0.131965 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.131965 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7744 # number of integer regfile reads -system.cpu.int_regfile_writes 4257 # number of integer regfile writes +system.cpu.cpi 7.503049 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.503049 # CPI: Total CPI of All Threads +system.cpu.ipc 0.133279 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.133279 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 7752 # number of integer regfile reads +system.cpu.int_regfile_writes 4259 # number of integer regfile writes system.cpu.fp_regfile_reads 32 # number of floating regfile reads -system.cpu.cc_regfile_reads 28092 # number of cc regfile reads -system.cpu.cc_regfile_writes 3277 # number of cc regfile writes -system.cpu.misc_regfile_reads 3176 # number of misc regfile reads +system.cpu.cc_regfile_reads 28119 # number of cc regfile reads +system.cpu.cc_regfile_writes 3280 # number of cc regfile writes +system.cpu.misc_regfile_reads 3175 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.050512 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2159 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.687075 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.080084 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2156 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.767123 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.050512 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021253 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021253 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 87.080084 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021260 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021260 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5463 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5463 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1539 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1539 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 598 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 598 # number of WriteReq hits +system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5466 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5466 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1537 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1537 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2137 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2137 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2137 # number of overall hits -system.cpu.dcache.overall_hits::total 2137 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 182 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 182 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2134 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2134 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2134 # number of overall hits +system.cpu.dcache.overall_hits::total 2134 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 186 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 186 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 497 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses -system.cpu.dcache.overall_misses::total 497 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10876493 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10876493 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22731000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22731000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 144500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 144500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33607493 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33607493 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33607493 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33607493 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1721 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1721 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses +system.cpu.dcache.overall_misses::total 502 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10668000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10668000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22567500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22567500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 142000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33235500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33235500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33235500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33235500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1723 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1723 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2634 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2634 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2634 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2634 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.105752 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.105752 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.345016 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.345016 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2636 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2636 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2636 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2636 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.107951 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.107951 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.188686 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.188686 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.188686 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.188686 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59760.950549 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59760.950549 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72161.904762 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72161.904762 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67620.710262 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67620.710262 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67620.710262 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67620.710262 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.190440 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.190440 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.190440 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.190440 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57354.838710 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 57354.838710 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71416.139241 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 71416.139241 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66206.175299 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66206.175299 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66206.175299 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66206.175299 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 63 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 273 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 273 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -895,82 +895,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6879255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6879255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3390500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3390500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10269755 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10269755 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10269755 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10269755 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.061011 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.061011 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6685000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6685000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3406500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3406500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10091500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10091500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10091500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10091500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.060940 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.060940 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055809 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.055809 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055809 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.055809 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65516.714286 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65516.714286 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80726.190476 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80726.190476 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69862.278912 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 69862.278912 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69862.278912 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 69862.278912 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055766 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.055766 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055766 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.055766 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63666.666667 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63666.666667 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81107.142857 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81107.142857 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68649.659864 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68649.659864 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68649.659864 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68649.659864 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 149.166565 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1613 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 149.175552 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1623 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 293 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.505119 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.539249 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 149.166565 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.072835 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.072835 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 149.175552 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.072840 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.072840 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4307 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4307 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1613 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1613 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1613 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1613 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1613 # number of overall hits -system.cpu.icache.overall_hits::total 1613 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 394 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 394 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 394 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 394 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 394 # number of overall misses -system.cpu.icache.overall_misses::total 394 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28003250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28003250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28003250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28003250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28003250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28003250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2007 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2007 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2007 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2007 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2007 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2007 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196313 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.196313 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.196313 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.196313 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.196313 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.196313 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71074.238579 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71074.238579 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71074.238579 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71074.238579 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71074.238579 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71074.238579 # average overall miss latency +system.cpu.icache.tags.tag_accesses 4325 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4325 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1623 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1623 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1623 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1623 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1623 # number of overall hits +system.cpu.icache.overall_hits::total 1623 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 393 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 393 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 393 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 393 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 393 # number of overall misses +system.cpu.icache.overall_misses::total 393 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 27030000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 27030000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 27030000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 27030000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 27030000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 27030000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2016 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2016 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2016 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2016 # number of demand (read+write) accesses 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+system.cpu.icache.demand_avg_miss_latency::total 68778.625954 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68778.625954 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68778.625954 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 456 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -979,118 +979,124 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 91.200000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 101 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 101 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 101 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 101 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 101 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 100 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 100 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 100 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 100 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 100 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 293 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 293 # number of 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accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.857143 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.911364 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.941980 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.850340 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938567 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.857143 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.911364 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78644.927536 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78786.144578 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 78677.576602 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79678.571429 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79678.571429 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78644.927536 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79086 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78782.418953 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78644.927536 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79086 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78782.418953 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79583.333333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79583.333333 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76154.545455 # average ReadCleanReq miss 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blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1099,89 +1105,94 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR 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+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 79 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 79 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 396 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 120 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18264000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5236000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23500000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2824500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2824500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18264000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8060500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26324500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18264000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8060500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26324500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.941980 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.742857 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889447 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2922500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2922500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18192500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18192500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5250500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5250500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18192500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8173000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26365500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18192500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8173000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26365500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.941980 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.816327 # mshr miss rate for demand accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938567 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.752381 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.900000 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.941980 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.816327 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66173.913043 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67128.205128 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 66384.180791 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67250 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67250 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66173.913043 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67170.833333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66476.010101 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66173.913043 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67170.833333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66476.010101 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69583.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69583.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66154.545455 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66154.545455 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66462.025316 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66462.025316 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66154.545455 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67545.454545 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66579.545455 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66154.545455 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67545.454545 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66579.545455 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 398 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 397 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 293 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 586 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 880 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 879 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28096 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 440 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 441 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 220000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 493000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 239245 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.membus.trans_dist::ReadReq 354 # Transaction distribution +system.cpu.toL2Bus.respLayer0.occupancy 439500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 221495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) system.membus.trans_dist::ReadResp 354 # Transaction distribution system.membus.trans_dist::ReadExReq 42 # Transaction distribution system.membus.trans_dist::ReadExResp 42 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 354 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 792 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 792 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25344 # Cumulative packet size per connected master and slave (bytes) @@ -1197,9 +1208,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 396 # Request fanout histogram -system.membus.reqLayer0.occupancy 497000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2092000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.0 # Layer utilization (%) +system.membus.reqLayer0.occupancy 485500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 2095750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 835d1798d..65214b87e 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 17788000 # Number of ticks simulated -final_tick 17788000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 17777000 # Number of ticks simulated +final_tick 17777000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 23007 # Simulator instruction rate (inst/s) -host_op_rate 26942 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 89104120 # Simulator tick rate (ticks/s) -host_mem_usage 300104 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 63568 # Simulator instruction rate (inst/s) +host_op_rate 74435 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 246000775 # Simulator tick rate (ticks/s) +host_mem_usage 307848 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.inst 271 # Nu system.physmem.num_reads::cpu.data 108 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory system.physmem.num_reads::total 406 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 975039352 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 388576568 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 97144142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1460760063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 975039352 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 975039352 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 975039352 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 388576568 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 97144142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1460760063 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 975642684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 388817011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 97204253 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1461663948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 975642684 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 975642684 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 975642684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 388817011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 97204253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1461663948 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 407 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 407 # Number of DRAM read bursts, including those serviced by the write queue @@ -79,7 +79,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 17774500 # Total gap between requests +system.physmem.totGap 17763500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -94,8 +94,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 224 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see @@ -204,65 +204,65 @@ system.physmem.bytesPerActivate::768-895 3 5.08% 79.66% # By system.physmem.bytesPerActivate::896-1023 2 3.39% 83.05% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 16.95% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation -system.physmem.totQLat 3111242 # Total ticks spent queuing -system.physmem.totMemAccLat 10742492 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3256492 # Total ticks spent queuing +system.physmem.totMemAccLat 10887742 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2035000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7644.33 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8001.21 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26394.33 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1464.36 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26751.21 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1465.26 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1464.36 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1465.26 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.44 # Data bus utilization in percentage -system.physmem.busUtilRead 11.44 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.45 # Data bus utilization in percentage +system.physmem.busUtilRead 11.45 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.77 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 340 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43671.99 # Average gap between requests +system.physmem.avgGap 43644.96 # Average gap between requests system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10829430 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14375115 # Total energy per rank (pJ) -system.physmem_0.averagePower 905.162692 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 243500 # Time in different power states +system.physmem_0.actBackEnergy 10756755 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 63750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14336940 # Total energy per rank (pJ) +system.physmem_0.averagePower 905.538607 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 334000 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15368000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15275500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10100115 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 639750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12751230 # Total energy per rank (pJ) -system.physmem_1.averagePower 805.383231 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1024000 # Time in different power states +system.physmem_1.actBackEnergy 10156545 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 590250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12758160 # Total energy per rank (pJ) +system.physmem_1.averagePower 805.820938 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 942000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14302250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14384250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2340 # Number of BP lookups -system.cpu.branchPred.condPredicted 1388 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 507 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 838 # Number of BTB lookups +system.cpu.branchPred.lookups 2336 # Number of BP lookups +system.cpu.branchPred.condPredicted 1386 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 508 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 837 # Number of BTB lookups system.cpu.branchPred.BTBHits 442 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 52.744630 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 290 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 55 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 52.807646 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 289 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,84 +381,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 35577 # number of cpu cycles simulated +system.cpu.numCycles 35555 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6129 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11284 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2340 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 732 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 7521 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1057 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 129 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 6172 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11259 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2336 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 731 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 7501 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1059 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 155 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 303 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 320 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3831 # Number of cache lines fetched +system.cpu.fetch.IcacheWaitRetryStallCycles 318 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 3825 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 176 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14930 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.882251 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.211921 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 14978 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.878021 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.210560 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8724 58.43% 58.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2462 16.49% 74.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 522 3.50% 78.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3222 21.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8782 58.63% 58.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2458 16.41% 75.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 521 3.48% 78.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3217 21.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14930 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.065773 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.317171 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5843 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3543 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5049 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 128 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 367 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 14978 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.065701 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.316664 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5920 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3520 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5039 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 131 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 368 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 329 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 9870 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1626 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 367 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6916 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 964 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1980 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4098 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 605 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 8889 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 403 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full +system.cpu.decode.DecodedInsts 9859 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1620 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 368 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6989 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 960 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1965 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4095 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 601 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 8880 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 409 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 531 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9240 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 40319 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9768 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 527 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9231 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 40283 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9759 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3746 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3737 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 299 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 1806 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1281 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1277 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8360 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8347 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7147 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 189 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3021 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7902 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 7144 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 184 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3008 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7841 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14930 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.478701 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.863585 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14978 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.476966 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.861224 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10739 71.93% 71.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1936 12.97% 84.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1601 10.72% 95.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 607 4.07% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 47 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10780 71.97% 71.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1947 13.00% 84.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1601 10.69% 95.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 605 4.04% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 45 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -466,149 +466,149 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14930 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14978 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 420 29.23% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 467 32.50% 61.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 550 38.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 411 28.90% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 464 32.63% 61.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 547 38.47% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4466 62.49% 62.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1589 22.23% 84.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1084 15.17% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4467 62.53% 62.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.64% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.64% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1588 22.23% 84.87% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1081 15.13% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7147 # Type of FU issued -system.cpu.iq.rate 0.200888 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1437 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.201063 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30806 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11411 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6546 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 7144 # Type of FU issued +system.cpu.iq.rate 0.200928 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1422 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.199048 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30828 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11385 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 6550 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8556 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8538 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 779 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 343 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 339 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 367 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 358 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 8413 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 368 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 356 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 8400 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 1806 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1281 # Number of dispatched store instructions +system.cpu.iew.iewDispStoreInsts 1277 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedTakenIncorrect 67 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 360 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6739 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1406 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 408 # Number of squashed instructions skipped in execute +system.cpu.iew.branchMispredicts 361 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 6741 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1404 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 403 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 14 # number of nop insts executed -system.cpu.iew.exec_refs 2430 # number of memory reference insts executed -system.cpu.iew.exec_branches 1270 # Number of branches executed -system.cpu.iew.exec_stores 1024 # Number of stores executed -system.cpu.iew.exec_rate 0.189420 # Inst execution rate -system.cpu.iew.wb_sent 6605 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6562 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2976 # num instructions producing a value -system.cpu.iew.wb_consumers 5371 # num instructions consuming a value +system.cpu.iew.exec_refs 2427 # number of memory reference insts executed +system.cpu.iew.exec_branches 1272 # Number of branches executed +system.cpu.iew.exec_stores 1023 # Number of stores executed +system.cpu.iew.exec_rate 0.189594 # Inst execution rate +system.cpu.iew.wb_sent 6608 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6566 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2973 # num instructions producing a value +system.cpu.iew.wb_consumers 5368 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.184445 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.554087 # average fanout of values written-back +system.cpu.iew.wb_rate 0.184672 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.553838 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2578 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2565 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 346 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14390 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.373732 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.023936 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 347 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 14437 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.372515 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.021269 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11747 81.63% 81.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1377 9.57% 91.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 605 4.20% 95.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 294 2.04% 97.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 168 1.17% 98.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 77 0.54% 99.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 46 0.32% 99.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 32 0.22% 99.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 44 0.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11787 81.64% 81.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1388 9.61% 91.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 602 4.17% 95.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 293 2.03% 97.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 168 1.16% 98.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 78 0.54% 99.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 45 0.31% 99.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 33 0.23% 99.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 43 0.30% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14390 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14437 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -654,121 +654,121 @@ system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction -system.cpu.commit.bw_lim_events 44 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22145 # The number of ROB reads -system.cpu.rob.rob_writes 16457 # The number of ROB writes -system.cpu.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20647 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 22180 # The number of ROB reads +system.cpu.rob.rob_writes 16432 # The number of ROB writes +system.cpu.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20577 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.747605 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.747605 # CPI: Total CPI of All Threads -system.cpu.ipc 0.129072 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.129072 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6713 # number of integer regfile reads +system.cpu.cpi 7.742814 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.742814 # CPI: Total CPI of All Threads +system.cpu.ipc 0.129152 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.129152 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 6717 # number of integer regfile reads system.cpu.int_regfile_writes 3745 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 23953 # number of cc regfile reads -system.cpu.cc_regfile_writes 2889 # number of cc regfile writes -system.cpu.misc_regfile_reads 2609 # number of misc regfile reads +system.cpu.cc_regfile_reads 23956 # number of cc regfile reads +system.cpu.cc_regfile_writes 2895 # number of cc regfile writes +system.cpu.misc_regfile_reads 2607 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.188922 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 84.382295 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.507042 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.485915 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.188922 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.164431 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.164431 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.382295 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.164809 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.164809 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.275391 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4696 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4696 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1176 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1176 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4692 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4692 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1173 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1173 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1898 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1898 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1898 # number of overall hits -system.cpu.dcache.overall_hits::total 1898 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 1895 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1895 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1895 # number of overall hits +system.cpu.dcache.overall_hits::total 1895 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 357 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 357 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 357 # number of overall misses -system.cpu.dcache.overall_misses::total 357 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9257492 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9257492 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7277250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7277250 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 126000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 126000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16534742 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16534742 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16534742 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16534742 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1342 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1342 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses +system.cpu.dcache.overall_misses::total 358 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9199500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9199500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7245500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7245500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 125000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16445000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16445000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16445000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16445000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1340 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1340 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2255 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2255 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2255 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2255 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123696 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.123696 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2253 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2253 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2253 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2253 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.124627 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.124627 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.158315 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.158315 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.158315 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.158315 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55768.024096 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55768.024096 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38100.785340 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38100.785340 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46315.803922 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46315.803922 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46315.803922 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46315.803922 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.158899 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.158899 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.158899 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.158899 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55086.826347 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55086.826347 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37934.554974 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37934.554974 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45935.754190 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45935.754190 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45935.754190 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45935.754190 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 717 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 731 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 39.833333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 40.611111 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 214 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 214 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 214 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 214 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 215 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 215 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 215 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -777,120 +777,120 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 143 system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5795755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5795755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2367750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2367750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8163505 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8163505 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8163505 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8163505 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076006 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5829500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5829500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2385500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2385500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8215000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8215000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8215000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8215000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076119 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076119 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063415 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063415 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063415 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063415 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56821.127451 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56821.127451 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57750 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57750 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57087.447552 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57087.447552 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57087.447552 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57087.447552 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063471 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063471 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063471 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063471 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57151.960784 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57151.960784 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58182.926829 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58182.926829 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57447.552448 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57447.552448 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57447.552448 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57447.552448 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 42 # number of replacements -system.cpu.icache.tags.tagsinuse 136.057531 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3467 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 136.424572 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3459 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.752542 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.725424 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 136.057531 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.265737 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.265737 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 136.424572 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.266454 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.266454 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 253 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 7955 # Number of tag accesses -system.cpu.icache.tags.data_accesses 7955 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 3467 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3467 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3467 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3467 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3467 # number of overall hits -system.cpu.icache.overall_hits::total 3467 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses -system.cpu.icache.overall_misses::total 363 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21749991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21749991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21749991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21749991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21749991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21749991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3830 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3830 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3830 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3830 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3830 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3830 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094778 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.094778 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.094778 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.094778 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.094778 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.094778 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59917.330579 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 59917.330579 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 59917.330579 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 59917.330579 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 59917.330579 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 59917.330579 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8313 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 7941 # Number of tag accesses +system.cpu.icache.tags.data_accesses 7941 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 3459 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3459 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3459 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3459 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3459 # number of overall hits +system.cpu.icache.overall_hits::total 3459 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses +system.cpu.icache.overall_misses::total 364 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21691493 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21691493 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21691493 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21691493 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21691493 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21691493 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 3823 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 3823 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 3823 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 3823 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 3823 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 3823 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.095213 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.095213 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.095213 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.095213 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.095213 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.095213 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59592.013736 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 59592.013736 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 59592.013736 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 59592.013736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 59592.013736 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 59592.013736 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8521 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 33 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 90 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 89 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 92.366667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 95.741573 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18653743 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 18653743 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18653743 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 18653743 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18653743 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 18653743 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077285 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077285 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077285 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.077285 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077285 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.077285 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63019.402027 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63019.402027 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63019.402027 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 63019.402027 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63019.402027 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 63019.402027 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18899993 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 18899993 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18899993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 18899993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18899993 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 18899993 # number of overall MSHR miss cycles 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latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63851.327703 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 63851.327703 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified @@ -899,94 +899,100 @@ system.cpu.l2cache.prefetcher.pfInCache 0 # nu system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 192.560599 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 193.028614 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 74 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.115385 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.203297 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.350778 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 45.044062 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.165759 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008444 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002749 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000559 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.011753 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.716720 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 45.124038 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.187855 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008467 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002754 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000561 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.011782 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.021240 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7429 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7429 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 23 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 19 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 42 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 7941 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7941 # Number of data accesses system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 23 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 23 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 19 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 19 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 23 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 30 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 53 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 23 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 30 # number of overall hits system.cpu.l2cache.overall_hits::total 53 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 273 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 83 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 356 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 30 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 30 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 273 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 273 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 83 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 83 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 273 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 113 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 386 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 273 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 113 # number of overall misses system.cpu.l2cache.overall_misses::total 386 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18354000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5568750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 23922750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2253750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2253750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 18354000 # number of demand (read+write) miss cycles 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18451000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 18451000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5549000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 5549000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 18451000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7800000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 26251000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 18451000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7800000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 26251000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq 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system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.922297 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813725 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.894472 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.731707 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.731707 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.922297 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.922297 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.813725 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.813725 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.922297 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.790210 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.879271 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.922297 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.790210 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.879271 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67230.769231 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67093.373494 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67198.735955 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75125 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75125 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67230.769231 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69225.663717 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67814.766839 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67230.769231 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69225.663717 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67814.766839 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75033.333333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75033.333333 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67586.080586 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67586.080586 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66855.421687 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66855.421687 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67586.080586 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69026.548673 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68007.772021 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67586.080586 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69026.548673 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68007.772021 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -995,22 +1001,24 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 78 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 48 # number of HardPFReq MSHR misses system.cpu.l2cache.HardPFReq_mshr_misses::total 48 # number of HardPFReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 30 # 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(read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6620500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22614500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15994000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6620500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1641917 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24256417 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.879397 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1697924 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1697924 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2071000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2071000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 16769500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 16769500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4788500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4788500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16769500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6859500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23629000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16769500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6859500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1697924 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25326924 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.918919 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.764706 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.865604 # mshr miss rate for demand accesses @@ -1046,54 +1056,57 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.918919 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.974943 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58801.470588 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59201.923077 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58890.714286 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34206.604167 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34206.604167 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66758.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66758.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58801.470588 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61300.925926 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59511.842105 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58801.470588 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61300.925926 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34206.604167 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56673.871495 # average overall mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35373.416667 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 35373.416667 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69033.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69033.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61652.573529 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61652.573529 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61391.025641 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61391.025641 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61652.573529 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63513.888889 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62181.578947 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61652.573529 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63513.888889 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35373.416667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59175.056075 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 398 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 32 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFReq 64 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 591 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 296 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 102 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 623 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 876 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 908 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 64 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 503 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.127237 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.333570 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 546 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.117216 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.321973 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 439 87.28% 87.28% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 64 12.72% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 482 88.28% 88.28% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 64 11.72% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 503 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 496999 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 228995 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 377 # Transaction distribution +system.cpu.toL2Bus.snoop_fanout::total 546 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 442999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 215495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) system.membus.trans_dist::ReadResp 375 # Transaction distribution system.membus.trans_dist::ReadExReq 30 # Transaction distribution system.membus.trans_dist::ReadExResp 30 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 377 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 812 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 812 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25920 # Cumulative packet size per connected master and slave (bytes) @@ -1109,9 +1122,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 407 # Request fanout histogram -system.membus.reqLayer0.occupancy 508443 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 510442 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2142008 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2136258 # Layer occupancy (ticks) system.membus.respLayer1.utilization 12.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index eccfa92c7..85d747802 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000026 # Nu sim_ticks 25816500 # Number of ticks simulated final_tick 25816500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77759 # Simulator instruction rate (inst/s) -host_op_rate 90742 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 439383785 # Simulator tick rate (ticks/s) -host_mem_usage 301384 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 428411 # Simulator instruction rate (inst/s) +host_op_rate 499438 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2416370273 # Simulator tick rate (ticks/s) +host_mem_usage 308620 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4566 # Number of instructions simulated sim_ops 5330 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5391 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.896193 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 82.893462 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.896193 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 82.893462 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.020238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.020238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id @@ -294,14 +294,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4571000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4571000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2300500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2300500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6871500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6871500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6871500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6871500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4620000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4620000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2322000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2322000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6942000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6942000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6942000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6942000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses @@ -310,24 +310,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46642.857143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46642.857143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47142.857143 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47142.857143 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49234.042553 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 49234.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49234.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 49234.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 114.417529 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 114.412880 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 114.417529 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.055868 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.055868 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 114.412880 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.055866 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.055866 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id @@ -384,100 +384,106 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 241 system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12227000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12227000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12227000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12227000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12227000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12227000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12347500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12347500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12347500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12347500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12347500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12347500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50734.439834 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50734.439834 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51234.439834 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51234.439834 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51234.439834 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51234.439834 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51234.439834 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51234.439834 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 153.834298 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 153.810302 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.699770 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48.134528 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003226 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.682127 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48.128175 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003225 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004695 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004694 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 16 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 16 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits system.cpu.l2cache.overall_hits::total 32 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 225 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 82 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 307 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 225 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 225 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 82 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 82 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 350 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses system.cpu.l2cache.overall_misses::total 350 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11818000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4305000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 16123000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2257500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2257500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11818000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 11818000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4305000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4305000 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 11818000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 6562500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 18380500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 11818000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 6562500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 18380500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 241 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 98 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 241 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 241 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 98 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 98 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 241 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 382 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 241 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 382 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.836735 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.905605 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.933610 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.836735 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.836735 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.916230 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52524.444444 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52517.915309 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52524.444444 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52524.444444 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52515.714286 # average overall miss latency @@ -492,55 +498,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 225 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 307 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 225 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 225 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 82 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 82 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9112500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3321000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12433500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1741500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1741500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9112500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5062500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14175000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9112500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5062500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14175000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.905605 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1827500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1827500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9568000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9568000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3485000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3485000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9568000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5312500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14880500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9568000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5312500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14880500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.933610 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.836735 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42524.444444 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42524.444444 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42524.444444 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42515.714286 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42524.444444 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42515.714286 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 241 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 98 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 482 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 764 # Packet count per connected master and slave (bytes) @@ -548,27 +559,27 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 383 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 382 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 383 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 383 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 191500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.trans_dist::ReadReq 307 # Transaction distribution system.membus.trans_dist::ReadResp 307 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 307 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 8ffb75804..5213b7cc0 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000023 # Number of seconds simulated -sim_ticks 22762000 # Number of ticks simulated -final_tick 22762000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000022 # Number of seconds simulated +sim_ticks 22403000 # Number of ticks simulated +final_tick 22403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3472 # Simulator instruction rate (inst/s) -host_op_rate 3472 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15849922 # Simulator tick rate (ticks/s) -host_mem_usage 223436 # Number of bytes of host memory used -host_seconds 1.44 # Real time elapsed on the host +host_inst_rate 79030 # Simulator instruction rate (inst/s) +host_op_rate 79012 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 354943993 # Simulator tick rate (ticks/s) +host_mem_usage 292784 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 4986 # Number of instructions simulated sim_ops 4986 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21120 # Nu system.physmem.num_reads::cpu.inst 330 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory system.physmem.num_reads::total 471 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 927862227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 396450224 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1324312451 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 927862227 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 927862227 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 927862227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 396450224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1324312451 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 942730884 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 402803196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1345534080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 942730884 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 942730884 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 942730884 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 402803196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1345534080 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 471 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 471 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22674500 # Total gap between requests +system.physmem.totGap 22316000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -92,9 +92,9 @@ system.physmem.writePktSize::5 0 # Wr system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 277 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,79 +186,79 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 104 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 262.153846 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 181.184943 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 253.583818 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 28 26.92% 26.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 35 33.65% 60.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 18 17.31% 77.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 10 9.62% 87.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 2.88% 90.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 1.92% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 0.96% 93.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 0.96% 94.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6 5.77% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 104 # Bytes accessed per row activation -system.physmem.totQLat 5218000 # Total ticks spent queuing -system.physmem.totMemAccLat 14049250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 105 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 260.876190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.828028 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 254.099908 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 30 28.57% 28.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 33 31.43% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 19 18.10% 78.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 10 9.52% 87.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 2.86% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 1.90% 92.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 0.95% 93.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 0.95% 94.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6 5.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 105 # Bytes accessed per row activation +system.physmem.totQLat 4348750 # Total ticks spent queuing +system.physmem.totMemAccLat 13180000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2355000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11078.56 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9233.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29828.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1324.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27983.01 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1345.53 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1324.31 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1345.53 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.35 # Data bus utilization in percentage -system.physmem.busUtilRead 10.35 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.51 # Data bus utilization in percentage +system.physmem.busUtilRead 10.51 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.74 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.71 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 356 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 48141.19 # Average gap between requests +system.physmem.avgGap 47380.04 # Average gap between requests system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 491400 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 538200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 9465705 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1196250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 12369120 # Total energy per rank (pJ) -system.physmem_0.averagePower 781.248697 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1950500 # Time in different power states +system.physmem_0.actBackEnergy 9525555 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1143750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12423270 # Total energy per rank (pJ) +system.physmem_0.averagePower 784.668877 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2113750 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 13375750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 13462250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 514080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 280500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2184000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 521640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 284625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2191800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10729395 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 87750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14812845 # Total energy per rank (pJ) -system.physmem_1.averagePower 935.597347 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 284750 # Time in different power states +system.physmem_1.actBackEnergy 10738800 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 87000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14840985 # Total energy per rank (pJ) +system.physmem_1.averagePower 936.635216 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 103500 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15222250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15234500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2110 # Number of BP lookups -system.cpu.branchPred.condPredicted 1371 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 423 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1629 # Number of BTB lookups -system.cpu.branchPred.BTBHits 525 # Number of BTB hits +system.cpu.branchPred.lookups 2126 # Number of BP lookups +system.cpu.branchPred.condPredicted 1379 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 429 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1641 # Number of BTB lookups +system.cpu.branchPred.BTBHits 514 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.228361 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 280 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 31.322364 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 281 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -279,236 +279,236 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 45525 # number of cpu cycles simulated +system.cpu.numCycles 44807 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8934 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12895 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2110 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 805 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4920 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 864 # Number of cycles fetch has spent squashing -system.cpu.fetch.PendingTrapStallCycles 192 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2026 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14478 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.890662 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.186824 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 8961 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12993 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2126 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 795 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4908 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 876 # Number of cycles fetch has spent squashing +system.cpu.fetch.PendingTrapStallCycles 194 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2040 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14501 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.896007 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.195594 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11164 77.11% 77.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1470 10.15% 87.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 124 0.86% 88.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 160 1.11% 89.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 283 1.95% 91.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 94 0.65% 91.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 128 0.88% 92.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 113 0.78% 93.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 942 6.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11177 77.08% 77.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1470 10.14% 87.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 121 0.83% 88.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 160 1.10% 89.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 283 1.95% 91.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 95 0.66% 91.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 127 0.88% 92.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 112 0.77% 93.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 956 6.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14478 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.046348 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.283251 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8487 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2706 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2773 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 121 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 391 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 174 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 14501 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.047448 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.289977 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8511 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2687 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2777 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 129 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 397 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 172 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11880 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 172 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 391 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8645 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 502 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1002 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2724 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1214 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11398 # Number of instructions processed by rename +system.cpu.decode.DecodedInsts 12008 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 170 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 397 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8669 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 506 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 996 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2735 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1198 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11509 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 231 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 967 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 6879 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13412 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13162 # Number of integer rename lookups +system.cpu.rename.LQFullEvents 229 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 954 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 6966 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13566 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13315 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3282 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3597 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 13 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 290 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2474 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1168 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3684 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 14 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 296 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2503 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1169 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8940 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9007 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8204 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 35 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3964 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1790 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8237 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4031 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1845 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14478 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.566653 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.310295 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14501 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.568030 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.308332 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11167 77.13% 77.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1314 9.08% 86.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 734 5.07% 91.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 423 2.92% 94.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 344 2.38% 96.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 310 2.14% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 102 0.70% 99.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 57 0.39% 99.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 27 0.19% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11165 76.99% 76.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1330 9.17% 86.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 739 5.10% 91.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 423 2.92% 94.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 353 2.43% 96.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 304 2.10% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 105 0.72% 99.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 58 0.40% 99.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 24 0.17% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14478 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14501 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 4.59% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 129 65.82% 70.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7 3.57% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 131 66.84% 70.41% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 58 29.59% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4822 58.78% 58.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2303 28.07% 86.93% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1072 13.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4840 58.76% 58.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2319 28.15% 87.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1071 13.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8204 # Type of FU issued -system.cpu.iq.rate 0.180209 # Inst issue rate +system.cpu.iq.FU_type_0::total 8237 # Type of FU issued +system.cpu.iq.rate 0.183833 # Inst issue rate system.cpu.iq.fu_busy_cnt 196 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023891 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31113 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12922 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7408 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.023795 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31205 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 13056 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7426 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8398 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8431 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 82 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 83 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1342 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1371 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 267 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 23 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 391 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 464 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10483 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2474 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1168 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 397 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 472 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10561 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 155 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2503 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1169 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 9 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 96 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 348 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 444 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7875 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2160 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 329 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 354 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 452 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7898 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2175 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 339 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1532 # number of nop insts executed -system.cpu.iew.exec_refs 3217 # number of memory reference insts executed -system.cpu.iew.exec_branches 1365 # Number of branches executed -system.cpu.iew.exec_stores 1057 # Number of stores executed -system.cpu.iew.exec_rate 0.172982 # Inst execution rate -system.cpu.iew.wb_sent 7509 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7410 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2869 # num instructions producing a value -system.cpu.iew.wb_consumers 4254 # num instructions consuming a value +system.cpu.iew.exec_nop 1543 # number of nop insts executed +system.cpu.iew.exec_refs 3228 # number of memory reference insts executed +system.cpu.iew.exec_branches 1368 # Number of branches executed +system.cpu.iew.exec_stores 1053 # Number of stores executed +system.cpu.iew.exec_rate 0.176267 # Inst execution rate +system.cpu.iew.wb_sent 7529 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7428 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2859 # num instructions producing a value +system.cpu.iew.wb_consumers 4251 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.162768 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.674424 # average fanout of values written-back +system.cpu.iew.wb_rate 0.165778 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.672548 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4860 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4937 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 382 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13623 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.412758 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.228786 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 388 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13632 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.412485 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.223639 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11456 84.09% 84.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 871 6.39% 90.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 510 3.74% 94.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 252 1.85% 96.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 148 1.09% 97.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 178 1.31% 98.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 65 0.48% 98.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 40 0.29% 99.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 103 0.76% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11448 83.98% 83.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 886 6.50% 90.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 511 3.75% 94.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 255 1.87% 96.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 161 1.18% 97.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 164 1.20% 98.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 65 0.48% 98.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 40 0.29% 99.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 102 0.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13623 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13632 # Number of insts commited each cycle system.cpu.commit.committedInsts 5623 # Number of instructions committed system.cpu.commit.committedOps 5623 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -554,101 +554,101 @@ system.cpu.commit.op_class_0::MemWrite 901 16.02% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5623 # Class of committed instruction -system.cpu.commit.bw_lim_events 103 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 23990 # The number of ROB reads -system.cpu.rob.rob_writes 21831 # The number of ROB writes -system.cpu.timesIdled 267 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 31047 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 24077 # The number of ROB reads +system.cpu.rob.rob_writes 22001 # The number of ROB writes +system.cpu.timesIdled 266 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 30306 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4986 # Number of Instructions Simulated system.cpu.committedOps 4986 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 9.130566 # CPI: Cycles Per Instruction -system.cpu.cpi_total 9.130566 # CPI: Total CPI of All Threads -system.cpu.ipc 0.109522 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.109522 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10639 # number of integer regfile reads -system.cpu.int_regfile_writes 5201 # number of integer regfile writes +system.cpu.cpi 8.986562 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.986562 # CPI: Total CPI of All Threads +system.cpu.ipc 0.111277 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.111277 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10682 # number of integer regfile reads +system.cpu.int_regfile_writes 5223 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 165 # number of misc regfile reads +system.cpu.misc_regfile_reads 167 # number of misc regfile reads system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 91.212769 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2418 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 91.242537 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2427 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.148936 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.212766 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 91.212769 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022269 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022269 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 91.242537 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022276 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022276 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5997 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5997 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1862 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1862 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 6025 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 6025 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1871 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1871 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2418 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2418 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2418 # number of overall hits -system.cpu.dcache.overall_hits::total 2418 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 165 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 165 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2427 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2427 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2427 # number of overall hits +system.cpu.dcache.overall_hits::total 2427 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 345 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 345 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses -system.cpu.dcache.overall_misses::total 510 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12038750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12038750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24387249 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24387249 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 36425999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 36425999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 36425999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 36425999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2027 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2027 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 515 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 515 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 515 # number of overall misses +system.cpu.dcache.overall_misses::total 515 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11738500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11738500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24073999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24073999 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35812499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35812499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35812499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35812499 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2041 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2041 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2928 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2928 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2928 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2928 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081401 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.081401 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2942 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2942 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2942 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2942 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083293 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.083293 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.382908 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.382908 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.174180 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.174180 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.174180 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.174180 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72962.121212 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72962.121212 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70687.678261 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70687.678261 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71423.527451 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71423.527451 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71423.527451 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71423.527451 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 611 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.175051 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.175051 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.175051 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.175051 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69050 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 69050 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69779.707246 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69779.707246 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69538.833010 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69538.833010 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69538.833010 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69538.833010 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 615 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.545455 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.909091 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 295 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 295 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 369 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 369 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 369 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses @@ -657,82 +657,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7833500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7833500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4084749 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4084749 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11918249 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11918249 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11918249 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11918249 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044894 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044894 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7586500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7586500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4094999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4094999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11681499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11681499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11681499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11681499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044586 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044586 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048156 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048156 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048156 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048156 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86082.417582 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86082.417582 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81694.980000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81694.980000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84526.588652 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84526.588652 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84526.588652 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84526.588652 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047927 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.047927 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047927 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.047927 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83368.131868 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83368.131868 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81899.980000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81899.980000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82847.510638 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82847.510638 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82847.510638 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82847.510638 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 158.205778 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 158.208729 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1588 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 333 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.735736 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.768769 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 158.205778 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077249 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077249 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 158.208729 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077250 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077250 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 316 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.154297 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4385 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4385 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits -system.cpu.icache.overall_hits::total 1577 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 449 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 449 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 449 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 449 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 449 # number of overall misses -system.cpu.icache.overall_misses::total 449 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34003000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34003000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34003000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34003000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34003000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34003000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2026 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2026 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2026 # number of demand (read+write) accesses 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-system.cpu.icache.demand_avg_miss_latency::cpu.inst 75730.512249 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75730.512249 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75730.512249 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75730.512249 # average overall miss latency +system.cpu.icache.tags.tag_accesses 4413 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4413 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1588 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1588 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1588 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1588 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1588 # number of overall hits +system.cpu.icache.overall_hits::total 1588 # number of overall hits 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of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2040 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2040 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2040 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2040 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2040 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2040 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.221569 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.221569 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.221569 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.221569 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.221569 # miss rate for overall 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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79247.747748 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79247.747748 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79247.747748 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 79247.747748 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79247.747748 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 79247.747748 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25884000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25884000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25884000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25884000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25884000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25884000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.163235 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.163235 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.163235 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.163235 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163235 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.163235 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77729.729730 # average ReadReq mshr miss latency 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system.cpu.l2cache.tags.sampled_refs 421 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.007126 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.047506 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.168468 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.981967 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004888 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001769 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006657 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.142310 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 58.097265 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004887 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001773 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006660 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012848 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4263 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4263 # Number of data accesses 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system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.990991 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.990991 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990991 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.993671 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990991 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993671 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78863.636364 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85038.461538 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 80198.337292 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80680 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80680 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78863.636364 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83492.907801 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 80249.469214 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78863.636364 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83492.907801 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 80249.469214 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80380 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80380 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76827.272727 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76827.272727 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81829.670330 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81829.670330 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76827.272727 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81315.602837 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78170.912951 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76827.272727 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81315.602837 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78170.912951 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -858,83 +863,89 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 330 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 421 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 330 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 330 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 91 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 91 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 330 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 471 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 330 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 471 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21894000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6598000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28492000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3411000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3411000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21894000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10009000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 31903000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21894000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10009000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 31903000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.992925 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3519000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3519000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22053000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22053000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6536500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6536500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22053000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10055500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 32108500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22053000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10055500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 32108500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.990991 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.993671 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993671 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66345.454545 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72505.494505 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67676.959620 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68220 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68220 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66345.454545 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70985.815603 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67734.607219 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66345.454545 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70985.815603 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67734.607219 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70380 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70380 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66827.272727 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66827.272727 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71829.670330 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71829.670330 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66827.272727 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71315.602837 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68170.912951 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66827.272727 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71315.602837 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68170.912951 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 666 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 333 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 91 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 683 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 948 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 965 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21312 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 30336 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 474 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 491 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 474 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 491 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 474 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 237000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 569000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 233500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 421 # Transaction distribution +system.cpu.toL2Bus.snoop_fanout::total 491 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 245500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 499500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.membus.trans_dist::ReadResp 421 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution system.membus.trans_dist::ReadExResp 50 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 421 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 942 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 942 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30144 # Cumulative packet size per connected master and slave (bytes) @@ -950,9 +961,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 471 # Request fanout histogram -system.membus.reqLayer0.occupancy 598000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 582000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2506000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 2503500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 8476aa73a..c6923a4b0 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000115 # Number of seconds simulated -sim_ticks 115467 # Number of ticks simulated -final_tick 115467 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 115089 # Number of ticks simulated +final_tick 115089 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 66709 # Simulator instruction rate (inst/s) -host_op_rate 66698 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1369179 # Simulator tick rate (ticks/s) -host_mem_usage 449556 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 64252 # Simulator instruction rate (inst/s) +host_op_rate 64242 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1314462 # Simulator tick rate (ticks/s) +host_mem_usage 449728 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1470 # system.mem_ctrls.num_reads::total 1470 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 1466 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 1466 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 814778248 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 814778248 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 812561165 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 812561165 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1627339413 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1627339413 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 817454318 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 817454318 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 815229952 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 815229952 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1632684270 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1632684270 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1470 # Number of read requests accepted system.mem_ctrls.writeReqs 1466 # Number of write requests accepted system.mem_ctrls.readBursts 1470 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 1466 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 59456 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 34624 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 60800 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 58496 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 35584 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 59392 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 94080 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 93824 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 541 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 491 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 556 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 513 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 34 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 32 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 7 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 3 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 13 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 88 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 66 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 248 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 103 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 46 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 103 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 45 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 158 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 15 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 36 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 12 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 78 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 64 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 241 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 97 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 44 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 115 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 43 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 165 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 13 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 33 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::4 7 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 3 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 13 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 76 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 60 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 249 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 103 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 47 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 114 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 44 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 182 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 16 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 11 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 66 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 59 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 245 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 98 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 45 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 118 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 43 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 186 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 14 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 115396 # Total gap between requests +system.mem_ctrls.totGap 115018 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 1466 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 929 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 914 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -135,26 +135,26 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 13 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 17 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 56 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 62 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 60 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 11 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 15 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 55 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 61 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 58 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::20 61 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 59 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 58 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 58 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 58 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 58 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -184,89 +184,89 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 362 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 330.077348 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 218.964738 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 303.831296 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 84 23.20% 23.20% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 104 28.73% 51.93% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 58 16.02% 67.96% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 36 9.94% 77.90% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 19 5.25% 83.15% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 10 2.76% 85.91% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 9 2.49% 88.40% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 5 1.38% 89.78% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 37 10.22% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 362 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 57 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 16.105263 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.953786 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 2.697116 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 1 1.75% 1.75% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 25 43.86% 45.61% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 25 43.86% 89.47% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 5 8.77% 98.25% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::34-35 1 1.75% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 57 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 57 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.666667 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.637263 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.023533 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 37 64.91% 64.91% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 6 10.53% 75.44% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 11 19.30% 94.74% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 2 3.51% 98.25% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 1 1.75% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 57 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 12340 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 29991 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 4645 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 13.28 # Average queueing delay per DRAM burst +system.mem_ctrls.bytesPerActivate::samples 343 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 339.965015 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 217.922152 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 320.777927 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 88 25.66% 25.66% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 98 28.57% 54.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 42 12.24% 66.47% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 32 9.33% 75.80% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 16 4.66% 80.47% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 13 3.79% 84.26% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 8 2.33% 86.59% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 1.46% 88.05% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 41 11.95% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 343 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 56 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 16.125000 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.967614 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 2.737368 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 2 3.57% 3.57% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 19 33.93% 37.50% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 27 48.21% 85.71% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 7 12.50% 98.21% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::34-35 1 1.79% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 56 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 56 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.571429 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.541189 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.041976 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 41 73.21% 73.21% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 3 5.36% 78.57% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 8 14.29% 92.86% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 3 5.36% 98.21% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 1 1.79% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 56 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 12397 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 29763 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 4570 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 13.56 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 32.28 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 514.92 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 526.56 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 814.78 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 812.56 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 32.56 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 508.27 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 516.05 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 817.45 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 815.23 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 8.14 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.02 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 4.11 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 8.00 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 3.97 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.03 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.24 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 618 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 892 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 66.52 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 91.49 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 39.30 # Average gap between requests -system.mem_ctrls.pageHitRate 79.31 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 559440 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 310800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 1684800 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 1327104 # Energy for write commands per rank (pJ) +system.mem_ctrls.avgWrQLen 25.10 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 631 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 861 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 69.04 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 90.35 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 39.18 # Average gap between requests +system.mem_ctrls.pageHitRate 79.91 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 544320 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 302400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1522560 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 1202688 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 54116712 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 18087600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 83206296 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 761.516108 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 29701 # Time in different power states +system.mem_ctrls_0.actBackEnergy 49529808 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 22111200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 82332816 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 753.521892 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 36376 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 3640 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 76066 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 69262 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 2079000 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 1155000 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 9372480 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 7993728 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.actEnergy 1988280 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 1104600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 9397440 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 8076672 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 74259144 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 418800 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 102397992 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 937.161297 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 278 # Time in different power states +system.mem_ctrls_1.actBackEnergy 74119608 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 541200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 102347640 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 936.700469 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1449 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 105360 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 105142 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits @@ -288,7 +288,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 115467 # number of cpu cycles simulated +system.cpu.numCycles 115089 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5624 # Number of instructions committed @@ -307,7 +307,7 @@ system.cpu.num_mem_refs 2034 # nu system.cpu.num_load_insts 1132 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 115467 # Number of busy cycles +system.cpu.num_busy_cycles 115089 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 883 # Number of branches fetched @@ -362,10 +362,10 @@ system.ruby.outstanding_req_hist::total 7659 system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 7658 -system.ruby.latency_hist::mean 14.077958 -system.ruby.latency_hist::gmean 5.242569 -system.ruby.latency_hist::stdev 26.858459 -system.ruby.latency_hist | 7322 95.61% 95.61% | 283 3.70% 99.31% | 37 0.48% 99.79% | 6 0.08% 99.87% | 9 0.12% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::mean 14.028598 +system.ruby.latency_hist::gmean 5.234161 +system.ruby.latency_hist::stdev 27.167008 +system.ruby.latency_hist | 7344 95.90% 95.90% | 261 3.41% 99.31% | 37 0.48% 99.79% | 4 0.05% 99.84% | 9 0.12% 99.96% | 3 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 7658 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 @@ -377,17 +377,17 @@ system.ruby.hit_latency_hist::total 6188 system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1470 -system.ruby.miss_latency_hist::mean 60.710884 -system.ruby.miss_latency_hist::gmean 54.957755 -system.ruby.miss_latency_hist::stdev 32.665540 -system.ruby.miss_latency_hist | 1134 77.14% 77.14% | 283 19.25% 96.39% | 37 2.52% 98.91% | 6 0.41% 99.32% | 9 0.61% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::mean 60.453741 +system.ruby.miss_latency_hist::gmean 54.500138 +system.ruby.miss_latency_hist::stdev 34.320124 +system.ruby.miss_latency_hist | 1156 78.64% 78.64% | 261 17.76% 96.39% | 37 2.52% 98.91% | 4 0.27% 99.18% | 9 0.61% 99.80% | 3 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1470 system.ruby.Directory.incomplete_times 1469 system.ruby.l1_cntrl0.cacheMemory.demand_hits 6188 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1470 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7658 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.356795 +system.ruby.network.routers0.percent_links_utilized 6.377673 system.ruby.network.routers0.msg_count.Control::2 1470 system.ruby.network.routers0.msg_count.Data::2 1466 system.ruby.network.routers0.msg_count.Response_Data::4 1470 @@ -396,7 +396,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 11760 system.ruby.network.routers0.msg_bytes.Data::2 105552 system.ruby.network.routers0.msg_bytes.Response_Data::4 105840 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers1.percent_links_utilized 6.356795 +system.ruby.network.routers1.percent_links_utilized 6.377673 system.ruby.network.routers1.msg_count.Control::2 1470 system.ruby.network.routers1.msg_count.Data::2 1466 system.ruby.network.routers1.msg_count.Response_Data::4 1470 @@ -405,7 +405,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 11760 system.ruby.network.routers1.msg_bytes.Data::2 105552 system.ruby.network.routers1.msg_bytes.Response_Data::4 105840 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.percent_links_utilized 6.356795 +system.ruby.network.routers2.percent_links_utilized 6.377673 system.ruby.network.routers2.msg_count.Control::2 1470 system.ruby.network.routers2.msg_count.Data::2 1466 system.ruby.network.routers2.msg_count.Response_Data::4 1470 @@ -422,32 +422,32 @@ system.ruby.network.msg_byte.Control 35280 system.ruby.network.msg_byte.Data 316656 system.ruby.network.msg_byte.Response_Data 317520 system.ruby.network.msg_byte.Writeback_Control 35184 -system.ruby.network.routers0.throttle0.link_utilization 6.363723 +system.ruby.network.routers0.throttle0.link_utilization 6.384624 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1470 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1466 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 105840 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers0.throttle1.link_utilization 6.349866 +system.ruby.network.routers0.throttle1.link_utilization 6.370722 system.ruby.network.routers0.throttle1.msg_count.Control::2 1470 system.ruby.network.routers0.throttle1.msg_count.Data::2 1466 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11760 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 105552 -system.ruby.network.routers1.throttle0.link_utilization 6.349866 +system.ruby.network.routers1.throttle0.link_utilization 6.370722 system.ruby.network.routers1.throttle0.msg_count.Control::2 1470 system.ruby.network.routers1.throttle0.msg_count.Data::2 1466 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11760 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 105552 -system.ruby.network.routers1.throttle1.link_utilization 6.363723 +system.ruby.network.routers1.throttle1.link_utilization 6.384624 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1470 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1466 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 105840 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.throttle0.link_utilization 6.363723 +system.ruby.network.routers2.throttle0.link_utilization 6.384624 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1470 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1466 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 105840 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.throttle1.link_utilization 6.349866 +system.ruby.network.routers2.throttle1.link_utilization 6.370722 system.ruby.network.routers2.throttle1.msg_count.Control::2 1470 system.ruby.network.routers2.throttle1.msg_count.Data::2 1466 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11760 @@ -462,13 +462,13 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 # system.ruby.delayVCHist.vnet_2::samples 1466 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 1466 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 1466 # delay histogram for vnet_2 -system.ruby.LD.latency_hist::bucket_size 32 -system.ruby.LD.latency_hist::max_bucket 319 +system.ruby.LD.latency_hist::bucket_size 64 +system.ruby.LD.latency_hist::max_bucket 639 system.ruby.LD.latency_hist::samples 1132 -system.ruby.LD.latency_hist::mean 35.492049 -system.ruby.LD.latency_hist::gmean 16.147834 -system.ruby.LD.latency_hist::stdev 37.303839 -system.ruby.LD.latency_hist | 465 41.08% 41.08% | 518 45.76% 86.84% | 124 10.95% 97.79% | 3 0.27% 98.06% | 3 0.27% 98.32% | 12 1.06% 99.38% | 2 0.18% 99.56% | 0 0.00% 99.56% | 3 0.27% 99.82% | 2 0.18% 100.00% +system.ruby.LD.latency_hist::mean 35.838339 +system.ruby.LD.latency_hist::gmean 16.062923 +system.ruby.LD.latency_hist::stdev 41.117345 +system.ruby.LD.latency_hist | 998 88.16% 88.16% | 109 9.63% 97.79% | 13 1.15% 98.94% | 2 0.18% 99.12% | 7 0.62% 99.73% | 3 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist::total 1132 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 @@ -477,21 +477,21 @@ system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 465 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.hit_latency_hist::total 465 -system.ruby.LD.miss_latency_hist::bucket_size 32 -system.ruby.LD.miss_latency_hist::max_bucket 319 +system.ruby.LD.miss_latency_hist::bucket_size 64 +system.ruby.LD.miss_latency_hist::max_bucket 639 system.ruby.LD.miss_latency_hist::samples 667 -system.ruby.LD.miss_latency_hist::mean 58.143928 -system.ruby.LD.miss_latency_hist::gmean 52.206801 -system.ruby.LD.miss_latency_hist::stdev 33.349415 -system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 518 77.66% 77.66% | 124 18.59% 96.25% | 3 0.45% 96.70% | 3 0.45% 97.15% | 12 1.80% 98.95% | 2 0.30% 99.25% | 0 0.00% 99.25% | 3 0.45% 99.70% | 2 0.30% 100.00% +system.ruby.LD.miss_latency_hist::mean 58.731634 +system.ruby.LD.miss_latency_hist::gmean 51.741753 +system.ruby.LD.miss_latency_hist::stdev 39.915394 +system.ruby.LD.miss_latency_hist | 533 79.91% 79.91% | 109 16.34% 96.25% | 13 1.95% 98.20% | 2 0.30% 98.50% | 7 1.05% 99.55% | 3 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 667 system.ruby.ST.latency_hist::bucket_size 32 system.ruby.ST.latency_hist::max_bucket 319 system.ruby.ST.latency_hist::samples 901 -system.ruby.ST.latency_hist::mean 14.748058 -system.ruby.ST.latency_hist::gmean 5.824702 -system.ruby.ST.latency_hist::stdev 24.783906 -system.ruby.ST.latency_hist | 684 75.92% 75.92% | 183 20.31% 96.23% | 29 3.22% 99.45% | 0 0.00% 99.45% | 2 0.22% 99.67% | 2 0.22% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::mean 14.653718 +system.ruby.ST.latency_hist::gmean 5.820052 +system.ruby.ST.latency_hist::stdev 24.674998 +system.ruby.ST.latency_hist | 684 75.92% 75.92% | 188 20.87% 96.78% | 26 2.89% 99.67% | 0 0.00% 99.67% | 0 0.00% 99.67% | 1 0.11% 99.78% | 1 0.11% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% system.ruby.ST.latency_hist::total 901 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 @@ -503,18 +503,18 @@ system.ruby.ST.hit_latency_hist::total 684 system.ruby.ST.miss_latency_hist::bucket_size 32 system.ruby.ST.miss_latency_hist::max_bucket 319 system.ruby.ST.miss_latency_hist::samples 217 -system.ruby.ST.miss_latency_hist::mean 51.778802 -system.ruby.ST.miss_latency_hist::gmean 47.157588 -system.ruby.ST.miss_latency_hist::stdev 27.288529 -system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 183 84.33% 84.33% | 29 13.36% 97.70% | 0 0.00% 97.70% | 2 0.92% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::mean 51.387097 +system.ruby.ST.miss_latency_hist::gmean 47.001474 +system.ruby.ST.miss_latency_hist::stdev 27.408897 +system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 188 86.64% 86.64% | 26 11.98% 98.62% | 0 0.00% 98.62% | 0 0.00% 98.62% | 1 0.46% 99.08% | 1 0.46% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% system.ruby.ST.miss_latency_hist::total 217 -system.ruby.IFETCH.latency_hist::bucket_size 64 -system.ruby.IFETCH.latency_hist::max_bucket 639 +system.ruby.IFETCH.latency_hist::bucket_size 32 +system.ruby.IFETCH.latency_hist::max_bucket 319 system.ruby.IFETCH.latency_hist::samples 5625 -system.ruby.IFETCH.latency_hist::mean 9.661156 -system.ruby.IFETCH.latency_hist::gmean 4.110524 -system.ruby.IFETCH.latency_hist::stdev 22.183687 -system.ruby.IFETCH.latency_hist | 5472 97.28% 97.28% | 127 2.26% 99.54% | 18 0.32% 99.86% | 4 0.07% 99.93% | 3 0.05% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::mean 9.539378 +system.ruby.IFETCH.latency_hist::gmean 4.106431 +system.ruby.IFETCH.latency_hist::stdev 21.247440 +system.ruby.IFETCH.latency_hist | 5039 89.58% 89.58% | 435 7.73% 97.32% | 121 2.15% 99.47% | 5 0.09% 99.56% | 8 0.14% 99.70% | 15 0.27% 99.96% | 1 0.02% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% system.ruby.IFETCH.latency_hist::total 5625 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 @@ -523,21 +523,21 @@ system.ruby.IFETCH.hit_latency_hist::mean 3 system.ruby.IFETCH.hit_latency_hist::gmean 3.000000 system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5039 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.hit_latency_hist::total 5039 -system.ruby.IFETCH.miss_latency_hist::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist::bucket_size 32 +system.ruby.IFETCH.miss_latency_hist::max_bucket 319 system.ruby.IFETCH.miss_latency_hist::samples 586 -system.ruby.IFETCH.miss_latency_hist::mean 66.940273 -system.ruby.IFETCH.miss_latency_hist::gmean 61.663848 -system.ruby.IFETCH.miss_latency_hist::stdev 32.593558 -system.ruby.IFETCH.miss_latency_hist | 433 73.89% 73.89% | 127 21.67% 95.56% | 18 3.07% 98.63% | 4 0.68% 99.32% | 3 0.51% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::mean 65.771331 +system.ruby.IFETCH.miss_latency_hist::gmean 61.076979 +system.ruby.IFETCH.miss_latency_hist::stdev 28.360902 +system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 435 74.23% 74.23% | 121 20.65% 94.88% | 5 0.85% 95.73% | 8 1.37% 97.10% | 15 2.56% 99.66% | 1 0.17% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% system.ruby.IFETCH.miss_latency_hist::total 586 system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1470 -system.ruby.Directory.miss_mach_latency_hist::mean 60.710884 -system.ruby.Directory.miss_mach_latency_hist::gmean 54.957755 -system.ruby.Directory.miss_mach_latency_hist::stdev 32.665540 -system.ruby.Directory.miss_mach_latency_hist | 1134 77.14% 77.14% | 283 19.25% 96.39% | 37 2.52% 98.91% | 6 0.41% 99.32% | 9 0.61% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::mean 60.453741 +system.ruby.Directory.miss_mach_latency_hist::gmean 54.500138 +system.ruby.Directory.miss_mach_latency_hist::stdev 34.320124 +system.ruby.Directory.miss_mach_latency_hist | 1156 78.64% 78.64% | 261 17.76% 96.39% | 37 2.52% 98.91% | 4 0.27% 99.18% | 9 0.61% 99.80% | 3 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1470 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 @@ -565,29 +565,29 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 7 system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 -system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32 -system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319 +system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 667 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 58.143928 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 52.206801 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 33.349415 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 518 77.66% 77.66% | 124 18.59% 96.25% | 3 0.45% 96.70% | 3 0.45% 97.15% | 12 1.80% 98.95% | 2 0.30% 99.25% | 0 0.00% 99.25% | 3 0.45% 99.70% | 2 0.30% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 58.731634 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 51.741753 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 39.915394 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 533 79.91% 79.91% | 109 16.34% 96.25% | 13 1.95% 98.20% | 2 0.30% 98.50% | 7 1.05% 99.55% | 3 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 667 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 217 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 51.778802 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 47.157588 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 27.288529 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 183 84.33% 84.33% | 29 13.36% 97.70% | 0 0.00% 97.70% | 2 0.92% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 51.387097 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 47.001474 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 27.408897 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 188 86.64% 86.64% | 26 11.98% 98.62% | 0 0.00% 98.62% | 0 0.00% 98.62% | 1 0.46% 99.08% | 1 0.46% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist::total 217 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 32 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 586 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 66.940273 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 61.663848 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 32.593558 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 433 73.89% 73.89% | 127 21.67% 95.56% | 18 3.07% 98.63% | 4 0.68% 99.32% | 3 0.51% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 65.771331 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 61.076979 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 28.360902 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 435 74.23% 74.23% | 121 20.65% 94.88% | 5 0.85% 95.73% | 8 1.37% 97.10% | 15 2.56% 99.66% | 1 0.17% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 586 system.ruby.Directory_Controller.GETX 1470 0.00% 0.00% system.ruby.Directory_Controller.PUTX 1466 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 4f23a8939..7140a68cc 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000031 # Nu sim_ticks 30902500 # Number of ticks simulated final_tick 30902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 544856 # Simulator instruction rate (inst/s) -host_op_rate 544118 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2985748792 # Simulator tick rate (ticks/s) -host_mem_usage 288768 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 339265 # Simulator instruction rate (inst/s) +host_op_rate 338999 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1861147916 # Simulator tick rate (ticks/s) +host_mem_usage 289452 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -108,14 +108,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5625 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.155054 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 86.152837 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.155054 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021034 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021034 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.152837 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021033 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021033 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id @@ -186,14 +186,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 137 system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4654500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4654500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2675000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2675000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7329500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7329500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7329500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7329500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4698000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4698000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2700000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2700000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7398000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7398000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7398000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7398000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses @@ -202,24 +202,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 129.101534 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 129.096971 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5331 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.071186 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 129.101534 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063038 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063038 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 129.096971 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.063036 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063036 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id @@ -276,97 +276,102 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 295 system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15699000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15699000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15699000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15699000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15699000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15699000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15846500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15846500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15846500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15846500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15846500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15846500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052435 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052435 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052435 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53216.949153 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53216.949153 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53216.949153 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53216.949153 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53216.949153 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53216.949153 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53716.949153 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53716.949153 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53716.949153 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53716.949153 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53716.949153 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53716.949153 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 183.714965 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 183.690355 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.005263 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.039474 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.257719 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 53.457246 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.238740 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 53.451615 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003975 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001631 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005607 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005606 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011597 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3886 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3886 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 3990 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3990 # Number of data accesses +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 293 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 380 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 293 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 293 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 87 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 87 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 293 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 430 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 293 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses system.cpu.l2cache.overall_misses::total 430 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15383000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4567500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19950500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2625000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2625000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15383000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 15383000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4567500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4567500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 15383000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 7192500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 22575500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 15383000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 7192500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 22575500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 295 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 382 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 295 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 295 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 87 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 87 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 295 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 137 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 432 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 295 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 137 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 432 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993220 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.994764 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993220 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993220 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993220 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.995370 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993220 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995370 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.706485 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.315789 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.706485 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.706485 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52501.162791 # average overall miss latency @@ -381,83 +386,89 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 293 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 380 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 293 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 293 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 87 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 87 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11866500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3523500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15390000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2025000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2025000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11866500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5548500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17415000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11866500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5548500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17415000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994764 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2125000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2125000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12453000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12453000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3697500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3697500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12453000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5822500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18275500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12453000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5822500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18275500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993220 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.995370 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995370 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.706485 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.706485 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.706485 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.162791 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.706485 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.162791 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 382 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 13 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 590 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 295 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 87 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 603 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 864 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 877 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 27648 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 432 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 445 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 432 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 445 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 432 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 216000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 445 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 222500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 442500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.trans_dist::ReadReq 380 # Transaction distribution system.membus.trans_dist::ReadResp 380 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution system.membus.trans_dist::ReadExResp 50 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 380 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index dd15d3497..8f334ebb7 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20101000 # Number of ticks simulated -final_tick 20101000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19998000 # Number of ticks simulated +final_tick 19998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 29548 # Simulator instruction rate (inst/s) -host_op_rate 29545 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 102528509 # Simulator tick rate (ticks/s) -host_mem_usage 221532 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 99740 # Simulator instruction rate (inst/s) +host_op_rate 99716 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 344211505 # Simulator tick rate (ticks/s) +host_mem_usage 290580 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21952 # Nu system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory system.physmem.num_reads::total 444 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1092084971 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 321576041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1413661012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1092084971 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1092084971 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1092084971 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 321576041 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1413661012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1097709771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 323232323 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1420942094 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1097709771 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1097709771 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1097709771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 323232323 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1420942094 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 444 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 19960500 # Total gap between requests +system.physmem.totGap 19858500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 141 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see @@ -188,31 +188,31 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 332.307692 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 193.606609 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.258819 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 194.430832 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 340.544877 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 29 37.18% 37.18% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 17 21.79% 58.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 7 8.97% 67.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 4 5.13% 73.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 4 5.13% 78.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 3 3.85% 82.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 1.28% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4 5.13% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 2.56% 84.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 3.85% 88.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 9 11.54% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation -system.physmem.totQLat 3861750 # Total ticks spent queuing -system.physmem.totMemAccLat 12186750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3950250 # Total ticks spent queuing +system.physmem.totMemAccLat 12275250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8697.64 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8896.96 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27447.64 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1413.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27646.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1420.94 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1413.66 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1420.94 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.04 # Data bus utilization in percentage -system.physmem.busUtilRead 11.04 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.10 # Data bus utilization in percentage +system.physmem.busUtilRead 11.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,44 +220,44 @@ system.physmem.readRowHits 357 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.41 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 44956.08 # Average gap between requests +system.physmem.avgGap 44726.35 # Average gap between requests system.physmem.pageHitRate 80.41 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 461160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 251625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2511600 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 2519400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10794375 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 15068130 # Total energy per rank (pJ) -system.physmem_0.averagePower 951.571203 # Core power per rank (mW) +system.physmem_0.totalEnergy 15077640 # Total energy per rank (pJ) +system.physmem_0.averagePower 952.021468 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15316250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15318750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 68040 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 37125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 288600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 7470990 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2946000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 11827875 # Total energy per rank (pJ) -system.physmem_1.averagePower 747.063003 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 6720750 # Time in different power states +system.physmem_1.actBackEnergy 7492365 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2927250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 11830500 # Total energy per rank (pJ) +system.physmem_1.averagePower 747.228802 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 6597250 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 10486250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 10517250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2330 # Number of BP lookups -system.cpu.branchPred.condPredicted 1881 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2331 # Number of BP lookups +system.cpu.branchPred.condPredicted 1883 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 415 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1929 # Number of BTB lookups -system.cpu.branchPred.BTBHits 660 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1931 # Number of BTB lookups +system.cpu.branchPred.BTBHits 661 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 34.214619 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 34.230968 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 218 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits @@ -279,178 +279,178 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 40203 # number of cpu cycles simulated +system.cpu.numCycles 39997 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7819 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13492 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2330 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 7837 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13501 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2331 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 879 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4287 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 4391 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 863 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 153 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 1828 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 299 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12714 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.061192 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.469867 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 12836 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.051807 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.461524 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10352 81.42% 81.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 189 1.49% 82.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 216 1.70% 84.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 152 1.20% 85.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 247 1.94% 87.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 139 1.09% 88.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 253 1.99% 90.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 114 0.90% 91.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1052 8.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10473 81.59% 81.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 190 1.48% 83.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 215 1.67% 84.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 153 1.19% 85.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 248 1.93% 87.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 135 1.05% 88.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 253 1.97% 90.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 115 0.90% 91.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1054 8.21% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12714 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.057956 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.335597 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7212 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3139 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1951 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 12836 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.058279 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.337550 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7233 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3240 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1952 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 129 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 282 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 336 # Number of times decode resolved a branch +system.cpu.decode.BranchResolved 335 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 150 # Number of times decode detected a branch misprediction system.cpu.decode.DecodedInsts 11562 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 472 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 282 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7370 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 950 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 627 # count of cycles rename stalled for serializing inst +system.cpu.rename.IdleCycles 7391 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 953 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 624 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 1916 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1569 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11201 # Number of instructions processed by rename +system.cpu.rename.UnblockCycles 1670 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11195 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1508 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9631 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18130 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18104 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 1610 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9626 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18124 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18098 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4633 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4628 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 361 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2014 # Number of loads inserted to the mem dependence unit. +system.cpu.rename.skidInsts 362 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2015 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1832 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 10320 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9105 # Number of instructions issued +system.cpu.iq.iqInstsIssued 9101 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 75 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 4591 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3348 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 3358 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12714 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.716140 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.547958 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12836 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.709022 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.537942 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9591 75.44% 75.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 944 7.42% 82.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 633 4.98% 87.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 463 3.64% 91.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 426 3.35% 94.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 301 2.37% 97.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 240 1.89% 99.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 71 0.56% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 45 0.35% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9696 75.54% 75.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 959 7.47% 83.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 638 4.97% 87.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 461 3.59% 91.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 440 3.43% 95.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 291 2.27% 97.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 236 1.84% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 68 0.53% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 47 0.37% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12714 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12836 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11 4.37% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 122 48.41% 52.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 119 47.22% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11 4.38% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 121 48.21% 52.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 119 47.41% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5535 60.79% 60.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 60.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1910 20.98% 81.79% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1658 18.21% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5531 60.77% 60.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 60.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.77% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1910 20.99% 81.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1658 18.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9105 # Type of FU issued -system.cpu.iq.rate 0.226476 # Inst issue rate -system.cpu.iq.fu_busy_cnt 252 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.027677 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31189 # Number of integer instruction queue reads +system.cpu.iq.FU_type_0::total 9101 # Type of FU issued +system.cpu.iq.rate 0.227542 # Inst issue rate +system.cpu.iq.fu_busy_cnt 251 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.027579 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31302 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 14945 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8271 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 8267 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9323 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9318 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1053 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1054 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 786 # Number of stores squashed @@ -460,56 +460,56 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 1 # system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 282 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 870 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 73 # Number of cycles IEW is unblocking +system.cpu.iew.iewBlockCycles 869 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 77 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 10383 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 18 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2014 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2015 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1832 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 62 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 66 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 345 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8701 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 8700 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 1776 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 401 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iew.exec_refs 3330 # number of memory reference insts executed system.cpu.iew.exec_branches 1363 # Number of branches executed system.cpu.iew.exec_stores 1554 # Number of stores executed -system.cpu.iew.exec_rate 0.216427 # Inst execution rate -system.cpu.iew.wb_sent 8428 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8298 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4465 # num instructions producing a value -system.cpu.iew.wb_consumers 7078 # num instructions consuming a value +system.cpu.iew.exec_rate 0.217516 # Inst execution rate +system.cpu.iew.wb_sent 8425 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8294 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4459 # num instructions producing a value +system.cpu.iew.wb_consumers 7044 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.206403 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.630828 # average fanout of values written-back +system.cpu.iew.wb_rate 0.207366 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.633021 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 4593 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 276 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12003 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.482546 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.346027 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12125 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.477691 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.335541 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9841 81.99% 81.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 848 7.06% 89.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 522 4.35% 93.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 225 1.87% 95.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 168 1.40% 96.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 120 1.00% 97.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 110 0.92% 98.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 59 0.49% 99.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 110 0.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9949 82.05% 82.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 859 7.08% 89.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 524 4.32% 93.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 226 1.86% 95.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 182 1.50% 96.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 108 0.89% 97.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 109 0.90% 98.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 59 0.49% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 109 0.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12003 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12125 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -555,60 +555,60 @@ system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5792 # Class of committed instruction -system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22278 # The number of ROB reads +system.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 22401 # The number of ROB reads system.cpu.rob.rob_writes 21482 # The number of ROB writes system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27489 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 27161 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.941126 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.941126 # CPI: Total CPI of All Threads -system.cpu.ipc 0.144069 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.144069 # IPC: Total IPC of All Threads +system.cpu.cpi 6.905559 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.905559 # CPI: Total CPI of All Threads +system.cpu.ipc 0.144811 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.144811 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 13740 # number of integer regfile reads -system.cpu.int_regfile_writes 7173 # number of integer regfile writes +system.cpu.int_regfile_writes 7170 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 63.843132 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2276 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 63.810933 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2272 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22.313725 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22.274510 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 63.843132 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.015587 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.015587 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 63.810933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.015579 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.015579 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1556 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1556 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 720 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 720 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2276 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2276 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2276 # number of overall hits -system.cpu.dcache.overall_hits::total 2276 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 111 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 111 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 326 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 326 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses -system.cpu.dcache.overall_misses::total 437 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8814500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8814500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 30924496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 30924496 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39738996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39738996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39738996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39738996 # number of overall miss cycles +system.cpu.dcache.ReadReq_hits::cpu.data 1553 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1553 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 719 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 719 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2272 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2272 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2272 # number of overall hits +system.cpu.dcache.overall_hits::total 2272 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 114 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 114 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 327 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 327 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 441 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 441 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 441 # number of overall misses +system.cpu.dcache.overall_misses::total 441 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8777500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8777500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 32490996 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 32490996 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41268496 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41268496 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41268496 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41268496 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1667 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1667 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -617,38 +617,38 @@ system.cpu.dcache.demand_accesses::cpu.data 2713 # system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066587 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.066587 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.311663 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.311663 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.161076 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.161076 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.161076 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.161076 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79409.909910 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 79409.909910 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 94860.417178 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 94860.417178 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 90935.917620 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 90935.917620 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 90935.917620 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 90935.917620 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 623 # number of cycles access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.068386 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.068386 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.312620 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.312620 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.162551 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.162551 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.162551 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.162551 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76995.614035 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76995.614035 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99360.844037 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 99360.844037 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 93579.356009 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 93579.356009 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 93579.356009 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 93579.356009 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 627 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 103.833333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 104.500000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 279 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 279 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 335 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 335 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 335 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 335 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 280 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 280 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses @@ -657,14 +657,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4529750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4529750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4417498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4417498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8947248 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8947248 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8947248 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8947248 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4552000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4552000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4551498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4551498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9103498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9103498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9103498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9103498 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032993 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032993 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses @@ -673,27 +673,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037597 system.cpu.dcache.demand_mshr_miss_rate::total 0.037597 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037597 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 82359.090909 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 82359.090909 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 93989.319149 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 93989.319149 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87718.117647 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 87718.117647 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87718.117647 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 87718.117647 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 82763.636364 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 82763.636364 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 96840.382979 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 96840.382979 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89249.980392 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 89249.980392 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89249.980392 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 89249.980392 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 169.362964 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 169.178952 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1389 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.979943 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 169.362964 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.082697 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.082697 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 169.178952 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082607 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082607 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4005 # Number of tag accesses system.cpu.icache.tags.data_accesses 4005 # Number of data accesses @@ -709,12 +709,12 @@ system.cpu.icache.demand_misses::cpu.inst 439 # n system.cpu.icache.demand_misses::total 439 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 439 # number of overall misses system.cpu.icache.overall_misses::total 439 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31975250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31975250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31975250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31975250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31975250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31975250 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31700000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31700000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31700000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31700000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31700000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31700000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1828 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1828 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1828 # number of demand (read+write) accesses @@ -727,17 +727,17 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.240153 system.cpu.icache.demand_miss_rate::total 0.240153 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.240153 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.240153 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72836.560364 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72836.560364 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72836.560364 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72836.560364 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72836.560364 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72836.560364 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 487 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72209.567198 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72209.567198 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72209.567198 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72209.567198 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72209.567198 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72209.567198 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 485 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 97.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 97 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -753,106 +753,112 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 350 system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26127750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26127750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26127750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26127750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26127750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 26127750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26208500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26208500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26208500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26208500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26208500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26208500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191466 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.191466 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.191466 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74650.714286 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74650.714286 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74650.714286 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74650.714286 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74650.714286 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74650.714286 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74881.428571 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74881.428571 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74881.428571 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74881.428571 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74881.428571 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74881.428571 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 199.954316 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 199.713481 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.017632 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.205981 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.748335 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005133 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000969 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006102 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.994608 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.718873 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005127 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000968 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006095 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4060 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4060 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 6 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 6 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 7 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 6 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits system.cpu.l2cache.overall_hits::total 7 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 344 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 54 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 398 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 344 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 344 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 54 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 54 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 445 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses system.cpu.l2cache.overall_misses::total 445 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 25715250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4463750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30179000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4367500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4367500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 25715250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8831250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34546500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 25715250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8831250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34546500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 350 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 405 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4478000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4478000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25621500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 25621500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4458500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4458500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 25621500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8936500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34558000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 25621500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8936500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34558000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 350 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 350 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 55 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 55 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 350 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 452 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 350 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 102 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 452 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.982857 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981818 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.982716 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.982857 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.982857 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.981818 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.981818 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982857 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.990196 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.984513 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982857 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.984513 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74753.633721 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82662.037037 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75826.633166 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92925.531915 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92925.531915 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74753.633721 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87438.118812 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77632.584270 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74753.633721 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87438.118812 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77632.584270 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95276.595745 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95276.595745 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74481.104651 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74481.104651 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82564.814815 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82564.814815 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74481.104651 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88480.198020 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77658.426966 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74481.104651 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88480.198020 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77658.426966 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -861,55 +867,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 398 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 344 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 344 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 54 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 54 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 445 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21441250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3792250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25233500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3785500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3785500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21441250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7577750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29019000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21441250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7577750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 29019000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982716 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4008000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4008000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22191500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22191500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3918500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3918500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22191500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7926500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30118000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22191500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7926500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30118000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.982857 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.981818 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.984513 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.984513 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62329.215116 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70226.851852 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63400.753769 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80542.553191 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80542.553191 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62329.215116 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75027.227723 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65211.235955 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62329.215116 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75027.227723 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65211.235955 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85276.595745 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85276.595745 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64510.174419 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64510.174419 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72564.814815 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72564.814815 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64510.174419 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78480.198020 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67680.898876 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64510.174419 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78480.198020 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67680.898876 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 405 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 350 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 903 # Packet count per connected master and slave (bytes) @@ -930,14 +941,14 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 589250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 165750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 523500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.trans_dist::ReadReq 397 # Transaction distribution system.membus.trans_dist::ReadResp 397 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution system.membus.trans_dist::ReadExResp 47 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 397 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) @@ -953,9 +964,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 444 # Request fanout histogram -system.membus.reqLayer0.occupancy 555000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 550500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 2341000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 2342500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index 51b100b5f..3da0fac46 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000096 # Number of seconds simulated -sim_ticks 95989 # Number of ticks simulated -final_tick 95989 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000095 # Number of seconds simulated +sim_ticks 95241 # Number of ticks simulated +final_tick 95241 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 73101 # Simulator instruction rate (inst/s) -host_op_rate 73087 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1316740 # Simulator tick rate (ticks/s) -host_mem_usage 448980 # Number of bytes of host memory used +host_inst_rate 71470 # Simulator instruction rate (inst/s) +host_op_rate 71456 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1277340 # Simulator tick rate (ticks/s) +host_mem_usage 449880 # Number of bytes of host memory used host_seconds 0.07 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated @@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1289 # system.mem_ctrls.num_reads::total 1289 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 1285 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 1285 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 859431810 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 859431810 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 856764838 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 856764838 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1716196648 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1716196648 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 866181581 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 866181581 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 863493663 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 863493663 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1729675245 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1729675245 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1289 # Number of read requests accepted system.mem_ctrls.writeReqs 1285 # Number of write requests accepted system.mem_ctrls.readBursts 1289 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 1285 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 44736 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 37760 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 45312 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 43328 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 39168 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 43904 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 82496 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 82240 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 590 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 557 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 612 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 580 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 30 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 32 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 16 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 8 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 111 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 113 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 121 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 141 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 57 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 123 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 59 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 34 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 12 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 59 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 23 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 63 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 15 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 11 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 58 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 21 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 61 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 11 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 8 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 31 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 15 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 32 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 16 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 8 # Per bank write bursts system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 111 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 120 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 148 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 59 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 37 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 12 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 59 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 23 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 58 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 18 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 8 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 113 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 127 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 65 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 35 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 11 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 56 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 22 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 66 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 14 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 9 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 95925 # Total gap between requests +system.mem_ctrls.totGap 95177 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 1285 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 699 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 677 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -135,24 +135,24 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 8 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 9 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 36 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 45 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 50 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 47 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 43 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 41 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 43 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 45 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 43 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 45 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 42 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -184,92 +184,92 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 230 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 387.339130 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 262.668395 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 318.441590 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 45 19.57% 19.57% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 51 22.17% 41.74% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 39 16.96% 58.70% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 22 9.57% 68.26% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 23 10.00% 78.26% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 5 2.17% 80.43% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 12 5.22% 85.65% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 9 3.91% 89.57% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 24 10.43% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 230 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 43 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 16.186047 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.978763 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 3.231215 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 22 51.16% 51.16% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 14 32.56% 83.72% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 5 11.63% 95.35% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 1 2.33% 97.67% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::34-35 1 2.33% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 43 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 43 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.465116 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.435760 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.031615 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 35 81.40% 81.40% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 1 2.33% 83.72% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 2 4.65% 88.37% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 5 11.63% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 43 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 8743 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 22024 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3495 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 12.51 # Average queueing delay per DRAM burst +system.mem_ctrls.bytesPerActivate::samples 241 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 353.991701 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 236.521382 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 306.711183 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 49 20.33% 20.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 67 27.80% 48.13% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 30 12.45% 60.58% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 30 12.45% 73.03% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 18 7.47% 80.50% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 7 2.90% 83.40% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 9 3.73% 87.14% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 14 5.81% 92.95% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 17 7.05% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 241 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 42 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 16.047619 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.828866 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 3.297837 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 1 2.38% 2.38% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 18 42.86% 45.24% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 17 40.48% 85.71% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 5 11.90% 97.62% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::34-35 1 2.38% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 42 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 42 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.333333 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.313589 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.845841 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 35 83.33% 83.33% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 3 7.14% 90.48% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 1 2.38% 92.86% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 3 7.14% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 42 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 8633 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 21496 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3385 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 12.75 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 31.51 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 466.05 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 472.05 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 859.43 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 856.76 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 31.75 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 454.93 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 460.98 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 866.18 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 863.49 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 7.33 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 3.64 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 3.69 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 7.16 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 3.55 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 3.60 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.98 # Average write queue length when enqueuing +system.mem_ctrls.avgWrQLen 25.53 # Average write queue length when enqueuing system.mem_ctrls.readRowHits 496 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 676 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 70.96 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 92.86 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 37.27 # Average gap between requests -system.mem_ctrls.pageHitRate 82.13 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 1035720 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 575400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 5229120 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 4271616 # Energy for write commands per rank (pJ) +system.mem_ctrls.writeRowHits 621 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 73.26 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 88.09 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 36.98 # Average gap between requests +system.mem_ctrls.pageHitRate 80.82 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 1141560 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 634200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5079360 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 4178304 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 59194044 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 4292400 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 80701020 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 861.316185 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 6799 # Time in different power states +system.mem_ctrls_0.actBackEnergy 60945084 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 2754600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 80835828 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 862.782607 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 4199 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 3120 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 83841 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 86387 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 672840 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 373800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 3257280 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 2716416 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.actEnergy 680400 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 378000 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 3194880 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 2768256 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 56250108 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 6873000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 76246164 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 813.795884 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 11133 # Time in different power states +system.mem_ctrls_1.actBackEnergy 57004560 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 6211200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 76340016 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 814.797592 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 10140 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 3120 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 79453 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 80556 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 95989 # number of cpu cycles simulated +system.cpu.numCycles 95241 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5327 # Number of instructions committed @@ -288,7 +288,7 @@ system.cpu.num_mem_refs 1401 # nu system.cpu.num_load_insts 723 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0.999990 # Number of idle cycles -system.cpu.num_busy_cycles 95988.000010 # Number of busy cycles +system.cpu.num_busy_cycles 95240.000010 # Number of busy cycles system.cpu.not_idle_fraction 0.999990 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000010 # Percentage of idle cycles system.cpu.Branches 1121 # Number of branches fetched @@ -343,10 +343,10 @@ system.ruby.outstanding_req_hist::total 6759 system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 6758 -system.ruby.latency_hist::mean 13.203759 -system.ruby.latency_hist::gmean 5.149407 -system.ruby.latency_hist::stdev 25.345890 -system.ruby.latency_hist | 6535 96.70% 96.70% | 182 2.69% 99.39% | 30 0.44% 99.84% | 2 0.03% 99.87% | 8 0.12% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::mean 13.093075 +system.ruby.latency_hist::gmean 5.137326 +system.ruby.latency_hist::stdev 25.295268 +system.ruby.latency_hist | 6551 96.94% 96.94% | 168 2.49% 99.42% | 27 0.40% 99.82% | 4 0.06% 99.88% | 3 0.04% 99.93% | 5 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 6758 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 @@ -358,17 +358,17 @@ system.ruby.hit_latency_hist::total 5469 system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1289 -system.ruby.miss_latency_hist::mean 56.496509 -system.ruby.miss_latency_hist::gmean 50.965481 -system.ruby.miss_latency_hist::stdev 32.440273 -system.ruby.miss_latency_hist | 1066 82.70% 82.70% | 182 14.12% 96.82% | 30 2.33% 99.15% | 2 0.16% 99.30% | 8 0.62% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::mean 55.916214 +system.ruby.miss_latency_hist::gmean 50.341721 +system.ruby.miss_latency_hist::stdev 32.999000 +system.ruby.miss_latency_hist | 1082 83.94% 83.94% | 168 13.03% 96.97% | 27 2.09% 99.07% | 4 0.31% 99.38% | 3 0.23% 99.61% | 5 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1289 system.ruby.Directory.incomplete_times 1288 system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.703893 +system.ruby.network.routers0.percent_links_utilized 6.756544 system.ruby.network.routers0.msg_count.Control::2 1289 system.ruby.network.routers0.msg_count.Data::2 1285 system.ruby.network.routers0.msg_count.Response_Data::4 1289 @@ -377,7 +377,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 10312 system.ruby.network.routers0.msg_bytes.Data::2 92520 system.ruby.network.routers0.msg_bytes.Response_Data::4 92808 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers1.percent_links_utilized 6.703893 +system.ruby.network.routers1.percent_links_utilized 6.756544 system.ruby.network.routers1.msg_count.Control::2 1289 system.ruby.network.routers1.msg_count.Data::2 1285 system.ruby.network.routers1.msg_count.Response_Data::4 1289 @@ -386,7 +386,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 10312 system.ruby.network.routers1.msg_bytes.Data::2 92520 system.ruby.network.routers1.msg_bytes.Response_Data::4 92808 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers2.percent_links_utilized 6.703893 +system.ruby.network.routers2.percent_links_utilized 6.756544 system.ruby.network.routers2.msg_count.Control::2 1289 system.ruby.network.routers2.msg_count.Data::2 1285 system.ruby.network.routers2.msg_count.Response_Data::4 1289 @@ -403,32 +403,32 @@ system.ruby.network.msg_byte.Control 30936 system.ruby.network.msg_byte.Data 277560 system.ruby.network.msg_byte.Response_Data 278424 system.ruby.network.msg_byte.Writeback_Control 30840 -system.ruby.network.routers0.throttle0.link_utilization 6.712227 +system.ruby.network.routers0.throttle0.link_utilization 6.764944 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1289 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1285 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 92808 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers0.throttle1.link_utilization 6.695559 +system.ruby.network.routers0.throttle1.link_utilization 6.748144 system.ruby.network.routers0.throttle1.msg_count.Control::2 1289 system.ruby.network.routers0.throttle1.msg_count.Data::2 1285 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 10312 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 92520 -system.ruby.network.routers1.throttle0.link_utilization 6.695559 +system.ruby.network.routers1.throttle0.link_utilization 6.748144 system.ruby.network.routers1.throttle0.msg_count.Control::2 1289 system.ruby.network.routers1.throttle0.msg_count.Data::2 1285 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 10312 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 92520 -system.ruby.network.routers1.throttle1.link_utilization 6.712227 +system.ruby.network.routers1.throttle1.link_utilization 6.764944 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1289 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1285 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 92808 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers2.throttle0.link_utilization 6.712227 +system.ruby.network.routers2.throttle0.link_utilization 6.764944 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1289 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1285 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 92808 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers2.throttle1.link_utilization 6.695559 +system.ruby.network.routers2.throttle1.link_utilization 6.748144 system.ruby.network.routers2.throttle1.msg_count.Control::2 1289 system.ruby.network.routers2.throttle1.msg_count.Data::2 1285 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 10312 @@ -446,10 +446,10 @@ system.ruby.delayVCHist.vnet_2::total 1285 # de system.ruby.LD.latency_hist::bucket_size 32 system.ruby.LD.latency_hist::max_bucket 319 system.ruby.LD.latency_hist::samples 715 -system.ruby.LD.latency_hist::mean 30.924476 -system.ruby.LD.latency_hist::gmean 13.876278 -system.ruby.LD.latency_hist::stdev 34.776798 -system.ruby.LD.latency_hist | 320 44.76% 44.76% | 330 46.15% 90.91% | 50 6.99% 97.90% | 2 0.28% 98.18% | 3 0.42% 98.60% | 6 0.84% 99.44% | 1 0.14% 99.58% | 0 0.00% 99.58% | 2 0.28% 99.86% | 1 0.14% 100.00% +system.ruby.LD.latency_hist::mean 29.991608 +system.ruby.LD.latency_hist::gmean 13.799155 +system.ruby.LD.latency_hist::stdev 30.436552 +system.ruby.LD.latency_hist | 320 44.76% 44.76% | 332 46.43% 91.19% | 50 6.99% 98.18% | 5 0.70% 98.88% | 4 0.56% 99.44% | 4 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist::total 715 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 @@ -461,18 +461,18 @@ system.ruby.LD.hit_latency_hist::total 320 system.ruby.LD.miss_latency_hist::bucket_size 32 system.ruby.LD.miss_latency_hist::max_bucket 319 system.ruby.LD.miss_latency_hist::samples 395 -system.ruby.LD.miss_latency_hist::mean 53.546835 -system.ruby.LD.miss_latency_hist::gmean 47.987716 -system.ruby.LD.miss_latency_hist::stdev 32.331244 -system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 330 83.54% 83.54% | 50 12.66% 96.20% | 2 0.51% 96.71% | 3 0.76% 97.47% | 6 1.52% 98.99% | 1 0.25% 99.24% | 0 0.00% 99.24% | 2 0.51% 99.75% | 1 0.25% 100.00% +system.ruby.LD.miss_latency_hist::mean 51.858228 +system.ruby.LD.miss_latency_hist::gmean 47.506026 +system.ruby.LD.miss_latency_hist::stdev 24.651585 +system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 332 84.05% 84.05% | 50 12.66% 96.71% | 5 1.27% 97.97% | 4 1.01% 98.99% | 4 1.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 395 -system.ruby.ST.latency_hist::bucket_size 32 -system.ruby.ST.latency_hist::max_bucket 319 +system.ruby.ST.latency_hist::bucket_size 64 +system.ruby.ST.latency_hist::max_bucket 639 system.ruby.ST.latency_hist::samples 673 -system.ruby.ST.latency_hist::mean 17.843982 -system.ruby.ST.latency_hist::gmean 6.493774 -system.ruby.ST.latency_hist::stdev 27.592771 -system.ruby.ST.latency_hist | 494 73.40% 73.40% | 145 21.55% 94.95% | 28 4.16% 99.11% | 1 0.15% 99.26% | 2 0.30% 99.55% | 3 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::mean 18.735513 +system.ruby.ST.latency_hist::gmean 6.548753 +system.ruby.ST.latency_hist::stdev 31.370836 +system.ruby.ST.latency_hist | 639 94.95% 94.95% | 25 3.71% 98.66% | 8 1.19% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist::total 673 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 @@ -481,21 +481,21 @@ system.ruby.ST.hit_latency_hist::mean 3 system.ruby.ST.hit_latency_hist::gmean 3.000000 system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 494 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.hit_latency_hist::total 494 -system.ruby.ST.miss_latency_hist::bucket_size 32 -system.ruby.ST.miss_latency_hist::max_bucket 319 +system.ruby.ST.miss_latency_hist::bucket_size 64 +system.ruby.ST.miss_latency_hist::max_bucket 639 system.ruby.ST.miss_latency_hist::samples 179 -system.ruby.ST.miss_latency_hist::mean 58.810056 -system.ruby.ST.miss_latency_hist::gmean 54.709109 -system.ruby.ST.miss_latency_hist::stdev 23.983086 -system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 145 81.01% 81.01% | 28 15.64% 96.65% | 1 0.56% 97.21% | 2 1.12% 98.32% | 3 1.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::mean 62.162011 +system.ruby.ST.miss_latency_hist::gmean 56.471067 +system.ruby.ST.miss_latency_hist::stdev 33.641225 +system.ruby.ST.miss_latency_hist | 145 81.01% 81.01% | 25 13.97% 94.97% | 8 4.47% 99.44% | 0 0.00% 99.44% | 0 0.00% 99.44% | 1 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 179 system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 5370 -system.ruby.IFETCH.latency_hist::mean 10.262756 -system.ruby.IFETCH.latency_hist::gmean 4.383388 -system.ruby.IFETCH.latency_hist::stdev 22.342607 -system.ruby.IFETCH.latency_hist | 5246 97.69% 97.69% | 101 1.88% 99.57% | 16 0.30% 99.87% | 1 0.02% 99.89% | 5 0.09% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::mean 10.135940 +system.ruby.IFETCH.latency_hist::gmean 4.369076 +system.ruby.IFETCH.latency_hist::stdev 22.541685 +system.ruby.IFETCH.latency_hist | 5260 97.95% 97.95% | 88 1.64% 99.59% | 11 0.20% 99.80% | 4 0.07% 99.87% | 3 0.06% 99.93% | 4 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 5370 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 @@ -507,18 +507,18 @@ system.ruby.IFETCH.hit_latency_hist::total 4655 system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 715 -system.ruby.IFETCH.miss_latency_hist::mean 57.546853 -system.ruby.IFETCH.miss_latency_hist::gmean 51.762329 -system.ruby.IFETCH.miss_latency_hist::stdev 34.218674 -system.ruby.IFETCH.miss_latency_hist | 591 82.66% 82.66% | 101 14.13% 96.78% | 16 2.24% 99.02% | 1 0.14% 99.16% | 5 0.70% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::mean 56.594406 +system.ruby.IFETCH.miss_latency_hist::gmean 50.506398 +system.ruby.IFETCH.miss_latency_hist::stdev 36.435131 +system.ruby.IFETCH.miss_latency_hist | 605 84.62% 84.62% | 88 12.31% 96.92% | 11 1.54% 98.46% | 4 0.56% 99.02% | 3 0.42% 99.44% | 4 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 715 system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1289 -system.ruby.Directory.miss_mach_latency_hist::mean 56.496509 -system.ruby.Directory.miss_mach_latency_hist::gmean 50.965481 -system.ruby.Directory.miss_mach_latency_hist::stdev 32.440273 -system.ruby.Directory.miss_mach_latency_hist | 1066 82.70% 82.70% | 182 14.12% 96.82% | 30 2.33% 99.15% | 2 0.16% 99.30% | 8 0.62% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::mean 55.916214 +system.ruby.Directory.miss_mach_latency_hist::gmean 50.341721 +system.ruby.Directory.miss_mach_latency_hist::stdev 32.999000 +system.ruby.Directory.miss_mach_latency_hist | 1082 83.94% 83.94% | 168 13.03% 96.97% | 27 2.09% 99.07% | 4 0.31% 99.38% | 3 0.23% 99.61% | 5 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1289 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 @@ -549,26 +549,26 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::total system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 395 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 53.546835 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 47.987716 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 32.331244 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 330 83.54% 83.54% | 50 12.66% 96.20% | 2 0.51% 96.71% | 3 0.76% 97.47% | 6 1.52% 98.99% | 1 0.25% 99.24% | 0 0.00% 99.24% | 2 0.51% 99.75% | 1 0.25% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 51.858228 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 47.506026 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 24.651585 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 332 84.05% 84.05% | 50 12.66% 96.71% | 5 1.27% 97.97% | 4 1.01% 98.99% | 4 1.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 395 -system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32 -system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319 +system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64 +system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 179 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 58.810056 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 54.709109 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 23.983086 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 145 81.01% 81.01% | 28 15.64% 96.65% | 1 0.56% 97.21% | 2 1.12% 98.32% | 3 1.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 62.162011 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 56.471067 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 33.641225 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 145 81.01% 81.01% | 25 13.97% 94.97% | 8 4.47% 99.44% | 0 0.00% 99.44% | 0 0.00% 99.44% | 1 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist::total 179 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 715 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 57.546853 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 51.762329 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.218674 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 591 82.66% 82.66% | 101 14.13% 96.78% | 16 2.24% 99.02% | 1 0.14% 99.16% | 5 0.70% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 56.594406 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 50.506398 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 36.435131 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 605 84.62% 84.62% | 88 12.31% 96.92% | 11 1.54% 98.46% | 4 0.56% 99.02% | 3 0.42% 99.44% | 4 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 715 system.ruby.Directory_Controller.GETX 1289 0.00% 0.00% system.ruby.Directory_Controller.PUTX 1285 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index f6a7e842c..fd8319ed7 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000028 # Nu sim_ticks 27800500 # Number of ticks simulated final_tick 27800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 510787 # Simulator instruction rate (inst/s) -host_op_rate 510102 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2658808340 # Simulator tick rate (ticks/s) -host_mem_usage 289420 # Number of bytes of host memory used +host_inst_rate 428112 # Simulator instruction rate (inst/s) +host_op_rate 427631 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2229390537 # Simulator tick rate (ticks/s) +host_mem_usage 290104 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated @@ -90,12 +90,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5370 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.114550 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 82.112122 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.114550 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 82.112122 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.020047 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.020047 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id @@ -168,14 +168,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2847000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2847000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4333500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4333500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7180500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7180500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7180500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7180500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2874000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2874000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4374000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4374000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7248000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7248000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7248000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7248000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -184,24 +184,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52722.222222 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52722.222222 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53188.888889 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53188.888889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53188.888889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53188.888889 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53222.222222 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53222.222222 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53688.888889 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53688.888889 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53688.888889 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53688.888889 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 117.036911 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 117.032289 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 117.036911 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057147 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057147 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 117.032289 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057145 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057145 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id @@ -258,100 +258,106 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 257 system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13666000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13666000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13666000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13666000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13666000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13666000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13794500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13794500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13794500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13794500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13794500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13794500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53175.097276 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53175.097276 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53175.097276 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53175.097276 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53175.097276 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53175.097276 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53675.097276 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53675.097276 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53675.097276 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53675.097276 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53675.097276 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53675.097276 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 142.175920 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 142.153744 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.512586 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 25.663334 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003556 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.494223 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 25.659521 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003555 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004339 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004338 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009399 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3525 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3525 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits system.cpu.l2cache.overall_hits::total 3 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 255 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 308 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 255 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 255 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 53 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 53 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 255 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 389 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 389 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13388000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2782500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 16170500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4252500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4252500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13388000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 13388000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2782500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2782500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 13388000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 20423000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 13388000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 20423000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 257 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 311 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 257 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 257 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 54 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 54 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 257 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 392 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 257 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 392 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992218 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981481 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.990354 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.992218 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.992218 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.981481 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.981481 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992218 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.992347 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.960784 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.623377 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.960784 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.960784 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52501.285347 # average overall miss latency @@ -366,55 +372,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 255 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 308 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 255 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 255 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 53 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 53 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 255 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 389 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10327500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2146500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12474000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3280500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3280500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10327500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5427000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15754500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10327500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5427000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15754500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.990354 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3442500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3442500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10838000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10838000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2252500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2252500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10838000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5695000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16533000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10838000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5695000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16533000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.992218 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.981481 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.960784 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.960784 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.960784 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.285347 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.960784 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.285347 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 311 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 257 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 54 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 514 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 784 # Packet count per connected master and slave (bytes) @@ -439,10 +450,10 @@ system.cpu.toL2Bus.respLayer0.occupancy 385500 # La system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.trans_dist::ReadReq 308 # Transaction distribution system.membus.trans_dist::ReadResp 308 # Transaction distribution system.membus.trans_dist::ReadExReq 81 # Transaction distribution system.membus.trans_dist::ReadExResp 81 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 66fb99cb1..ef02c087f 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21143500 # Number of ticks simulated -final_tick 21143500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21012000 # Number of ticks simulated +final_tick 21012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 30354 # Simulator instruction rate (inst/s) -host_op_rate 54988 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 119268705 # Simulator tick rate (ticks/s) -host_mem_usage 303472 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 49067 # Simulator instruction rate (inst/s) +host_op_rate 88883 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 191585973 # Simulator tick rate (ticks/s) +host_mem_usage 310932 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17600 # Nu system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 832407123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 426797834 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1259204957 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 832407123 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 832407123 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 832407123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 426797834 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1259204957 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 837616600 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 429468875 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1267085475 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 837616600 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 837616600 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 837616600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 429468875 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1267085475 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 417 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21095000 # Total gap between requests +system.physmem.totGap 20963500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 244 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,137 +186,137 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 100 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 237.440000 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 159.807528 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 245.488436 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 35 35.00% 35.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 31 31.00% 66.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 16 16.00% 82.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6 6.00% 88.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 2.00% 90.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 3.00% 93.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 2.00% 95.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.00% 96.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4 4.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 100 # Bytes accessed per row activation -system.physmem.totQLat 5105750 # Total ticks spent queuing -system.physmem.totMemAccLat 12924500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 99 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 239.838384 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 160.844462 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 248.938264 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 34 34.34% 34.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 32 32.32% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15 15.15% 81.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 5 5.05% 86.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 2.02% 88.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4 4.04% 92.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 1.01% 93.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 2.02% 95.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4 4.04% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 99 # Bytes accessed per row activation +system.physmem.totQLat 3956500 # Total ticks spent queuing +system.physmem.totMemAccLat 11775250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12244.00 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9488.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30994.00 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1262.23 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28238.01 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1270.13 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1262.23 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1270.13 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.86 # Data bus utilization in percentage -system.physmem.busUtilRead 9.86 # Data bus utilization in percentage for reads +system.physmem.busUtil 9.92 # Data bus utilization in percentage +system.physmem.busUtilRead 9.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.61 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 307 # Number of row buffer hits during reads +system.physmem.readRowHits 308 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.62 # Row buffer hit rate for reads +system.physmem.readRowHitRate 73.86 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 50587.53 # Average gap between requests -system.physmem.pageHitRate 73.62 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 181440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 99000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 936000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 50272.18 # Average gap between requests +system.physmem.pageHitRate 73.86 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 189000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 103125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 951600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 13058475 # Total energy per rank (pJ) -system.physmem_0.averagePower 824.789199 # Core power per rank (mW) +system.physmem_0.totalEnergy 13085760 # Total energy per rank (pJ) +system.physmem_0.averagePower 826.512553 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 438480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 239250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1513200 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 430920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 235125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1521000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10696905 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 116250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14021205 # Total energy per rank (pJ) -system.physmem_1.averagePower 885.596400 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 102500 # Time in different power states +system.physmem_1.actBackEnergy 10315575 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 450750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13970490 # Total energy per rank (pJ) +system.physmem_1.averagePower 882.393179 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 973750 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15223750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14667250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 3414 # Number of BP lookups -system.cpu.branchPred.condPredicted 3414 # Number of conditional branches predicted +system.cpu.branchPred.lookups 3416 # Number of BP lookups +system.cpu.branchPred.condPredicted 3416 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 534 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2533 # Number of BTB lookups -system.cpu.branchPred.BTBHits 863 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2538 # Number of BTB lookups +system.cpu.branchPred.BTBHits 864 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 34.070272 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 34.042553 # BTB Hit Percentage system.cpu.branchPred.usedRAS 247 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 76 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 42288 # number of cpu cycles simulated +system.cpu.numCycles 42025 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12201 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 15496 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3414 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1110 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9718 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1201 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 55 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1161 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 11194 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15490 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3416 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1111 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9646 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1195 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1127 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 2164 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 23748 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.168519 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.673732 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2165 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 22628 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.226003 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.725670 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19483 82.04% 82.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 236 0.99% 83.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 173 0.73% 83.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 257 1.08% 84.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 208 0.88% 85.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 228 0.96% 86.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 337 1.42% 88.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 205 0.86% 88.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2621 11.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18363 81.15% 81.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 236 1.04% 82.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 174 0.77% 82.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 258 1.14% 84.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 208 0.92% 85.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 227 1.00% 86.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 337 1.49% 87.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 205 0.91% 88.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2620 11.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 23748 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.080732 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.366440 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11953 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7408 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3332 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 22628 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.081285 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.368590 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 10919 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7328 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3329 # Number of cycles decode is running system.cpu.decode.UnblockCycles 455 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 600 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 25703 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 600 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 12221 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2293 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 795 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3474 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4365 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 24179 # Number of instructions processed by rename +system.cpu.decode.SquashCycles 597 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 25699 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 597 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 11189 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2276 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 782 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3470 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4314 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 24173 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 93 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 4214 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 27545 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 59275 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 33508 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 4163 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 27542 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 59265 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 33505 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16482 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 16479 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 29 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 1507 # count of insts added to the skid buffer @@ -324,109 +324,109 @@ system.cpu.memDep0.insertedLoads 2438 # Nu system.cpu.memDep0.insertedStores 1611 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21419 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 21416 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17882 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 79 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11697 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16508 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 17876 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 80 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11694 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16519 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 23748 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.752990 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.715169 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 22628 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.789995 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.748596 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 18623 78.42% 78.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1142 4.81% 83.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 888 3.74% 86.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 640 2.69% 89.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 832 3.50% 93.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 584 2.46% 95.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 601 2.53% 98.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 314 1.32% 99.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 124 0.52% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17504 77.36% 77.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1142 5.05% 82.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 891 3.94% 86.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 637 2.82% 89.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 831 3.67% 92.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 584 2.58% 95.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 600 2.65% 98.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 315 1.39% 99.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 124 0.55% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 23748 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 22628 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 173 77.58% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 31 13.90% 91.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19 8.52% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 174 77.68% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 31 13.84% 91.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19 8.48% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14368 80.35% 80.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.39% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2121 11.86% 92.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14362 80.34% 80.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2121 11.87% 92.29% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1379 7.71% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17882 # Type of FU issued -system.cpu.iq.rate 0.422862 # Inst issue rate -system.cpu.iq.fu_busy_cnt 223 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012471 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 59806 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 33148 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16353 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17876 # Type of FU issued +system.cpu.iq.rate 0.425366 # Inst issue rate +system.cpu.iq.fu_busy_cnt 224 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012531 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 58676 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 33142 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16350 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18098 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 18093 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 235 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -439,57 +439,57 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 600 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1925 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 68 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21444 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 597 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1916 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 21441 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2438 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1611 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 60 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 58 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 569 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 694 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16910 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1967 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 972 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 565 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 690 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16903 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1966 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 973 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3249 # number of memory reference insts executed -system.cpu.iew.exec_branches 1660 # Number of branches executed +system.cpu.iew.exec_refs 3248 # number of memory reference insts executed +system.cpu.iew.exec_branches 1659 # Number of branches executed system.cpu.iew.exec_stores 1282 # Number of stores executed -system.cpu.iew.exec_rate 0.399877 # Inst execution rate -system.cpu.iew.wb_sent 16617 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16357 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10994 # num instructions producing a value -system.cpu.iew.wb_consumers 17115 # num instructions consuming a value +system.cpu.iew.exec_rate 0.402213 # Inst execution rate +system.cpu.iew.wb_sent 16611 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16354 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10992 # num instructions producing a value +system.cpu.iew.wb_consumers 17112 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.386800 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.642361 # average fanout of values written-back +system.cpu.iew.wb_rate 0.389149 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.642356 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 11696 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 11693 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 587 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 21784 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.447438 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.339216 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 584 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 20667 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.471621 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.370778 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 18538 85.10% 85.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1010 4.64% 89.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 544 2.50% 92.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 738 3.39% 95.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 369 1.69% 97.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 141 0.65% 97.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 113 0.52% 98.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 72 0.33% 98.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 259 1.19% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17422 84.30% 84.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1008 4.88% 89.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 544 2.63% 91.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 740 3.58% 95.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 368 1.78% 97.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 141 0.68% 97.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 113 0.55% 98.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 72 0.35% 98.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 259 1.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 21784 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 20667 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -536,100 +536,100 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 9747 # Class of committed instruction system.cpu.commit.bw_lim_events 259 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 42968 # The number of ROB reads -system.cpu.rob.rob_writes 44876 # The number of ROB writes +system.cpu.rob.rob_reads 41848 # The number of ROB reads +system.cpu.rob.rob_writes 44866 # The number of ROB writes system.cpu.timesIdled 151 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18540 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 19397 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.860223 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.860223 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127223 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127223 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 21328 # number of integer regfile reads -system.cpu.int_regfile_writes 13105 # number of integer regfile writes +system.cpu.cpi 7.811338 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.811338 # CPI: Total CPI of All Threads +system.cpu.ipc 0.128019 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.128019 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 21318 # number of integer regfile reads +system.cpu.int_regfile_writes 13103 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.cc_regfile_reads 8064 # number of cc regfile reads +system.cpu.cc_regfile_reads 8054 # number of cc regfile reads system.cpu.cc_regfile_writes 5036 # number of cc regfile writes -system.cpu.misc_regfile_reads 7485 # number of misc regfile reads +system.cpu.misc_regfile_reads 7483 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.313704 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2393 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 82.324603 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.971631 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.950355 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.313704 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020096 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020096 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 82.324603 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020099 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020099 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5351 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5351 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1536 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1536 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5349 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5349 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1533 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1533 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 857 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 857 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2393 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2393 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2393 # number of overall hits -system.cpu.dcache.overall_hits::total 2393 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 134 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 134 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2390 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2390 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2390 # number of overall hits +system.cpu.dcache.overall_hits::total 2390 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 136 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 136 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 78 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 78 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 212 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 212 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 212 # number of overall misses -system.cpu.dcache.overall_misses::total 212 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11119000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11119000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6761250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6761250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17880250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17880250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17880250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17880250 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1670 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 214 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 214 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 214 # number of overall misses +system.cpu.dcache.overall_misses::total 214 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10515500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10515500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6241000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6241000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16756500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16756500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16756500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16756500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1669 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1669 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2605 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2605 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2605 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2605 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080240 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.080240 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2604 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2604 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2604 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2604 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081486 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081486 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083422 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.083422 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.081382 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.081382 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.081382 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.081382 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 82977.611940 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 82977.611940 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 86682.692308 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 86682.692308 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 84340.801887 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 84340.801887 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 84340.801887 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 84340.801887 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 236 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.082181 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.082181 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.082181 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.082181 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77319.852941 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 77319.852941 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80012.820513 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80012.820513 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 78301.401869 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 78301.401869 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 78301.401869 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 78301.401869 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 241 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.200000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 70 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 70 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 70 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 70 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 72 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 72 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 72 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 72 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 78 # number of WriteReq MSHR misses @@ -638,82 +638,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5695500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5695500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6612750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6612750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12308250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12308250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12308250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12308250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038323 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038323 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5436500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5436500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6163000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6163000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11599500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11599500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11599500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11599500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038346 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038346 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083422 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054511 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.054511 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054511 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.054511 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88992.187500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88992.187500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84778.846154 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84778.846154 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86677.816901 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 86677.816901 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86677.816901 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 86677.816901 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054531 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.054531 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054531 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.054531 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84945.312500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84945.312500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79012.820513 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79012.820513 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81686.619718 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 81686.619718 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81686.619718 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 81686.619718 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 131.513084 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1796 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 131.388880 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1795 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 276 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.507246 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.503623 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 131.513084 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.064215 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.064215 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 131.388880 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.064155 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.064155 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 276 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4604 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4604 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1796 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1796 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1796 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1796 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1796 # number of overall hits -system.cpu.icache.overall_hits::total 1796 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses -system.cpu.icache.overall_misses::total 368 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28645750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28645750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28645750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28645750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28645750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28645750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2164 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2164 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2164 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2164 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2164 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2164 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.170055 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.170055 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.170055 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.170055 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.170055 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.170055 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77841.711957 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77841.711957 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77841.711957 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77841.711957 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77841.711957 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77841.711957 # average overall miss latency +system.cpu.icache.tags.tag_accesses 4606 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4606 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1795 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1795 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1795 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1795 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1795 # number of overall hits +system.cpu.icache.overall_hits::total 1795 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 370 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 370 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 370 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 370 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 370 # number of overall misses +system.cpu.icache.overall_misses::total 370 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 27513500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 27513500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 27513500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 27513500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 27513500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 27513500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2165 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2165 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2165 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2165 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2165 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2165 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.170901 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.170901 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.170901 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.170901 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.170901 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.170901 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74360.810811 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74360.810811 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74360.810811 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74360.810811 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74360.810811 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74360.810811 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -722,115 +722,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 92 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 276 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 276 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 276 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21933250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21933250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21933250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21933250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21933250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21933250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.127542 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.127542 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.127542 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.127542 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.127542 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.127542 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79468.297101 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79468.297101 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79468.297101 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 79468.297101 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79468.297101 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 79468.297101 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21617000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21617000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21617000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21617000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21617000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21617000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.127483 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.127483 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.127483 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.127483 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.127483 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.127483 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78322.463768 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78322.463768 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78322.463768 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 78322.463768 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78322.463768 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 78322.463768 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 163.168393 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 162.995820 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 338 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002959 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.574096 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.594298 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004015 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000964 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004980 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.424574 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.571246 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004011 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000963 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004974 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 160 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010315 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 275 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 64 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 339 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 78 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 78 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 275 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 275 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 64 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 64 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 275 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 417 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses system.cpu.l2cache.overall_misses::total 417 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21646250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5632500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 27278750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6534750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6534750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21646250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12167250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33813500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21646250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12167250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33813500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 276 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 340 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6046000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6046000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21192000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 21192000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5342000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 5342000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21192000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11388000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32580000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21192000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11388000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32580000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 78 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 78 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 276 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 276 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 64 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 276 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 276 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996377 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997059 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996377 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996377 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996377 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.997608 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996377 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997608 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78713.636364 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88007.812500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 80468.289086 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83778.846154 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83778.846154 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78713.636364 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85684.859155 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81087.529976 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78713.636364 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85684.859155 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81087.529976 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77512.820513 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77512.820513 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77061.818182 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77061.818182 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83468.750000 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83468.750000 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77061.818182 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80197.183099 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78129.496403 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77061.818182 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80197.183099 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78129.496403 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -839,55 +844,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 339 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 78 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 78 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 275 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 275 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 64 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 64 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 417 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18201750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4837000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23038750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5555250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5555250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18201750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10392250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28594000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18201750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10392250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28594000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997059 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5266000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5266000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18442000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18442000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4712000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4712000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18442000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9978000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28420000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18442000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9978000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28420000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996377 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66188.181818 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75578.125000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67960.914454 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71221.153846 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71221.153846 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66188.181818 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73184.859155 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68570.743405 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66188.181818 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73184.859155 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68570.743405 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67512.820513 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67512.820513 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67061.818182 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67061.818182 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73625 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73625 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67061.818182 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70267.605634 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68153.477218 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67061.818182 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70267.605634 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68153.477218 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 78 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 78 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 276 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 64 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 552 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 283 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 835 # Packet count per connected master and slave (bytes) @@ -908,14 +918,14 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 471250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 239250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 339 # Transaction distribution +system.cpu.toL2Bus.respLayer0.occupancy 414000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.membus.trans_dist::ReadResp 338 # Transaction distribution system.membus.trans_dist::ReadExReq 78 # Transaction distribution system.membus.trans_dist::ReadExResp 78 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 339 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) @@ -933,9 +943,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 417 # Request fanout histogram -system.membus.reqLayer0.occupancy 504000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 505000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 2222500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 10.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 2222250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 10.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 6ad7b9146..478e12e63 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000107 # Number of seconds simulated -sim_ticks 107237 # Number of ticks simulated -final_tick 107237 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 107256 # Number of ticks simulated +final_tick 107256 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 59170 # Simulator instruction rate (inst/s) -host_op_rate 107175 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1178869 # Simulator tick rate (ticks/s) -host_mem_usage 466480 # Number of bytes of host memory used +host_inst_rate 57113 # Simulator instruction rate (inst/s) +host_op_rate 103447 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1138055 # Simulator tick rate (ticks/s) +host_mem_usage 467864 # Number of bytes of host memory used host_seconds 0.09 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated @@ -21,59 +21,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1377 # system.mem_ctrls.num_reads::total 1377 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 1373 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 1373 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 821805907 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 821805907 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 819418671 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 819418671 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1641224577 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1641224577 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 821660327 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 821660327 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 819273514 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 819273514 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1640933841 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1640933841 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1377 # Number of read requests accepted system.mem_ctrls.writeReqs 1373 # Number of write requests accepted system.mem_ctrls.readBursts 1377 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 1373 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 42624 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 45504 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 42752 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 43264 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 44864 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 43264 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 88128 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 87872 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 711 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 686 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 701 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 674 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 57 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 56 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 6 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 10 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 51 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 57 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 42 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 64 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 27 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 134 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 126 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 22 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 12 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 54 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 56 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 43 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 70 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 29 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 129 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 124 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 21 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 2 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 28 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 7 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 32 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 34 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 8 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 31 # Per bank write bursts system.mem_ctrls.perBankWrBursts::0 50 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 6 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 10 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 52 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 55 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 44 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 66 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 28 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 133 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 11 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 54 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 54 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 41 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 72 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 30 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 129 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 129 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 22 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 21 # Per bank write bursts system.mem_ctrls.perBankWrBursts::12 2 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 30 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 7 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 33 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 36 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 8 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 32 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 107133 # Total gap between requests +system.mem_ctrls.totGap 107152 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 1373 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 666 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 676 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -135,14 +135,14 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 41 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 7 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 10 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 45 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 43 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 44 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 43 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::23 41 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::24 41 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::25 41 # What write queue length does an incoming req see @@ -184,92 +184,93 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 272 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 306.823529 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 199.088320 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 295.785748 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 71 26.10% 26.10% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 86 31.62% 57.72% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 34 12.50% 70.22% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 20 7.35% 77.57% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 17 6.25% 83.82% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 9 3.31% 87.13% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 11 4.04% 91.18% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 3 1.10% 92.28% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 21 7.72% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 272 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 276 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 306.782609 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 194.488181 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 303.473845 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 80 28.99% 28.99% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 80 28.99% 57.97% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 33 11.96% 69.93% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 22 7.97% 77.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 18 6.52% 84.42% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 7 2.54% 86.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 7 2.54% 89.49% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 4 1.45% 90.94% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 25 9.06% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 276 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 41 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 16.121951 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.902045 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 3.325621 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 2 4.88% 4.88% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 18 43.90% 48.78% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 18 43.90% 92.68% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 2 4.88% 97.56% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 16.243902 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 16.023325 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 3.314970 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 1 2.44% 2.44% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 16 39.02% 41.46% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 18 43.90% 85.37% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 5 12.20% 97.56% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::34-35 1 2.44% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 41 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 41 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.292683 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.274345 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.813754 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 36 87.80% 87.80% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 3 7.32% 95.12% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 2 4.88% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.487805 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.459950 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.003044 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 32 78.05% 78.05% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 2 4.88% 82.93% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 3 7.32% 90.24% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 4 9.76% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 41 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 9844 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 22498 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3330 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 14.78 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 9573 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 22417 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3380 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 14.16 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 33.78 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 397.47 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 398.67 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 821.81 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 819.42 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 33.16 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 403.37 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 403.37 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 821.66 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 819.27 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 6.22 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 3.11 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 3.11 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 6.30 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 3.15 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 3.15 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 26.04 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 427 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 625 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 64.11 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 90.98 # Row buffer hit rate for writes +system.mem_ctrls.avgWrQLen 25.88 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 443 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 622 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 65.53 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 88.98 # Row buffer hit rate for writes system.mem_ctrls.avgGap 38.96 # Average gap between requests -system.mem_ctrls.pageHitRate 77.75 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 695520 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 386400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 3219840 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 2623104 # Energy for write commands per rank (pJ) +system.mem_ctrls.pageHitRate 77.45 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 703080 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 390600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 3319680 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 2685312 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 57895812 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 10101000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 81532956 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 803.454502 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 16443 # Time in different power states +system.mem_ctrls_0.actBackEnergy 57105108 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 10794600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 81609660 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 804.210371 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 17627 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 81669 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 80485 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 1270080 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 705600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 4605120 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 3784320 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.actEnergy 1292760 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 718200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 4630080 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 3805056 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 62916372 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 5697000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 85589772 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 843.431798 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 9164 # Time in different power states +system.mem_ctrls_1.actBackEnergy 62793936 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 5804400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 85655712 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 844.081594 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 9408 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 89065 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 88844 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.apic_clk_domain.clock 16 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 107237 # number of cpu cycles simulated +system.cpu.numCycles 107256 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5381 # Number of instructions committed @@ -290,7 +291,7 @@ system.cpu.num_mem_refs 1988 # nu system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions system.cpu.num_idle_cycles 0.999991 # Number of idle cycles -system.cpu.num_busy_cycles 107236.000009 # Number of busy cycles +system.cpu.num_busy_cycles 107255.000009 # Number of busy cycles system.cpu.not_idle_fraction 0.999991 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000009 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched @@ -345,10 +346,10 @@ system.ruby.outstanding_req_hist::total 8852 system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8852 -system.ruby.latency_hist::mean 11.114437 -system.ruby.latency_hist::gmean 4.638310 -system.ruby.latency_hist::stdev 22.979355 -system.ruby.latency_hist | 8594 97.09% 97.09% | 215 2.43% 99.51% | 29 0.33% 99.84% | 6 0.07% 99.91% | 6 0.07% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::mean 11.116584 +system.ruby.latency_hist::gmean 4.640695 +system.ruby.latency_hist::stdev 22.790037 +system.ruby.latency_hist | 8597 97.12% 97.12% | 214 2.42% 99.54% | 29 0.33% 99.86% | 4 0.05% 99.91% | 5 0.06% 99.97% | 3 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8852 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 @@ -360,17 +361,17 @@ system.ruby.hit_latency_hist::total 7475 system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1377 -system.ruby.miss_latency_hist::mean 55.163399 -system.ruby.miss_latency_hist::gmean 49.389540 -system.ruby.miss_latency_hist::stdev 33.124416 -system.ruby.miss_latency_hist | 1119 81.26% 81.26% | 215 15.61% 96.88% | 29 2.11% 98.98% | 6 0.44% 99.42% | 6 0.44% 99.85% | 2 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::mean 55.177197 +system.ruby.miss_latency_hist::gmean 49.553011 +system.ruby.miss_latency_hist::stdev 32.253276 +system.ruby.miss_latency_hist | 1122 81.48% 81.48% | 214 15.54% 97.02% | 29 2.11% 99.13% | 4 0.29% 99.42% | 5 0.36% 99.78% | 3 0.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1377 system.ruby.Directory.incomplete_times 1376 system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.411034 +system.ruby.network.routers0.percent_links_utilized 6.409898 system.ruby.network.routers0.msg_count.Control::2 1377 system.ruby.network.routers0.msg_count.Data::2 1373 system.ruby.network.routers0.msg_count.Response_Data::4 1377 @@ -379,7 +380,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 11016 system.ruby.network.routers0.msg_bytes.Data::2 98856 system.ruby.network.routers0.msg_bytes.Response_Data::4 99144 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.routers1.percent_links_utilized 6.411034 +system.ruby.network.routers1.percent_links_utilized 6.409898 system.ruby.network.routers1.msg_count.Control::2 1377 system.ruby.network.routers1.msg_count.Data::2 1373 system.ruby.network.routers1.msg_count.Response_Data::4 1377 @@ -388,7 +389,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 11016 system.ruby.network.routers1.msg_bytes.Data::2 98856 system.ruby.network.routers1.msg_bytes.Response_Data::4 99144 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.routers2.percent_links_utilized 6.411034 +system.ruby.network.routers2.percent_links_utilized 6.409898 system.ruby.network.routers2.msg_count.Control::2 1377 system.ruby.network.routers2.msg_count.Data::2 1373 system.ruby.network.routers2.msg_count.Response_Data::4 1377 @@ -405,32 +406,32 @@ system.ruby.network.msg_byte.Control 33048 system.ruby.network.msg_byte.Data 296568 system.ruby.network.msg_byte.Response_Data 297432 system.ruby.network.msg_byte.Writeback_Control 32952 -system.ruby.network.routers0.throttle0.link_utilization 6.418494 +system.ruby.network.routers0.throttle0.link_utilization 6.417357 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 99144 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.routers0.throttle1.link_utilization 6.403573 +system.ruby.network.routers0.throttle1.link_utilization 6.402439 system.ruby.network.routers0.throttle1.msg_count.Control::2 1377 system.ruby.network.routers0.throttle1.msg_count.Data::2 1373 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11016 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 98856 -system.ruby.network.routers1.throttle0.link_utilization 6.403573 +system.ruby.network.routers1.throttle0.link_utilization 6.402439 system.ruby.network.routers1.throttle0.msg_count.Control::2 1377 system.ruby.network.routers1.throttle0.msg_count.Data::2 1373 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11016 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 98856 -system.ruby.network.routers1.throttle1.link_utilization 6.418494 +system.ruby.network.routers1.throttle1.link_utilization 6.417357 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1377 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1373 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 99144 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.routers2.throttle0.link_utilization 6.418494 +system.ruby.network.routers2.throttle0.link_utilization 6.417357 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1377 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1373 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 99144 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.routers2.throttle1.link_utilization 6.403573 +system.ruby.network.routers2.throttle1.link_utilization 6.402439 system.ruby.network.routers2.throttle1.msg_count.Control::2 1377 system.ruby.network.routers2.throttle1.msg_count.Data::2 1373 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11016 @@ -445,13 +446,13 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 # system.ruby.delayVCHist.vnet_2::samples 1373 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 1373 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 1373 # delay histogram for vnet_2 -system.ruby.LD.latency_hist::bucket_size 32 -system.ruby.LD.latency_hist::max_bucket 319 +system.ruby.LD.latency_hist::bucket_size 64 +system.ruby.LD.latency_hist::max_bucket 639 system.ruby.LD.latency_hist::samples 1045 -system.ruby.LD.latency_hist::mean 24.819139 -system.ruby.LD.latency_hist::gmean 10.890845 -system.ruby.LD.latency_hist::stdev 28.082269 -system.ruby.LD.latency_hist | 546 52.25% 52.25% | 414 39.62% 91.87% | 77 7.37% 99.23% | 1 0.10% 99.33% | 2 0.19% 99.52% | 4 0.38% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::mean 24.565550 +system.ruby.LD.latency_hist::gmean 10.818925 +system.ruby.LD.latency_hist::stdev 28.664875 +system.ruby.LD.latency_hist | 965 92.34% 92.34% | 74 7.08% 99.43% | 4 0.38% 99.81% | 1 0.10% 99.90% | 0 0.00% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist::total 1045 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 @@ -460,21 +461,21 @@ system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 546 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.hit_latency_hist::total 546 -system.ruby.LD.miss_latency_hist::bucket_size 32 -system.ruby.LD.miss_latency_hist::max_bucket 319 +system.ruby.LD.miss_latency_hist::bucket_size 64 +system.ruby.LD.miss_latency_hist::max_bucket 639 system.ruby.LD.miss_latency_hist::samples 499 -system.ruby.LD.miss_latency_hist::mean 48.693387 -system.ruby.LD.miss_latency_hist::gmean 44.641812 -system.ruby.LD.miss_latency_hist::stdev 23.667547 -system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 414 82.97% 82.97% | 77 15.43% 98.40% | 1 0.20% 98.60% | 2 0.40% 99.00% | 4 0.80% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::mean 48.162325 +system.ruby.LD.miss_latency_hist::gmean 44.026667 +system.ruby.LD.miss_latency_hist::stdev 25.587548 +system.ruby.LD.miss_latency_hist | 419 83.97% 83.97% | 74 14.83% 98.80% | 4 0.80% 99.60% | 1 0.20% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 499 system.ruby.ST.latency_hist::bucket_size 64 system.ruby.ST.latency_hist::max_bucket 639 system.ruby.ST.latency_hist::samples 935 -system.ruby.ST.latency_hist::mean 16.765775 -system.ruby.ST.latency_hist::gmean 6.381495 -system.ruby.ST.latency_hist::stdev 28.609452 -system.ruby.ST.latency_hist | 895 95.72% 95.72% | 35 3.74% 99.47% | 1 0.11% 99.57% | 2 0.21% 99.79% | 1 0.11% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::mean 16.914439 +system.ruby.ST.latency_hist::gmean 6.394076 +system.ruby.ST.latency_hist::stdev 28.735394 +system.ruby.ST.latency_hist | 895 95.72% 95.72% | 33 3.53% 99.25% | 3 0.32% 99.57% | 2 0.21% 99.79% | 1 0.11% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist::total 935 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 @@ -486,18 +487,18 @@ system.ruby.ST.hit_latency_hist::total 681 system.ruby.ST.miss_latency_hist::bucket_size 64 system.ruby.ST.miss_latency_hist::max_bucket 639 system.ruby.ST.miss_latency_hist::samples 254 -system.ruby.ST.miss_latency_hist::mean 53.673228 -system.ruby.ST.miss_latency_hist::gmean 48.282634 -system.ruby.ST.miss_latency_hist::stdev 33.823763 -system.ruby.ST.miss_latency_hist | 214 84.25% 84.25% | 35 13.78% 98.03% | 1 0.39% 98.43% | 2 0.79% 99.21% | 1 0.39% 99.61% | 1 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::mean 54.220472 +system.ruby.ST.miss_latency_hist::gmean 48.633946 +system.ruby.ST.miss_latency_hist::stdev 33.614512 +system.ruby.ST.miss_latency_hist | 214 84.25% 84.25% | 33 12.99% 97.24% | 3 1.18% 98.43% | 2 0.79% 99.21% | 1 0.39% 99.61% | 1 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 254 system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6864 -system.ruby.IFETCH.latency_hist::mean 8.263112 -system.ruby.IFETCH.latency_hist::gmean 3.900453 -system.ruby.IFETCH.latency_hist::stdev 20.209679 -system.ruby.IFETCH.latency_hist | 6731 98.06% 98.06% | 102 1.49% 99.55% | 22 0.32% 99.87% | 3 0.04% 99.91% | 5 0.07% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::mean 8.284237 +system.ruby.IFETCH.latency_hist::gmean 3.905930 +system.ruby.IFETCH.latency_hist::stdev 19.803554 +system.ruby.IFETCH.latency_hist | 6729 98.03% 98.03% | 107 1.56% 99.59% | 22 0.32% 99.91% | 1 0.01% 99.93% | 4 0.06% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6864 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 @@ -509,10 +510,10 @@ system.ruby.IFETCH.hit_latency_hist::total 6241 system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 623 -system.ruby.IFETCH.miss_latency_hist::mean 60.987159 -system.ruby.IFETCH.miss_latency_hist::gmean 54.083593 -system.ruby.IFETCH.miss_latency_hist::stdev 38.003932 -system.ruby.IFETCH.miss_latency_hist | 490 78.65% 78.65% | 102 16.37% 95.02% | 22 3.53% 98.56% | 3 0.48% 99.04% | 5 0.80% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::mean 61.219904 +system.ruby.IFETCH.miss_latency_hist::gmean 54.926300 +system.ruby.IFETCH.miss_latency_hist::stdev 35.218812 +system.ruby.IFETCH.miss_latency_hist | 488 78.33% 78.33% | 107 17.17% 95.51% | 22 3.53% 99.04% | 1 0.16% 99.20% | 4 0.64% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 623 system.ruby.RMW_Read.latency_hist::bucket_size 4 system.ruby.RMW_Read.latency_hist::max_bucket 39 @@ -540,10 +541,10 @@ system.ruby.RMW_Read.miss_latency_hist::total 1 system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1377 -system.ruby.Directory.miss_mach_latency_hist::mean 55.163399 -system.ruby.Directory.miss_mach_latency_hist::gmean 49.389540 -system.ruby.Directory.miss_mach_latency_hist::stdev 33.124416 -system.ruby.Directory.miss_mach_latency_hist | 1119 81.26% 81.26% | 215 15.61% 96.88% | 29 2.11% 98.98% | 6 0.44% 99.42% | 6 0.44% 99.85% | 2 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::mean 55.177197 +system.ruby.Directory.miss_mach_latency_hist::gmean 49.553011 +system.ruby.Directory.miss_mach_latency_hist::stdev 32.253276 +system.ruby.Directory.miss_mach_latency_hist | 1122 81.48% 81.48% | 214 15.54% 97.02% | 29 2.11% 99.13% | 4 0.29% 99.42% | 5 0.36% 99.78% | 3 0.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1377 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 @@ -571,29 +572,29 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 7 system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 -system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32 -system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319 +system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 499 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 48.693387 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 44.641812 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 23.667547 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 414 82.97% 82.97% | 77 15.43% 98.40% | 1 0.20% 98.60% | 2 0.40% 99.00% | 4 0.80% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 48.162325 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 44.026667 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 25.587548 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 419 83.97% 83.97% | 74 14.83% 98.80% | 4 0.80% 99.60% | 1 0.20% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 499 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 254 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 53.673228 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 48.282634 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 33.823763 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 214 84.25% 84.25% | 35 13.78% 98.03% | 1 0.39% 98.43% | 2 0.79% 99.21% | 1 0.39% 99.61% | 1 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 54.220472 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 48.633946 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 33.614512 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 214 84.25% 84.25% | 33 12.99% 97.24% | 3 1.18% 98.43% | 2 0.79% 99.21% | 1 0.39% 99.61% | 1 0.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist::total 254 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 623 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 60.987159 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 54.083593 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 38.003932 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 490 78.65% 78.65% | 102 16.37% 95.02% | 22 3.53% 98.56% | 3 0.48% 99.04% | 5 0.80% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 61.219904 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 54.926300 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 35.218812 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 488 78.33% 78.33% | 107 17.17% 95.51% | 22 3.53% 99.04% | 1 0.16% 99.20% | 4 0.64% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 623 system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::bucket_size 4 system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::max_bucket 39 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 5185b356a..ef7ce3c79 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 28358500 # Number of ticks simulated final_tick 28358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97635 # Simulator instruction rate (inst/s) -host_op_rate 176805 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 514168344 # Simulator tick rate (ticks/s) -host_mem_usage 251928 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 304372 # Simulator instruction rate (inst/s) +host_op_rate 550952 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1601632215 # Simulator tick rate (ticks/s) +host_mem_usage 308112 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -93,14 +93,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 9748 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 80.793450 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 80.791087 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 80.793450 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019725 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019725 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 80.791087 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.019724 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.019724 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id @@ -171,14 +171,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 134 system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2942500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2942500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4226500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4226500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7169000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7169000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7169000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7169000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2970000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2970000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4266000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4266000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7236000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7236000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7236000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7236000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses @@ -187,24 +187,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 105.544338 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 105.540319 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 105.544338 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.051535 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.051535 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 105.540319 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.051533 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.051533 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id @@ -261,33 +261,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 228 system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12156500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12156500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12156500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12156500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12156500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12156500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12270500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12270500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12270500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12270500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12270500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12270500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53317.982456 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53317.982456 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53317.982456 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53317.982456 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53317.982456 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53317.982456 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53817.982456 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53817.982456 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53817.982456 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53817.982456 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53817.982456 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53817.982456 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 134.026823 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 134.006917 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.552484 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.474338 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.536457 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.470460 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy @@ -297,61 +297,66 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 167 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008606 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3257 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 227 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 282 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 227 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 227 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 55 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 227 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 361 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 361 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11918000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2887500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14805500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4147500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4147500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11918000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 11918000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2887500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2887500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 11918000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 18953000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 11918000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 18953000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 228 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 283 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 228 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 228 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 55 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 55 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 228 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 134 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 362 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 228 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 134 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 362 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.996466 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.995614 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.997238 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52502.202643 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.773050 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52502.202643 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52502.202643 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.202643 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52501.385042 # average overall miss latency @@ -366,55 +371,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 227 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 282 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 227 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 227 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 55 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9193500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2227500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11421000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3199500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3199500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9193500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5427000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14620500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9193500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5427000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14620500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996466 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3357500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3357500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9648000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9648000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2337500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2337500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9648000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5695000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15343000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9648000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5695000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15343000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995614 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42502.202643 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42502.202643 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42502.202643 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.385042 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42502.202643 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.385042 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 228 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 724 # Packet count per connected master and slave (bytes) @@ -439,10 +449,10 @@ system.cpu.toL2Bus.respLayer0.occupancy 342000 # La system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.trans_dist::ReadReq 282 # Transaction distribution system.membus.trans_dist::ReadResp 282 # Transaction distribution system.membus.trans_dist::ReadExReq 79 # Transaction distribution system.membus.trans_dist::ReadExResp 79 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 282 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) |