diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/quick/se/00.hello/ref | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/quick/se/00.hello/ref')
24 files changed, 4755 insertions, 4613 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index 20c464e74..5987fdc63 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000038 # Number of seconds simulated -sim_ticks 37822000 # Number of ticks simulated -final_tick 37822000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 38282000 # Number of ticks simulated +final_tick 38282000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 100508 # Simulator instruction rate (inst/s) -host_op_rate 100471 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 592356577 # Simulator tick rate (ticks/s) -host_mem_usage 249008 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 159466 # Simulator instruction rate (inst/s) +host_op_rate 159415 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 951356890 # Simulator tick rate (ticks/s) +host_mem_usage 253388 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 6413 # Number of instructions simulated sim_ops 6413 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10816 # Number of bytes read from this memory system.physmem.bytes_read::total 34048 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 23232 # Nu system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory system.physmem.num_reads::total 532 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 614245677 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 285971128 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 900216805 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 614245677 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 614245677 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 614245677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 285971128 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 900216805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 606864845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 282534873 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 889399718 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 606864845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 606864845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 606864845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 282534873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 889399718 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 532 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 532 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 37718000 # Total gap between requests +system.physmem.totGap 38177000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -187,71 +187,71 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 82 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 385.560976 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 252.880176 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.081835 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 17 20.73% 20.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 21 25.61% 46.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 10.98% 57.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 11 13.41% 70.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 4.88% 75.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 3.66% 79.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 3.66% 82.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5 6.10% 89.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 10.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 82 # Bytes accessed per row activation -system.physmem.totQLat 3215000 # Total ticks spent queuing -system.physmem.totMemAccLat 13190000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 83 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 377.831325 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 247.256857 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.629090 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18 21.69% 21.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 20 24.10% 45.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11 13.25% 59.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 11 13.25% 72.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 3.61% 75.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4 4.82% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 3.61% 84.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4 4.82% 89.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 10.84% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 83 # Bytes accessed per row activation +system.physmem.totQLat 3252000 # Total ticks spent queuing +system.physmem.totMemAccLat 13227000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2660000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6043.23 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6112.78 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24793.23 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 900.22 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24862.78 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 889.40 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 900.22 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 889.40 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.03 # Data bus utilization in percentage -system.physmem.busUtilRead 7.03 # Data bus utilization in percentage for reads +system.physmem.busUtil 6.95 # Data bus utilization in percentage +system.physmem.busUtilRead 6.95 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 438 # Number of row buffer hits during reads +system.physmem.readRowHits 437 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.33 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.14 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 70898.50 # Average gap between requests -system.physmem.pageHitRate 82.33 # Row buffer hit rate, read and write combined +system.physmem.avgGap 71761.28 # Average gap between requests +system.physmem.pageHitRate 82.14 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 2020200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 21404070 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25911645 # Total energy per rank (pJ) -system.physmem_0.averagePower 825.080242 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 366250 # Time in different power states +system.physmem_0.actBackEnergy 21270690 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 184500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25871865 # Total energy per rank (pJ) +system.physmem_0.averagePower 823.813565 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 196750 # Time in different power states system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 30363250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 30182000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 340200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 185625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1521000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 347760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 189750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1505400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 20148930 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1168500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 25398495 # Total energy per rank (pJ) -system.physmem_1.averagePower 808.740487 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1794750 # Time in different power states +system.physmem_1.actBackEnergy 20078820 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1230000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 25385970 # Total energy per rank (pJ) +system.physmem_1.averagePower 808.341665 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2146500 # Time in different power states system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 28584000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 28481000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 2005 # Number of BP lookups system.cpu.branchPred.condPredicted 1239 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 379 # Number of conditional branches incorrect @@ -299,16 +299,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 37822000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 75644 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 38282000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 76564 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6413 # Number of instructions committed system.cpu.committedOps 6413 # Number of ops (including micro ops) committed system.cpu.discardedOps 1095 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 11.795416 # CPI: cycles per instruction -system.cpu.ipc 0.084779 # IPC: instructions per cycle +system.cpu.cpi 11.938874 # CPI: cycles per instruction +system.cpu.ipc 0.083760 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction system.cpu.op_class_0::IntAlu 4331 67.53% 67.83% # Class of committed instruction system.cpu.op_class_0::IntMult 1 0.02% 67.85% # Class of committed instruction @@ -345,24 +345,24 @@ system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 6413 # Class of committed instruction system.cpu.tickCycles 12651 # Number of cycles that the object actually ticked -system.cpu.idleCycles 62993 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states +system.cpu.idleCycles 63913 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.701168 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.736314 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1990 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.775148 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.701168 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025318 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025318 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.736314 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025326 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025326 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4591 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4591 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1250 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1250 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits @@ -379,14 +379,14 @@ system.cpu.dcache.demand_misses::cpu.data 221 # n system.cpu.dcache.demand_misses::total 221 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 221 # number of overall misses system.cpu.dcache.overall_misses::total 221 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7590000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7590000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9158000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9158000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16748000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16748000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16748000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16748000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7713000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7713000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9281000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9281000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16994000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16994000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16994000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16994000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1346 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1346 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -403,14 +403,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.099955 system.cpu.dcache.demand_miss_rate::total 0.099955 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.099955 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.099955 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79062.500000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 79062.500000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73264 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73264 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75782.805430 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75782.805430 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75782.805430 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75782.805430 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 80343.750000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 80343.750000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74248 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74248 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76895.927602 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76895.927602 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76895.927602 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76895.927602 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -431,14 +431,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 169 system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7494000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7494000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5379500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5379500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12873500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12873500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12873500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12873500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7617000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7617000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5452500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5452500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13069500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13069500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13069500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13069500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071322 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071322 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -447,31 +447,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076436 system.cpu.dcache.demand_mshr_miss_rate::total 0.076436 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076436 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.076436 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78062.500000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78062.500000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73691.780822 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73691.780822 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76174.556213 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76174.556213 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76174.556213 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76174.556213 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79343.750000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79343.750000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74691.780822 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74691.780822 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77334.319527 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77334.319527 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77334.319527 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77334.319527 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 174.485780 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 174.445567 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2322 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 364 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 6.379121 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 174.485780 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.085198 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.085198 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 174.445567 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.085178 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.085178 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.177734 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 5736 # Number of tag accesses system.cpu.icache.tags.data_accesses 5736 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 2322 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2322 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2322 # number of demand (read+write) hits @@ -484,12 +484,12 @@ system.cpu.icache.demand_misses::cpu.inst 364 # n system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28087500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28087500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28087500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28087500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28087500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28087500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28460500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28460500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28460500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28460500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28460500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28460500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2686 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2686 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2686 # number of demand (read+write) accesses @@ -502,12 +502,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.135517 system.cpu.icache.demand_miss_rate::total 0.135517 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.135517 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.135517 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77163.461538 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77163.461538 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77163.461538 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77163.461538 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77163.461538 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77163.461538 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78188.186813 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 78188.186813 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 78188.186813 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 78188.186813 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 78188.186813 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 78188.186813 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -520,43 +520,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 364 system.cpu.icache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 364 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27723500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27723500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27723500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27723500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27723500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27723500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28096500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 28096500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28096500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 28096500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28096500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 28096500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135517 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.135517 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.135517 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76163.461538 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76163.461538 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76163.461538 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 76163.461538 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76163.461538 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 76163.461538 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77188.186813 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77188.186813 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77188.186813 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 77188.186813 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77188.186813 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 77188.186813 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 232.271171 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 278.242026 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 459 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002179 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 532 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.001880 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 174.500375 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.770796 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005325 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001763 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007088 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014008 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 174.459359 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 103.782667 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005324 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.003167 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.008491 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 532 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 407 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.016235 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4796 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4796 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -575,18 +575,18 @@ system.cpu.l2cache.demand_misses::total 532 # nu system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses system.cpu.l2cache.overall_misses::total 532 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5270000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5270000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27166000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 27166000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7348500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7348500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27166000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12618500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 39784500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27166000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12618500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 39784500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5343000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5343000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27539000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 27539000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7471500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7471500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27539000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12814500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 40353500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27539000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12814500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 40353500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 364 # number of ReadCleanReq accesses(hits+misses) @@ -611,18 +611,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.998124 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997253 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.998124 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72191.780822 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72191.780822 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74837.465565 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74837.465565 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76546.875000 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76546.875000 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74837.465565 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74665.680473 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74782.894737 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74837.465565 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74665.680473 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74782.894737 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73191.780822 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73191.780822 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75865.013774 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75865.013774 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77828.125000 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77828.125000 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75865.013774 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75825.443787 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75852.443609 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75865.013774 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75825.443787 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75852.443609 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -641,18 +641,18 @@ system.cpu.l2cache.demand_mshr_misses::total 532 system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 532 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4540000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4540000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23536000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23536000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6388500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6388500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23536000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10928500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 34464500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23536000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10928500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 34464500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4613000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4613000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23909000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23909000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6511500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6511500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23909000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11124500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 35033500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23909000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11124500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 35033500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for ReadCleanReq accesses @@ -665,25 +665,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.998124 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.998124 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62191.780822 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62191.780822 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64837.465565 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64837.465565 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66546.875000 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66546.875000 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64837.465565 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64665.680473 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64782.894737 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64837.465565 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64665.680473 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64782.894737 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63191.780822 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63191.780822 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65865.013774 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65865.013774 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67828.125000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67828.125000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65865.013774 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65825.443787 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65852.443609 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65865.013774 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65825.443787 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65852.443609 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 533 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 460 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution @@ -714,7 +714,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 546000 # La system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 253500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 532 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 459 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution @@ -738,6 +744,6 @@ system.membus.snoop_fanout::total 532 # Re system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) system.membus.respLayer1.occupancy 2826500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 7.5 # Layer utilization (%) +system.membus.respLayer1.utilization 7.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 0781260bf..1341b2242 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 22019000 # Number of ticks simulated -final_tick 22019000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 22248000 # Number of ticks simulated +final_tick 22248000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122018 # Simulator instruction rate (inst/s) -host_op_rate 121990 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 420608458 # Simulator tick rate (ticks/s) -host_mem_usage 250288 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 114507 # Simulator instruction rate (inst/s) +host_op_rate 114481 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 398824007 # Simulator tick rate (ticks/s) +host_mem_usage 254412 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 6385 # Number of instructions simulated sim_ops 6385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory system.physmem.bytes_read::total 31040 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 19968 # Nu system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory system.physmem.num_reads::total 485 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 906853172 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 502838458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1409691630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 906853172 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 906853172 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 906853172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 502838458 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1409691630 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 897518878 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 497662711 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1395181589 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 897518878 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 897518878 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 897518878 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 497662711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1395181589 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 485 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 485 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21881000 # Total gap between requests +system.physmem.totGap 22109000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -92,8 +92,8 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -188,76 +188,76 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 353.684211 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 230.878571 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 321.867393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 352.842105 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 230.159600 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 321.021248 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 18 23.68% 23.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 19 25.00% 48.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10 13.16% 61.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 10 13.16% 75.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5 6.58% 81.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 2.63% 84.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 11.84% 60.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 11 14.47% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 6 7.89% 82.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 1.32% 84.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 2 2.63% 86.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 13.16% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation -system.physmem.totQLat 4444750 # Total ticks spent queuing -system.physmem.totMemAccLat 13538500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 4498250 # Total ticks spent queuing +system.physmem.totMemAccLat 13592000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2425000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9164.43 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9274.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27914.43 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1409.69 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28024.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1395.18 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1409.69 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1395.18 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.01 # Data bus utilization in percentage -system.physmem.busUtilRead 11.01 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.90 # Data bus utilization in percentage +system.physmem.busUtilRead 10.90 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.74 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 394 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.24 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45115.46 # Average gap between requests +system.physmem.avgGap 45585.57 # Average gap between requests system.physmem.pageHitRate 81.24 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1653600 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 1645800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 10785825 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 13798605 # Total energy per rank (pJ) -system.physmem_0.averagePower 871.536712 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 297750 # Time in different power states +system.physmem_0.totalEnergy 13790805 # Total energy per rank (pJ) +system.physmem_0.averagePower 871.044055 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 294840 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 160875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1271400 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 1255800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10085580 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 657000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13486815 # Total energy per rank (pJ) -system.physmem_1.averagePower 851.440341 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1024500 # Time in different power states +system.physmem_1.actBackEnergy 10074465 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 662250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13465350 # Total energy per rank (pJ) +system.physmem_1.averagePower 850.487920 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1034500 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14308250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14291750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2849 # Number of BP lookups -system.cpu.branchPred.condPredicted 1676 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 2853 # Number of BP lookups +system.cpu.branchPred.condPredicted 1680 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 481 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2197 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 2201 # Number of BTB lookups system.cpu.branchPred.BTBHits 713 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.453345 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 32.394366 # BTB Hit Percentage system.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 41 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 461 # Number of indirect predictor lookups. @@ -281,10 +281,10 @@ system.cpu.dtb.data_hits 3300 # DT system.cpu.dtb.data_misses 76 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 3376 # DTB accesses -system.cpu.itb.fetch_hits 2293 # ITB hits +system.cpu.itb.fetch_hits 2294 # ITB hits system.cpu.itb.fetch_misses 27 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2320 # ITB accesses +system.cpu.itb.fetch_accesses 2321 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -298,65 +298,65 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 22019000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 44039 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 22248000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 44497 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8533 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16533 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2849 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 8475 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16557 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2853 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 1180 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 5068 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 5121 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1044 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 654 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2293 # Number of cache lines fetched +system.cpu.fetch.PendingTrapStallCycles 656 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2294 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 333 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14799 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.117170 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.500450 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 14796 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.119019 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.502117 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11815 79.84% 79.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 299 2.02% 81.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 232 1.57% 83.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 256 1.73% 85.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 292 1.97% 87.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 232 1.57% 88.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 283 1.91% 90.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 144 0.97% 91.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1246 8.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11808 79.81% 79.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 299 2.02% 81.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 232 1.57% 83.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 257 1.74% 85.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 292 1.97% 87.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 233 1.57% 88.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 283 1.91% 90.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 144 0.97% 91.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1248 8.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14799 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.064693 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.375417 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8370 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3320 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2446 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 14796 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.064117 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.372093 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8328 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3356 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2449 # Number of cycles decode is running system.cpu.decode.UnblockCycles 215 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 448 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 226 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14994 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 15018 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 221 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 448 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8529 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1727 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 614 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2478 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1003 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14444 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 8488 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1745 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 620 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2480 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1015 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14460 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 937 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 10925 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17893 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17884 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 949 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 10938 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17913 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17904 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4577 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6348 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6361 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 28 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 585 # count of insts added to the skid buffer @@ -364,109 +364,109 @@ system.cpu.memDep0.insertedLoads 2839 # Nu system.cpu.memDep0.insertedStores 1293 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 18 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 13053 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 13069 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10776 # Number of instructions issued +system.cpu.iq.iqInstsIssued 10787 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6694 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3672 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 6710 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3679 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14799 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.728157 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.465404 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14796 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.729048 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.467428 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10757 72.69% 72.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1297 8.76% 81.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 917 6.20% 87.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 680 4.59% 92.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 523 3.53% 95.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 348 2.35% 98.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 194 1.31% 99.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10757 72.70% 72.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1291 8.73% 81.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 918 6.20% 87.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 680 4.60% 92.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 521 3.52% 95.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 349 2.36% 98.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 197 1.33% 99.44% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 55 0.37% 99.81% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 28 0.19% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14799 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14796 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 19 13.77% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 82 59.42% 73.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 37 26.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 21 15.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 82 58.57% 73.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 37 26.43% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7177 66.60% 66.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.63% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2482 23.03% 89.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1112 10.32% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7188 66.64% 66.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2482 23.01% 89.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1112 10.31% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10776 # Type of FU issued -system.cpu.iq.rate 0.244692 # Inst issue rate -system.cpu.iq.fu_busy_cnt 138 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012806 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 36485 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19785 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9739 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10787 # Type of FU issued +system.cpu.iq.rate 0.242421 # Inst issue rate +system.cpu.iq.fu_busy_cnt 140 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012979 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 36506 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19817 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9751 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10901 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10914 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 119 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -480,54 +480,54 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 1 # system.cpu.iew.lsq.thread0.cacheBlocked 89 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 448 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1371 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 296 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13164 # Number of instructions dispatched to IQ +system.cpu.iew.iewBlockCycles 1381 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 302 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 13180 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2839 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1293 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 289 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 295 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 23 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 390 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 497 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10291 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 10303 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 2309 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 485 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 484 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 84 # number of nop insts executed system.cpu.iew.exec_refs 3386 # number of memory reference insts executed -system.cpu.iew.exec_branches 1641 # Number of branches executed +system.cpu.iew.exec_branches 1643 # Number of branches executed system.cpu.iew.exec_stores 1077 # Number of stores executed -system.cpu.iew.exec_rate 0.233679 # Inst execution rate -system.cpu.iew.wb_sent 9945 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9749 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5139 # num instructions producing a value -system.cpu.iew.wb_consumers 7002 # num instructions consuming a value -system.cpu.iew.wb_rate 0.221372 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.733933 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 6711 # The number of squashed insts skipped by commit +system.cpu.iew.exec_rate 0.231544 # Inst execution rate +system.cpu.iew.wb_sent 9957 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9761 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5150 # num instructions producing a value +system.cpu.iew.wb_consumers 7013 # num instructions consuming a value +system.cpu.iew.wb_rate 0.219363 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.734350 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 6727 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 407 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13565 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.471950 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.389989 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 13560 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.472124 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.390428 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11138 82.11% 82.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1158 8.54% 90.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11134 82.11% 82.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1157 8.53% 90.64% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 469 3.46% 94.10% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 205 1.51% 95.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 134 0.99% 96.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 84 0.62% 97.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 133 0.98% 96.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 85 0.63% 97.22% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 96 0.71% 97.93% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 89 0.66% 98.58% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 192 1.42% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13565 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13560 # Number of insts commited each cycle system.cpu.commit.committedInsts 6402 # Number of instructions committed system.cpu.commit.committedOps 6402 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -574,63 +574,63 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 6402 # Class of committed instruction system.cpu.commit.bw_lim_events 192 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 26135 # The number of ROB reads -system.cpu.rob.rob_writes 27477 # The number of ROB writes -system.cpu.timesIdled 253 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29240 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 26146 # The number of ROB reads +system.cpu.rob.rob_writes 27511 # The number of ROB writes +system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29701 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6385 # Number of Instructions Simulated system.cpu.committedOps 6385 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.897259 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.897259 # CPI: Total CPI of All Threads -system.cpu.ipc 0.144985 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.144985 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12924 # number of integer regfile reads -system.cpu.int_regfile_writes 7434 # number of integer regfile writes +system.cpu.cpi 6.968990 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.968990 # CPI: Total CPI of All Threads +system.cpu.ipc 0.143493 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.143493 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12938 # number of integer regfile reads +system.cpu.int_regfile_writes 7444 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 109.409218 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2405 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 109.756228 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2407 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.901734 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.913295 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 109.409218 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026711 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026711 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 109.756228 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026796 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026796 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1899 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1899 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2405 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2405 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2405 # number of overall hits -system.cpu.dcache.overall_hits::total 2405 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 508 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 508 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2407 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2407 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2407 # number of overall hits +system.cpu.dcache.overall_hits::total 2407 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 180 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 180 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 539 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 539 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 539 # number of overall misses -system.cpu.dcache.overall_misses::total 539 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12774500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12774500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23738475 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23738475 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 36512975 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 36512975 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 36512975 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 36512975 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 357 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 357 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 537 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 537 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 537 # number of overall misses +system.cpu.dcache.overall_misses::total 537 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12910000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12910000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24562475 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24562475 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 37472475 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 37472475 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 37472475 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 37472475 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2079 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2079 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -641,34 +641,34 @@ system.cpu.dcache.overall_accesses::cpu.data 2944 system.cpu.dcache.overall_accesses::total 2944 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086580 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.086580 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.183084 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.183084 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.183084 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.183084 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70969.444444 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70969.444444 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66123.885794 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66123.885794 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67742.068646 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67742.068646 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67742.068646 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67742.068646 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2423 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412717 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.412717 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.182405 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.182405 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.182405 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.182405 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71722.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71722.222222 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68802.450980 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 68802.450980 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69781.145251 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69781.145251 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69781.145251 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69781.145251 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2459 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 43 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 56.348837 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.186047 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 366 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 366 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 366 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 366 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 285 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 285 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 364 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 364 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 364 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses @@ -677,14 +677,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 173 system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8466000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8466000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5695500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5695500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14161500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14161500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14161500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14161500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8568000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8568000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6031500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6031500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14599500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14599500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14599500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14599500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048581 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048581 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses @@ -693,122 +693,122 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058764 system.cpu.dcache.demand_mshr_miss_rate::total 0.058764 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058764 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.058764 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83821.782178 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83821.782178 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79104.166667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79104.166667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81858.381503 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 81858.381503 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81858.381503 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 81858.381503 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84831.683168 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84831.683168 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83770.833333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83770.833333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84390.173410 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84390.173410 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84390.173410 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84390.173410 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 158.432951 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1836 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 159.084059 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1838 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 313 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.865815 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.872204 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 158.432951 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077360 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077360 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 159.084059 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077678 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077678 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 313 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.152832 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4899 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4899 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1836 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1836 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1836 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1836 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1836 # number of overall hits -system.cpu.icache.overall_hits::total 1836 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 457 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 457 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 457 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 457 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 457 # number of overall misses -system.cpu.icache.overall_misses::total 457 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32838500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32838500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32838500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32838500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32838500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32838500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2293 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2293 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2293 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2293 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2293 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2293 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199302 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.199302 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.199302 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.199302 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.199302 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.199302 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71856.673961 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71856.673961 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71856.673961 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71856.673961 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71856.673961 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71856.673961 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 54 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 4901 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4901 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1838 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1838 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1838 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1838 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1838 # number of overall hits +system.cpu.icache.overall_hits::total 1838 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 456 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 456 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 456 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 456 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 456 # number of overall misses +system.cpu.icache.overall_misses::total 456 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32999500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32999500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32999500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32999500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32999500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32999500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2294 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2294 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2294 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2294 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2294 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2294 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.198779 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.198779 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.198779 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.198779 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.198779 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.198779 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72367.324561 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72367.324561 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72367.324561 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72367.324561 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72367.324561 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72367.324561 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 56 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 54 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 56 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 144 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 144 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 144 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 144 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 144 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 144 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 143 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 143 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 143 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 143 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 143 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 143 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24470500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24470500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24470500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24470500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24470500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24470500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136502 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136502 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136502 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.136502 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136502 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.136502 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78180.511182 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78180.511182 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78180.511182 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 78180.511182 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78180.511182 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 78180.511182 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24573000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24573000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24573000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24573000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24573000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24573000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136443 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136443 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136443 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.136443 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136443 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.136443 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78507.987220 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78507.987220 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78507.987220 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 78507.987220 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78507.987220 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 78507.987220 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 220.994877 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 268.962928 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 413 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002421 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 485 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002062 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.475596 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 62.519281 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004836 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001908 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006744 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 413 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012604 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.125052 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 109.837876 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004856 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.003352 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.008208 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 485 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014801 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4373 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4373 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -827,18 +827,18 @@ system.cpu.l2cache.demand_misses::total 485 # nu system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses system.cpu.l2cache.overall_misses::total 485 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5584500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5584500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 23987500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 23987500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8306000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 8306000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23987500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13890500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 37878000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23987500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13890500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 37878000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5920500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5920500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 24090000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 24090000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8408000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 8408000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 24090000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 14328500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 38418500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 24090000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 14328500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 38418500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 313 # number of ReadCleanReq accesses(hits+misses) @@ -863,18 +863,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.997942 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997942 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77562.500000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77562.500000 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76883.012821 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76883.012821 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82237.623762 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82237.623762 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76883.012821 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80291.907514 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78098.969072 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76883.012821 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80291.907514 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78098.969072 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82229.166667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82229.166667 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77211.538462 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77211.538462 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83247.524752 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83247.524752 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77211.538462 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82823.699422 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79213.402062 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77211.538462 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82823.699422 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79213.402062 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -893,18 +893,18 @@ system.cpu.l2cache.demand_mshr_misses::total 485 system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 485 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4864500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4864500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20867500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20867500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7296000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7296000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20867500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12160500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 33028000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20867500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12160500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 33028000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5200500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5200500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20970000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20970000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7398000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7398000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20970000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12598500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 33568500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20970000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12598500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 33568500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadCleanReq accesses @@ -917,25 +917,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997942 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67562.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67562.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66883.012821 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66883.012821 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72237.623762 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72237.623762 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66883.012821 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70291.907514 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68098.969072 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66883.012821 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70291.907514 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68098.969072 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72229.166667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72229.166667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67211.538462 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67211.538462 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73247.524752 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73247.524752 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67211.538462 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72823.699422 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69213.402062 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67211.538462 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72823.699422 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69213.402062 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 486 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 414 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution @@ -966,7 +966,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 469500 # La system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 485 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 413 # Transaction distribution system.membus.trans_dist::ReadExReq 72 # Transaction distribution system.membus.trans_dist::ReadExResp 72 # Transaction distribution @@ -987,9 +993,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 485 # Request fanout histogram -system.membus.reqLayer0.occupancy 590500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 591500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 2579250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 2578750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt index 724287a51..f237b4325 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 3214500 # Number of ticks simulated final_tick 3214500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1026789 # Simulator instruction rate (inst/s) -host_op_rate 1024872 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 513643962 # Simulator tick rate (ticks/s) -host_mem_usage 238508 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 280584 # Simulator instruction rate (inst/s) +host_op_rate 280421 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 140703848 # Simulator tick rate (ticks/s) +host_mem_usage 242116 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -130,6 +130,12 @@ system.cpu.op_class::MemWrite 868 13.54% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6413 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 3214500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7598 # Transaction distribution system.membus.trans_dist::ReadResp 7598 # Transaction distribution @@ -144,14 +150,14 @@ system.membus.pkt_size::total 41152 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 8463 # Request fanout histogram -system.membus.snoop_fanout::mean 0.757769 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.428459 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2050 24.22% 24.22% # Request fanout histogram -system.membus.snoop_fanout::1 6413 75.78% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 8463 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 8463 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index d4fc31bad..ffd6a3082 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000036 # Number of seconds simulated -sim_ticks 35682500 # Number of ticks simulated -final_tick 35682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 36128500 # Number of ticks simulated +final_tick 36128500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 318235 # Simulator instruction rate (inst/s) -host_op_rate 317806 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1768975757 # Simulator tick rate (ticks/s) -host_mem_usage 248500 # Number of bytes of host memory used +host_inst_rate 310790 # Simulator instruction rate (inst/s) +host_op_rate 310669 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1752338800 # Simulator tick rate (ticks/s) +host_mem_usage 252108 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory system.physmem.bytes_read::total 28544 # Number of bytes read from this memory @@ -22,15 +22,15 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 498619772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 301324179 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 799943950 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 498619772 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498619772 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 498619772 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 301324179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 799943950 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 492464398 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 297604384 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 790068782 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 492464398 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 492464398 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 492464398 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 297604384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 790068782 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -65,8 +65,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 35682500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 71365 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 36128500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 72257 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6403 # Number of instructions committed @@ -85,7 +85,7 @@ system.cpu.num_mem_refs 2060 # nu system.cpu.num_load_insts 1192 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 71365 # Number of busy cycles +system.cpu.num_busy_cycles 72257 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1056 # Number of branches fetched @@ -124,23 +124,23 @@ system.cpu.op_class::MemWrite 868 13.54% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6413 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.763836 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.721081 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1882 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.202381 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.763836 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.721081 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025323 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025323 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4268 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4268 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits @@ -157,14 +157,14 @@ system.cpu.dcache.demand_misses::cpu.data 168 # n system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses system.cpu.dcache.overall_misses::total 168 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5890000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5890000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4526000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4526000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10416000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 10416000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 10416000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 10416000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5985000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5985000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4599000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4599000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10584000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10584000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10584000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10584000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -181,14 +181,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.081951 system.cpu.dcache.demand_miss_rate::total 0.081951 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.081951 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.081951 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -203,14 +203,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5795000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5795000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4453000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4453000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10248000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10248000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10248000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10248000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5890000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5890000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4526000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4526000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10416000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10416000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10416000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10416000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -219,31 +219,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 system.cpu.dcache.demand_mshr_miss_rate::total 0.081951 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.081951 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 127.232065 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 127.170991 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6135 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 21.989247 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 127.232065 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.062125 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.062125 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 127.170991 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.062095 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.062095 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 13107 # Number of tag accesses system.cpu.icache.tags.data_accesses 13107 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 6135 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6135 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6135 # number of demand (read+write) hits @@ -256,12 +256,12 @@ system.cpu.icache.demand_misses::cpu.inst 279 # n system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses system.cpu.icache.overall_misses::total 279 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17250500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17250500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17250500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17250500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17250500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17250500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17528500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17528500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17528500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17528500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17528500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17528500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6414 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6414 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6414 # number of demand (read+write) accesses @@ -274,12 +274,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043499 system.cpu.icache.demand_miss_rate::total 0.043499 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.043499 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.043499 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61829.749104 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61829.749104 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61829.749104 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61829.749104 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61829.749104 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61829.749104 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62826.164875 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62826.164875 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62826.164875 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62826.164875 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62826.164875 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62826.164875 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -292,43 +292,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 279 system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16971500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16971500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16971500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16971500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16971500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16971500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17249500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17249500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17249500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17249500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17249500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17249500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043499 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.043499 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.043499 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60829.749104 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60829.749104 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61826.164875 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61826.164875 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61826.164875 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61826.164875 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61826.164875 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61826.164875 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 184.000496 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 230.937880 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 446 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002242 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.230075 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.770421 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003883 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001732 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005615 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011383 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.167974 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 103.769906 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003881 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.003167 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007048 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 446 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013611 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -347,18 +347,18 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4343500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4343500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16541500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 16541500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5652500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 5652500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16541500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9996000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 26537500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16541500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9996000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 26537500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4416500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4416500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16819500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 16819500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5747500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 5747500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16819500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10164000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 26983500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16819500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10164000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 26983500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 279 # number of ReadCleanReq accesses(hits+misses) @@ -383,18 +383,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.997763 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.798561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.798561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59501.121076 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59501.121076 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.798561 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.798561 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.798561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60501.121076 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.798561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60501.121076 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -413,18 +413,18 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3613500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3613500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13761500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13761500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4702500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4702500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13761500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8316000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22077500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13761500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8316000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22077500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3686500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3686500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14039500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14039500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4797500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4797500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14039500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8484000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22523500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14039500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8484000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22523500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadCleanReq accesses @@ -437,25 +437,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.798561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.798561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.798561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.798561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.798561 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.121076 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.798561 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.121076 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 447 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution @@ -486,7 +486,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 418500 # La system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 446 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 373 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution @@ -508,7 +514,7 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 446 # Request fanout histogram system.membus.reqLayer0.occupancy 446500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) system.membus.respLayer1.occupancy 2230000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 6.2 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index ac371de2b..95775a988 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20329000 # Number of ticks simulated -final_tick 20329000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000021 # Number of seconds simulated +sim_ticks 20616000 # Number of ticks simulated +final_tick 20616000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113549 # Simulator instruction rate (inst/s) -host_op_rate 113428 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 891182571 # Simulator tick rate (ticks/s) -host_mem_usage 248724 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 91304 # Simulator instruction rate (inst/s) +host_op_rate 91266 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 727585147 # Simulator tick rate (ticks/s) +host_mem_usage 252076 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory system.physmem.bytes_read::total 19840 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 310 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 708347681 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 267598013 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 975945693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 708347681 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 708347681 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 708347681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 267598013 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 975945693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 698486612 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 263872720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 962359333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 698486612 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 698486612 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 698486612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 263872720 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 962359333 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 310 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 310 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20241500 # Total gap between requests +system.physmem.totGap 20527500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -188,70 +188,70 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 41 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 429.268293 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 281.421645 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.320856 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 424.585366 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 277.937119 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 331.553388 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 10 24.39% 24.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 6 14.63% 39.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4 9.76% 48.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3 7.32% 56.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5 12.20% 51.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2 4.88% 56.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 6 14.63% 70.73% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 2 4.88% 75.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 4 9.76% 85.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 3 7.32% 92.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 3 7.32% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation -system.physmem.totQLat 1774250 # Total ticks spent queuing -system.physmem.totMemAccLat 7586750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1590750 # Total ticks spent queuing +system.physmem.totMemAccLat 7403250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1550000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5723.39 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5131.45 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24473.39 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 975.95 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23881.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 962.36 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 975.95 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 962.36 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.62 # Data bus utilization in percentage -system.physmem.busUtilRead 7.62 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.52 # Data bus utilization in percentage +system.physmem.busUtilRead 7.52 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 260 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.87 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 65295.16 # Average gap between requests +system.physmem.avgGap 66217.74 # Average gap between requests system.physmem.pageHitRate 83.87 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 83160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 45375 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 787800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10557540 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 238500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 12729495 # Total energy per rank (pJ) -system.physmem_0.averagePower 804.010422 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 825750 # Time in different power states +system.physmem_0.actBackEnergy 10790100 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12758055 # Total energy per rank (pJ) +system.physmem_0.averagePower 805.814306 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 727750 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 14971750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15310750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 189000 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1185600 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 1162200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10490850 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 299250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13284945 # Total energy per rank (pJ) -system.physmem_1.averagePower 838.894625 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 457000 # Time in different power states +system.physmem_1.actBackEnergy 10417320 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 361500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13250265 # Total energy per rank (pJ) +system.physmem_1.averagePower 836.902890 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 560000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14872250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14766250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 794 # Number of BP lookups system.cpu.branchPred.condPredicted 394 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 170 # Number of conditional branches incorrect @@ -299,16 +299,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 20329000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 40658 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 20616000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 41232 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2585 # Number of instructions committed system.cpu.committedOps 2585 # Number of ops (including micro ops) committed system.cpu.discardedOps 573 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 15.728433 # CPI: cycles per instruction -system.cpu.ipc 0.063579 # IPC: instructions per cycle +system.cpu.cpi 15.950484 # CPI: cycles per instruction +system.cpu.ipc 0.062694 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 189 7.31% 7.31% # Class of committed instruction system.cpu.op_class_0::IntAlu 1678 64.91% 72.22% # Class of committed instruction system.cpu.op_class_0::IntMult 1 0.04% 72.26% # Class of committed instruction @@ -344,25 +344,25 @@ system.cpu.op_class_0::MemWrite 298 11.53% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 2585 # Class of committed instruction -system.cpu.tickCycles 5421 # Number of cycles that the object actually ticked -system.cpu.idleCycles 35237 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 5423 # Number of cycles that the object actually ticked +system.cpu.idleCycles 35809 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 48.302993 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 48.342284 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.141176 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 48.302993 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011793 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011793 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 48.342284 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011802 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011802 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1673 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1673 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 441 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 441 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 251 # number of WriteReq hits @@ -379,14 +379,14 @@ system.cpu.dcache.demand_misses::cpu.data 102 # n system.cpu.dcache.demand_misses::total 102 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 102 # number of overall misses system.cpu.dcache.overall_misses::total 102 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4783500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4783500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3258000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3258000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8041500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8041500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8041500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8041500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4617500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4617500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3301000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3301000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7918500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7918500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7918500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7918500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 500 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 500 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -403,14 +403,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.128463 system.cpu.dcache.demand_miss_rate::total 0.128463 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.128463 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.128463 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81076.271186 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 81076.271186 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75767.441860 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75767.441860 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 78838.235294 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 78838.235294 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 78838.235294 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 78838.235294 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78262.711864 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 78262.711864 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76767.441860 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76767.441860 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 77632.352941 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77632.352941 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 77632.352941 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 77632.352941 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -433,14 +433,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4654000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4654000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2017500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2017500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6671500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6671500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6671500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6671500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4487000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4487000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2044500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2044500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6531500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6531500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6531500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6531500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.116000 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.116000 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses @@ -449,31 +449,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.107053 system.cpu.dcache.demand_mshr_miss_rate::total 0.107053 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.107053 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.107053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80241.379310 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80241.379310 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74722.222222 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74722.222222 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78488.235294 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78488.235294 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78488.235294 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78488.235294 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77362.068966 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77362.068966 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75722.222222 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75722.222222 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76841.176471 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76841.176471 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76841.176471 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76841.176471 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 119.197826 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 119.307121 # Cycle average of tags in use system.cpu.icache.tags.total_refs 754 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 225 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.351111 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 119.197826 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.058202 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.058202 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 119.307121 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.058255 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.058255 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 225 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.109863 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 2183 # Number of tag accesses system.cpu.icache.tags.data_accesses 2183 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 754 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 754 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 754 # number of demand (read+write) hits @@ -486,12 +486,12 @@ system.cpu.icache.demand_misses::cpu.inst 225 # n system.cpu.icache.demand_misses::total 225 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 225 # number of overall misses system.cpu.icache.overall_misses::total 225 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17116000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17116000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17116000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17116000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17116000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17116000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17383000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17383000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17383000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17383000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17383000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17383000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 979 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 979 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 979 # number of demand (read+write) accesses @@ -504,12 +504,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.229826 system.cpu.icache.demand_miss_rate::total 0.229826 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.229826 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.229826 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76071.111111 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76071.111111 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76071.111111 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76071.111111 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76071.111111 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76071.111111 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77257.777778 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77257.777778 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77257.777778 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77257.777778 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77257.777778 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77257.777778 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -522,43 +522,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 225 system.cpu.icache.demand_mshr_misses::total 225 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 225 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16891000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16891000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16891000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16891000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16891000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16891000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17158000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17158000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17158000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17158000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17158000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17158000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.229826 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.229826 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.229826 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.229826 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.229826 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.229826 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75071.111111 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75071.111111 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75071.111111 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75071.111111 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75071.111111 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75071.111111 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76257.777778 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76257.777778 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76257.777778 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76257.777778 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 147.090026 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 167.807293 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 283 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 310 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 119.314039 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 27.775987 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003641 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000848 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004489 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 283 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008636 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 119.421716 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48.385576 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003644 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001477 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005121 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 310 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009460 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2790 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2790 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 225 # number of ReadCleanReq misses @@ -571,18 +571,18 @@ system.cpu.l2cache.demand_misses::total 310 # nu system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 310 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1977000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1977000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16553500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 16553500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4566000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4566000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16553500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6543000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23096500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16553500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6543000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23096500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2004000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2004000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16820500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 16820500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4399000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4399000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16820500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6403000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23223500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16820500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6403000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23223500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 225 # number of ReadCleanReq accesses(hits+misses) @@ -607,18 +607,18 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73222.222222 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73222.222222 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73571.111111 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73571.111111 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78724.137931 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78724.137931 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73571.111111 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76976.470588 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74504.838710 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73571.111111 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76976.470588 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74504.838710 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74222.222222 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74222.222222 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74757.777778 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74757.777778 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75844.827586 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75844.827586 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74757.777778 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75329.411765 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74914.516129 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74757.777778 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75329.411765 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74914.516129 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -637,18 +637,18 @@ system.cpu.l2cache.demand_mshr_misses::total 310 system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 310 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1707000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1707000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14303500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14303500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3986000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3986000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14303500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5693000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19996500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14303500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5693000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19996500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1734000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1734000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14570500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14570500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3819000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3819000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14570500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5553000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20123500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14570500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5553000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20123500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses @@ -661,25 +661,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63222.222222 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63222.222222 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63571.111111 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63571.111111 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68724.137931 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68724.137931 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63571.111111 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66976.470588 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64504.838710 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63571.111111 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66976.470588 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64504.838710 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64222.222222 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64222.222222 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64757.777778 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64757.777778 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65844.827586 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65844.827586 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64757.777778 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65329.411765 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64914.516129 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64757.777778 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65329.411765 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64914.516129 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 310 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution @@ -707,10 +707,16 @@ system.cpu.toL2Bus.snoop_fanout::total 310 # Re system.cpu.toL2Bus.reqLayer0.occupancy 155000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 337500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 310 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 283 # Transaction distribution system.membus.trans_dist::ReadExReq 27 # Transaction distribution system.membus.trans_dist::ReadExResp 27 # Transaction distribution @@ -733,7 +739,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 310 # Request fanout histogram system.membus.reqLayer0.occupancy 363000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 1648250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 8.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 1648750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 8.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 51e8f72d6..cdae5e837 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12409500 # Number of ticks simulated -final_tick 12409500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 12542500 # Number of ticks simulated +final_tick 12542500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95060 # Simulator instruction rate (inst/s) -host_op_rate 95002 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 493600045 # Simulator tick rate (ticks/s) -host_mem_usage 248984 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 60996 # Simulator instruction rate (inst/s) +host_op_rate 60977 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 320317516 # Simulator tick rate (ticks/s) +host_mem_usage 253100 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory system.physmem.bytes_read::total 17408 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 11968 # Nu system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 964422418 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 438373827 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1402796245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 964422418 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 964422418 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 964422418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 438373827 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1402796245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 954195735 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 433725334 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1387921068 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 954195735 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 954195735 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 954195735 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 433725334 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1387921068 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 272 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 272 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 12313000 # Total gap between requests +system.physmem.totGap 12445000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 81 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 80 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -188,9 +188,9 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 36 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 398.222222 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 237.741650 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 358.174986 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 394.666667 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 235.952583 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 357.320824 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 12 33.33% 33.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 5 13.89% 47.22% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 3 8.33% 55.56% # Bytes accessed per row activation @@ -201,37 +201,37 @@ system.physmem.bytesPerActivate::768-895 2 5.56% 83.33% # By system.physmem.bytesPerActivate::896-1023 1 2.78% 86.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 13.89% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 36 # Bytes accessed per row activation -system.physmem.totQLat 1652750 # Total ticks spent queuing -system.physmem.totMemAccLat 6752750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1866000 # Total ticks spent queuing +system.physmem.totMemAccLat 6966000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6076.29 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6860.29 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24826.29 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1402.80 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25610.29 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1387.92 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1402.80 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1387.92 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.96 # Data bus utilization in percentage -system.physmem.busUtilRead 10.96 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.84 # Data bus utilization in percentage +system.physmem.busUtilRead 10.84 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 226 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45268.38 # Average gap between requests +system.physmem.avgGap 45753.68 # Average gap between requests system.physmem.pageHitRate 83.09 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 68040 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 37125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 592800 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 585000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 5478840 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 21750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 6707115 # Total energy per rank (pJ) -system.physmem_0.averagePower 833.570297 # Core power per rank (mW) +system.physmem_0.totalEnergy 6699315 # Total energy per rank (pJ) +system.physmem_0.averagePower 832.600901 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states system.physmem_0.memoryStateTime::REF 260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states @@ -239,31 +239,31 @@ system.physmem_0.memoryStateTime::ACT 7777500 # Ti system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 787800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5200965 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 265500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 6969270 # Total energy per rank (pJ) -system.physmem_1.averagePower 866.151313 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 708000 # Time in different power states +system.physmem_1.actBackEnergy 5198400 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 267750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 6961155 # Total energy per rank (pJ) +system.physmem_1.averagePower 865.142768 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 432500 # Time in different power states system.physmem_1.memoryStateTime::REF 260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7371500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7367500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 1003 # Number of BP lookups +system.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 1001 # Number of BP lookups system.cpu.branchPred.condPredicted 492 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 213 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 688 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 687 # Number of BTB lookups system.cpu.branchPred.BTBHits 176 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 25.581395 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 221 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 25.618632 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 220 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 18 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 101 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 100 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 3 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 98 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 97 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 33 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -282,10 +282,10 @@ system.cpu.dtb.data_hits 1061 # DT system.cpu.dtb.data_misses 30 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations system.cpu.dtb.data_accesses 1091 # DTB accesses -system.cpu.itb.fetch_hits 878 # ITB hits +system.cpu.itb.fetch_hits 877 # ITB hits system.cpu.itb.fetch_misses 32 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 910 # ITB accesses +system.cpu.itb.fetch_accesses 909 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,53 +299,53 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 12409500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 24820 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 12542500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 25086 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4371 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6065 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1003 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 400 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1173 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 4377 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6059 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1001 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 399 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1174 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 472 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1146 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1154 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 878 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 6955 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.872035 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.274710 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 877 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 147 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 6970 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.869297 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.271813 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5922 85.15% 85.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 27 0.39% 85.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 100 1.44% 86.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 87 1.25% 88.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 141 2.03% 90.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 81 1.16% 91.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 46 0.66% 92.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 76 1.09% 93.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 475 6.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5938 85.19% 85.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 27 0.39% 85.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 100 1.43% 87.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 87 1.25% 88.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 141 2.02% 90.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 81 1.16% 91.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 45 0.65% 92.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 76 1.09% 93.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 475 6.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6955 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.040411 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.244359 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5210 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 623 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 6970 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.039903 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.241529 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5221 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 627 # Number of cycles decode is blocked system.cpu.decode.RunCycles 919 # Number of cycles decode is running system.cpu.decode.UnblockCycles 40 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 163 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 145 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction system.cpu.decode.DecodedInsts 5274 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 268 # Number of squashed instructions handled by decode +system.cpu.decode.SquashedInsts 263 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 163 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5285 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 327 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 288 # count of cycles rename stalled for serializing inst +system.cpu.rename.IdleCycles 5296 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 881 # Number of cycles rename is running system.cpu.rename.UnblockCycles 11 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 5069 # Number of instructions processed by rename @@ -371,23 +371,23 @@ system.cpu.iq.iqSquashedInstsIssued 28 # Nu system.cpu.iq.iqSquashedInstsExamined 2005 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 1025 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 6955 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.540331 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.279888 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 6970 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.539168 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.278867 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5508 79.19% 79.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 469 6.74% 85.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 342 4.92% 90.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 254 3.65% 94.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 193 2.77% 97.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 103 1.48% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 56 0.81% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5524 79.25% 79.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 467 6.70% 85.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 343 4.92% 90.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 254 3.64% 94.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 193 2.77% 97.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 103 1.48% 98.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 56 0.80% 99.57% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 20 0.29% 99.86% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 10 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 6955 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 6970 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 6 9.84% 9.84% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 9.84% # attempts to use FU when none available @@ -457,10 +457,10 @@ system.cpu.iq.FU_type_0::MemWrite 373 9.93% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 3758 # Type of FU issued -system.cpu.iq.rate 0.151410 # Inst issue rate +system.cpu.iq.rate 0.149805 # Inst issue rate system.cpu.iq.fu_busy_cnt 61 # FU busy when requested system.cpu.iq.fu_busy_rate 0.016232 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 14547 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 14562 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 6395 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 3419 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads @@ -480,7 +480,7 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 0 # system.cpu.iew.lsq.thread0.cacheBlocked 56 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 163 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 297 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 299 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 3 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 4700 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 46 # Number of squashed instructions skipped by dispatch @@ -501,33 +501,33 @@ system.cpu.iew.exec_nop 307 # nu system.cpu.iew.exec_refs 1093 # number of memory reference insts executed system.cpu.iew.exec_branches 599 # Number of branches executed system.cpu.iew.exec_stores 366 # Number of stores executed -system.cpu.iew.exec_rate 0.146414 # Inst execution rate +system.cpu.iew.exec_rate 0.144862 # Inst execution rate system.cpu.iew.wb_sent 3483 # cumulative count of insts sent to commit system.cpu.iew.wb_count 3425 # cumulative count of insts written-back system.cpu.iew.wb_producers 1633 # num instructions producing a value system.cpu.iew.wb_consumers 2097 # num instructions consuming a value -system.cpu.iew.wb_rate 0.137994 # insts written-back per cycle +system.cpu.iew.wb_rate 0.136530 # insts written-back per cycle system.cpu.iew.wb_fanout 0.778732 # average fanout of values written-back system.cpu.commit.commitSquashedInsts 2122 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 140 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6540 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.393884 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.249766 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 6555 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.392982 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.248476 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5669 86.68% 86.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 198 3.03% 89.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 318 4.86% 94.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5684 86.71% 86.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 198 3.02% 89.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 318 4.85% 94.58% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 118 1.80% 96.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 63 0.96% 97.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 63 0.96% 97.35% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 53 0.81% 98.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 37 0.57% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 37 0.56% 98.72% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 23 0.35% 99.07% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 61 0.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6540 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6555 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -574,38 +574,38 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 2576 # Class of committed instruction system.cpu.commit.bw_lim_events 61 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 10930 # The number of ROB reads +system.cpu.rob.rob_reads 10945 # The number of ROB reads system.cpu.rob.rob_writes 9815 # The number of ROB writes system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17865 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 18116 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 10.397989 # CPI: Cycles Per Instruction -system.cpu.cpi_total 10.397989 # CPI: Total CPI of All Threads -system.cpu.ipc 0.096172 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.096172 # IPC: Total IPC of All Threads +system.cpu.cpi 10.509426 # CPI: Cycles Per Instruction +system.cpu.cpi_total 10.509426 # CPI: Total CPI of All Threads +system.cpu.ipc 0.095153 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.095153 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 4383 # number of integer regfile reads system.cpu.int_regfile_writes 2640 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 45.439304 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 45.419736 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 735 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.647059 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 45.439304 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011094 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011094 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 45.419736 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011089 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011089 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1919 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1919 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 522 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 522 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits @@ -622,14 +622,14 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6673500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6673500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5672000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5672000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12345500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12345500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12345500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12345500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6754500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6754500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5744000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5744000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12498500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12498500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12498500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12498500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 623 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 623 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -646,19 +646,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.198473 system.cpu.dcache.demand_miss_rate::total 0.198473 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.198473 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.198473 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66074.257426 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66074.257426 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70024.691358 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70024.691358 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67832.417582 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67832.417582 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67832.417582 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67832.417582 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 256 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66876.237624 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66876.237624 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70913.580247 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70913.580247 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 68673.076923 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 68673.076923 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 68673.076923 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 68673.076923 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 260 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 42.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.333333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits @@ -676,14 +676,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4797000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4797000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1851000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1851000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6648000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6648000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6648000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6648000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4858000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4858000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1875000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1875000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6733000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6733000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6733000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6733000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.097913 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.097913 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses @@ -692,72 +692,72 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.092694 system.cpu.dcache.demand_mshr_miss_rate::total 0.092694 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.092694 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.092694 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78639.344262 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78639.344262 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77125 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77125 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78211.764706 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78211.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78211.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78211.764706 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79639.344262 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79639.344262 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78125 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78125 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79211.764706 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 79211.764706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79211.764706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 79211.764706 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 90.399218 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 625 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 90.302659 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 624 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.342246 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.336898 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 90.399218 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.044140 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.044140 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 90.302659 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.044093 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.044093 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 187 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.091309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1943 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1943 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 625 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 625 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 625 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 625 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 625 # number of overall hits -system.cpu.icache.overall_hits::total 625 # number of overall hits +system.cpu.icache.tags.tag_accesses 1941 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1941 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 624 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 624 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 624 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 624 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 624 # number of overall hits +system.cpu.icache.overall_hits::total 624 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 253 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 253 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 253 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 253 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 253 # number of overall misses system.cpu.icache.overall_misses::total 253 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18863999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18863999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18863999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18863999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18863999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18863999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 878 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 878 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 878 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 878 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 878 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 878 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.288155 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.288155 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.288155 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.288155 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.288155 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.288155 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74561.260870 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74561.260870 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74561.260870 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74561.260870 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74561.260870 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74561.260870 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19081499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19081499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19081499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19081499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19081499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19081499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 877 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 877 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 877 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 877 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 877 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 877 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.288483 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.288483 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.288483 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.288483 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.288483 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.288483 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75420.944664 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75420.944664 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75420.944664 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75420.944664 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75420.944664 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75420.944664 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits @@ -771,43 +771,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187 system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14160499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14160499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14160499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14160499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14160499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14160499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.212984 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.212984 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.212984 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.212984 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.212984 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.212984 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75724.593583 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75724.593583 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75724.593583 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75724.593583 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75724.593583 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75724.593583 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14560999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14560999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14560999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14560999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14560999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14560999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.213227 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.213227 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.213227 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.213227 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.213227 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.213227 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77866.304813 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77866.304813 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77866.304813 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 77866.304813 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77866.304813 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 77866.304813 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 119.261302 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 135.950101 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 248 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 272 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.557444 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.703859 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002764 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000876 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003640 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 248 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 205 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007568 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.459206 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 45.490894 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002761 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001388 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004149 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 272 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008301 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2448 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2448 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 187 # number of ReadCleanReq misses @@ -820,18 +820,18 @@ system.cpu.l2cache.demand_misses::total 272 # nu system.cpu.l2cache.overall_misses::cpu.inst 187 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 272 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1813500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1813500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13879000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 13879000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4705500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4705500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13879000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6519000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20398000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13879000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6519000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20398000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1837500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1837500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14279500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 14279500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4766500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4766500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14279500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6604000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20883500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14279500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6604000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20883500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187 # number of ReadCleanReq accesses(hits+misses) @@ -856,18 +856,18 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75562.500000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75562.500000 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74219.251337 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74219.251337 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77139.344262 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77139.344262 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74219.251337 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76694.117647 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74992.647059 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74219.251337 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76694.117647 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74992.647059 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76562.500000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76562.500000 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76360.962567 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76360.962567 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78139.344262 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78139.344262 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76360.962567 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77694.117647 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76777.573529 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76360.962567 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77694.117647 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76777.573529 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -886,18 +886,18 @@ system.cpu.l2cache.demand_mshr_misses::total 272 system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1573500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1573500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12009000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12009000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4095500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4095500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12009000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5669000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17678000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12009000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5669000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17678000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1597500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1597500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12409500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12409500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4156500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4156500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12409500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5754000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18163500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12409500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5754000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18163500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses @@ -910,25 +910,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65562.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65562.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64219.251337 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64219.251337 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67139.344262 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67139.344262 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64219.251337 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66694.117647 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64992.647059 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64219.251337 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66694.117647 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64992.647059 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66562.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66562.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66360.962567 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66360.962567 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68139.344262 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68139.344262 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66360.962567 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67694.117647 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66777.573529 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66360.962567 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67694.117647 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66777.573529 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution @@ -956,10 +956,16 @@ system.cpu.toL2Bus.snoop_fanout::total 272 # Re system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 280500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 248 # Transaction distribution system.membus.trans_dist::ReadExReq 24 # Transaction distribution system.membus.trans_dist::ReadExResp 24 # Transaction distribution @@ -980,9 +986,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 272 # Request fanout histogram -system.membus.reqLayer0.occupancy 337000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 337500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) system.membus.respLayer1.occupancy 1440000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.6 # Layer utilization (%) +system.membus.respLayer1.utilization 11.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index a36aefa9a..74510a8b2 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000001 # Nu sim_ticks 1297500 # Number of ticks simulated final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 290379 # Simulator instruction rate (inst/s) -host_op_rate 289620 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 145475657 # Simulator tick rate (ticks/s) -host_mem_usage 238224 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 120967 # Simulator instruction rate (inst/s) +host_op_rate 120887 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60829891 # Simulator tick rate (ticks/s) +host_mem_usage 241828 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -130,6 +130,12 @@ system.cpu.op_class::MemWrite 298 11.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 1297500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 3000 # Transaction distribution system.membus.trans_dist::ReadResp 3000 # Transaction distribution @@ -144,14 +150,14 @@ system.membus.pkt_size::total 15414 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 3294 # Request fanout histogram -system.membus.snoop_fanout::mean 0.784760 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.411051 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 709 21.52% 21.52% # Request fanout histogram -system.membus.snoop_fanout::1 2585 78.48% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3294 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3294 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index c5f7031d7..f7ca8186a 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 18239500 # Number of ticks simulated -final_tick 18239500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 18484500 # Number of ticks simulated +final_tick 18484500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 190443 # Simulator instruction rate (inst/s) -host_op_rate 190287 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1345802218 # Simulator tick rate (ticks/s) -host_mem_usage 247188 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 121029 # Simulator instruction rate (inst/s) +host_op_rate 120936 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 866943608 # Simulator tick rate (ticks/s) +host_mem_usage 250796 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5248 # Number of bytes read from this memory system.physmem.bytes_read::total 15680 # Number of bytes read from this memory @@ -22,15 +22,15 @@ system.physmem.bytes_inst_read::total 10432 # Nu system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory system.physmem.num_reads::total 245 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 571945503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 287727186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 859672688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 571945503 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 571945503 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 571945503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 287727186 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 859672688 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 564364738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 283913549 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 848278287 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 564364738 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 564364738 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 564364738 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 283913549 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 848278287 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -65,8 +65,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 18239500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 36479 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 18484500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 36969 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -85,7 +85,7 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 36479 # Number of busy cycles +system.cpu.num_busy_cycles 36969 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched @@ -124,23 +124,23 @@ system.cpu.op_class::MemWrite 298 11.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 47.277997 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 47.258408 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 47.277997 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011542 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011542 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 47.258408 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011538 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011538 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 82 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 49 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020020 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1500 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1500 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits @@ -157,14 +157,14 @@ system.cpu.dcache.demand_misses::cpu.data 82 # n system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses system.cpu.dcache.overall_misses::total 82 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3410000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3410000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1674000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1674000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 5084000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 5084000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 5084000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 5084000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3465000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3465000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1701000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1701000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 5166000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 5166000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 5166000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 5166000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -181,14 +181,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -203,14 +203,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 82 system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3355000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3355000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1647000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1647000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5002000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5002000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5002000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5002000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3410000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3410000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1674000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1674000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5084000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5084000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5084000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5084000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses @@ -219,31 +219,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 79.677134 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 79.631047 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 79.677134 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.038905 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.038905 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 79.631047 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.038882 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.038882 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 163 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.079590 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 5335 # Number of tag accesses system.cpu.icache.tags.data_accesses 5335 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits @@ -256,12 +256,12 @@ system.cpu.icache.demand_misses::cpu.inst 163 # n system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses system.cpu.icache.overall_misses::total 163 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 10106500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 10106500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 10106500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 10106500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 10106500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 10106500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 10269500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 10269500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 10269500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 10269500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 10269500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 10269500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses @@ -274,12 +274,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.063032 system.cpu.icache.demand_miss_rate::total 0.063032 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.063032 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62003.067485 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62003.067485 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62003.067485 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62003.067485 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62003.067485 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62003.067485 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63003.067485 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 63003.067485 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 63003.067485 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 63003.067485 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63003.067485 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63003.067485 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -292,43 +292,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 163 system.cpu.icache.demand_mshr_misses::total 163 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 163 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9943500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9943500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9943500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9943500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9943500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9943500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10106500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10106500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10106500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10106500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10106500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10106500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61003.067485 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61003.067485 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61003.067485 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61003.067485 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61003.067485 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61003.067485 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62003.067485 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62003.067485 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62003.067485 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 62003.067485 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62003.067485 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 62003.067485 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 106.649585 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 127.028625 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 218 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 245 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.770969 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 26.878617 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002434 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000820 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003255 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 218 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.006653 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.723638 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 47.304987 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002433 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001444 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003877 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 245 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007477 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2205 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2205 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 163 # number of ReadCleanReq misses @@ -341,18 +341,18 @@ system.cpu.l2cache.demand_misses::total 245 # nu system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 82 # number of overall misses system.cpu.l2cache.overall_misses::total 245 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1606500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1606500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9699000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 9699000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3272500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3272500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 9699000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4879000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 14578000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 9699000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4879000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 14578000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1633500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1633500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9862000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 9862000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3327500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3327500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9862000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4961000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14823000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9862000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4961000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14823000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 163 # number of ReadCleanReq accesses(hits+misses) @@ -377,18 +377,18 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.067485 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.067485 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.067485 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59502.040816 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.067485 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59502.040816 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.067485 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.067485 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.067485 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60502.040816 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.067485 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60502.040816 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -407,18 +407,18 @@ system.cpu.l2cache.demand_mshr_misses::total 245 system.cpu.l2cache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 245 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1336500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1336500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8069000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8069000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2722500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2722500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8069000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4059000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12128000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8069000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4059000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12128000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1363500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1363500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8232000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8232000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2777500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2777500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8232000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4141000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12373000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8232000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4141000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12373000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses @@ -431,25 +431,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.067485 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.067485 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.067485 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49502.040816 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.067485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49502.040816 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.067485 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.067485 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.067485 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50502.040816 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.067485 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50502.040816 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 245 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution @@ -480,7 +480,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 244500 # La system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 123000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 245 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 218 # Transaction distribution system.membus.trans_dist::ReadExReq 27 # Transaction distribution system.membus.trans_dist::ReadExResp 27 # Transaction distribution @@ -504,6 +510,6 @@ system.membus.snoop_fanout::total 245 # Re system.membus.reqLayer0.occupancy 245500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) system.membus.respLayer1.occupancy 1225000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.7 # Layer utilization (%) +system.membus.respLayer1.utilization 6.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index ebafeb85e..9ca1ab172 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 30083500 # Number of ticks simulated -final_tick 30083500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 30404500 # Number of ticks simulated +final_tick 30404500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 80042 # Simulator instruction rate (inst/s) -host_op_rate 93682 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 522670316 # Simulator tick rate (ticks/s) -host_mem_usage 264608 # Number of bytes of host memory used +host_inst_rate 82707 # Simulator instruction rate (inst/s) +host_op_rate 96800 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 545818868 # Simulator tick rate (ticks/s) +host_mem_usage 269760 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 4605 # Number of instructions simulated sim_ops 5391 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory system.physmem.bytes_read::total 26944 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory system.physmem.num_reads::total 421 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 648860671 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 246779796 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 895640467 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 648860671 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 648860671 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 648860671 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 246779796 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 895640467 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 642010229 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 244174382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 886184611 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 642010229 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 642010229 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 642010229 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 244174382 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 886184611 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 421 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 29992500 # Total gap between requests +system.physmem.totGap 30312500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -187,71 +187,71 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 408.774194 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 287.809352 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 328.256468 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 27.42% 40.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 12 19.35% 59.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6 9.68% 69.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.84% 74.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 4.84% 79.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 4.84% 83.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.61% 85.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation -system.physmem.totQLat 2221000 # Total ticks spent queuing -system.physmem.totMemAccLat 10114750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 402.285714 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 286.546821 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.800854 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 30.16% 41.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13 20.63% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6 9.52% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 3.17% 74.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 4.76% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.59% 85.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation +system.physmem.totQLat 2201250 # Total ticks spent queuing +system.physmem.totMemAccLat 10095000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5275.53 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5228.62 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24025.53 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 895.64 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23978.62 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 886.18 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 895.64 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 886.18 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.00 # Data bus utilization in percentage -system.physmem.busUtilRead 7.00 # Data bus utilization in percentage for reads +system.physmem.busUtil 6.92 # Data bus utilization in percentage +system.physmem.busUtilRead 6.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 350 # Number of row buffer hits during reads +system.physmem.readRowHits 349 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.90 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 71241.09 # Average gap between requests -system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined +system.physmem.avgGap 72001.19 # Average gap between requests +system.physmem.pageHitRate 82.90 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1965600 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 1942200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16103925 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 20064615 # Total energy per rank (pJ) -system.physmem_0.averagePower 849.295873 # Core power per rank (mW) +system.physmem_0.totalEnergy 20036940 # Total energy per rank (pJ) +system.physmem_0.averagePower 848.348875 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 12000 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22845750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22840500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 694200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15554160 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 527250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 18499935 # Total energy per rank (pJ) -system.physmem_1.averagePower 783.273247 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2015750 # Time in different power states +system.physmem_1.actBackEnergy 15442155 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 625500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 18486180 # Total energy per rank (pJ) +system.physmem_1.averagePower 782.690871 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2431750 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 22043250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 21880250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 1968 # Number of BP lookups system.cpu.branchPred.condPredicted 1178 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 351 # Number of conditional branches incorrect @@ -266,7 +266,7 @@ system.cpu.branchPred.indirectHits 8 # Nu system.cpu.branchPred.indirectMisses 127 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 62 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,16 +387,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 30083500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 60167 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 30404500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 60809 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4605 # Number of instructions committed system.cpu.committedOps 5391 # Number of ops (including micro ops) committed system.cpu.discardedOps 1193 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 13.065581 # CPI: cycles per instruction -system.cpu.ipc 0.076537 # IPC: instructions per cycle +system.cpu.cpi 13.204995 # CPI: cycles per instruction +system.cpu.ipc 0.075729 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 3419 63.42% 63.42% # Class of committed instruction system.cpu.op_class_0::IntMult 4 0.07% 63.49% # Class of committed instruction @@ -432,25 +432,25 @@ system.cpu.op_class_0::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 5391 # Class of committed instruction -system.cpu.tickCycles 10719 # Number of cycles that the object actually ticked -system.cpu.idleCycles 49448 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 10721 # Number of cycles that the object actually ticked +system.cpu.idleCycles 50088 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.478936 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 86.589882 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.478936 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021113 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021113 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.589882 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021140 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021140 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4334 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4334 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1050 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1050 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits @@ -471,14 +471,14 @@ system.cpu.dcache.demand_misses::cpu.data 176 # n system.cpu.dcache.demand_misses::total 176 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 176 # number of overall misses system.cpu.dcache.overall_misses::total 176 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6690500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6690500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5002500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5002500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 11693000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 11693000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 11693000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 11693000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6774500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6774500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5069500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5069500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 11844000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 11844000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 11844000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 11844000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1159 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1159 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -499,14 +499,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.084942 system.cpu.dcache.demand_miss_rate::total 0.084942 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.084942 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.084942 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61380.733945 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61380.733945 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74664.179104 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74664.179104 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66437.500000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66437.500000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66437.500000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66437.500000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62151.376147 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62151.376147 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75664.179104 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75664.179104 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67295.454545 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67295.454545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67295.454545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67295.454545 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -529,14 +529,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6338000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6338000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3188000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3188000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9526000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9526000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9526000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9526000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6419000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6419000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3231000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3231000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9650000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9650000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9650000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9650000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088870 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088870 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses @@ -545,31 +545,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070463 system.cpu.dcache.demand_mshr_miss_rate::total 0.070463 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070463 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.070463 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61533.980583 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61533.980583 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74139.534884 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74139.534884 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65246.575342 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65246.575342 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65246.575342 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65246.575342 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62320.388350 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62320.388350 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75139.534884 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75139.534884 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66095.890411 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66095.890411 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66095.890411 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66095.890411 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 161.834516 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 162.072741 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1963 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 6.096273 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 161.834516 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.079021 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.079021 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 162.072741 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.079137 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.079137 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4892 # Number of tag accesses system.cpu.icache.tags.data_accesses 4892 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1963 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1963 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1963 # number of demand (read+write) hits @@ -582,12 +582,12 @@ system.cpu.icache.demand_misses::cpu.inst 322 # n system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses system.cpu.icache.overall_misses::total 322 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23678000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23678000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23678000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23678000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23678000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23678000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23964000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23964000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23964000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23964000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23964000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23964000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2285 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2285 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2285 # number of demand (read+write) accesses @@ -600,12 +600,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.140919 system.cpu.icache.demand_miss_rate::total 0.140919 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.140919 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.140919 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73534.161491 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 73534.161491 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 73534.161491 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 73534.161491 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 73534.161491 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73534.161491 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74422.360248 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74422.360248 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74422.360248 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74422.360248 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74422.360248 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74422.360248 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -620,43 +620,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 322 system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23356000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23356000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23356000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23356000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23356000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23356000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23642000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23642000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23642000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23642000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23642000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23642000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.140919 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.140919 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.140919 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.140919 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.140919 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.140919 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72534.161491 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72534.161491 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72534.161491 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72534.161491 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72534.161491 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72534.161491 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73422.360248 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73422.360248 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73422.360248 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73422.360248 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73422.360248 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73422.360248 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 195.879475 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 223.657376 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.111111 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 421 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.099762 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.746810 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 41.132665 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004722 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005978 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.975765 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 68.681611 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004729 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002096 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006825 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012848 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4189 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4189 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits @@ -681,18 +681,18 @@ system.cpu.l2cache.demand_misses::total 429 # nu system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses system.cpu.l2cache.overall_misses::total 429 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3123500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3123500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22677500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 22677500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5924000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 5924000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22677500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9047500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31725000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22677500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9047500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31725000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3166500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3166500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22963500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 22963500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6005000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6005000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22963500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9171500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32135000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22963500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9171500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32135000 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) @@ -719,18 +719,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.916667 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72639.534884 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72639.534884 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74352.459016 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74352.459016 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73135.802469 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73135.802469 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74352.459016 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72963.709677 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73951.048951 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74352.459016 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72963.709677 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73951.048951 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73639.534884 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73639.534884 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75290.163934 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75290.163934 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 74135.802469 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 74135.802469 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75290.163934 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73963.709677 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74906.759907 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75290.163934 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73963.709677 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74906.759907 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -755,18 +755,18 @@ system.cpu.l2cache.demand_mshr_misses::total 421 system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2693500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2693500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19627500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19627500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4648000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4648000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19627500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7341500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26969000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19627500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7341500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26969000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2736500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2736500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19913500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19913500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4721000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4721000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19913500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7457500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27371000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19913500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7457500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27371000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses @@ -779,25 +779,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62639.534884 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62639.534884 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64352.459016 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64352.459016 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63671.232877 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63671.232877 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64352.459016 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63288.793103 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64059.382423 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64352.459016 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63288.793103 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64059.382423 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63639.534884 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63639.534884 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65290.163934 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65290.163934 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64671.232877 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64671.232877 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65290.163934 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64288.793103 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65014.251781 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65290.163934 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64288.793103 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65014.251781 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 472 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 50 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -829,7 +829,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 483000 # La system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 421 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 378 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution @@ -852,7 +858,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 421 # Request fanout histogram system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2237750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2238500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 7.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 117199ea9..012901358 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17232500 # Number of ticks simulated -final_tick 17232500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 17458500 # Number of ticks simulated +final_tick 17458500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74373 # Simulator instruction rate (inst/s) -host_op_rate 87086 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 279001739 # Simulator tick rate (ticks/s) -host_mem_usage 265896 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 52261 # Simulator instruction rate (inst/s) +host_op_rate 61197 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 198636102 # Simulator tick rate (ticks/s) +host_mem_usage 269760 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory system.physmem.bytes_read::total 25408 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 17664 # Nu system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory system.physmem.num_reads::total 397 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1025039896 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 449383432 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1474423328 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1025039896 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1025039896 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1025039896 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 449383432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1474423328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1011770771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 443566171 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1455336942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1011770771 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1011770771 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1011770771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 443566171 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1455336942 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 397 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 17147000 # Total gap between requests +system.physmem.totGap 17373000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,10 +91,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -187,78 +187,78 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 391.111111 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 256.618090 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 341.397843 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13 20.63% 20.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18 28.57% 49.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7 11.11% 60.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6 9.52% 69.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 6.35% 76.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 3.17% 85.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 3287250 # Total ticks spent queuing -system.physmem.totMemAccLat 10731000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 61 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 398.688525 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 264.215339 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 341.944807 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12 19.67% 19.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15 24.59% 44.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 14.75% 59.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7 11.48% 70.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.92% 75.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 3.28% 78.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 3.28% 81.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 3.28% 85.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 14.75% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61 # Bytes accessed per row activation +system.physmem.totQLat 3455750 # Total ticks spent queuing +system.physmem.totMemAccLat 10899500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8280.23 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8704.66 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27030.23 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1474.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27454.66 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1455.34 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1474.42 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1455.34 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.52 # Data bus utilization in percentage -system.physmem.busUtilRead 11.52 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.37 # Data bus utilization in percentage +system.physmem.busUtilRead 11.37 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.88 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 331 # Number of row buffer hits during reads +system.physmem.readRowHits 330 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43191.44 # Average gap between requests -system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 43760.71 # Average gap between requests +system.physmem.pageHitRate 83.12 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2051400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14411520 # Total energy per rank (pJ) -system.physmem_0.averagePower 910.249171 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 69250 # Time in different power states +system.physmem_0.totalEnergy 14349150 # Total energy per rank (pJ) +system.physmem_0.averagePower 906.309806 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16107250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 764400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 143640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 78375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 748800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10407915 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 369750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12792885 # Total energy per rank (pJ) -system.physmem_1.averagePower 808.014211 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 741250 # Time in different power states +system.physmem_1.actBackEnergy 10299330 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 466500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12753765 # Total energy per rank (pJ) +system.physmem_1.averagePower 805.416167 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 734500 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14752750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14593500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2837 # Number of BP lookups +system.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 2836 # Number of BP lookups system.cpu.branchPred.condPredicted 1744 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2401 # Number of BTB lookups -system.cpu.branchPred.BTBHits 865 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2400 # Number of BTB lookups +system.cpu.branchPred.BTBHits 864 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 36.026656 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 36.000000 # BTB Hit Percentage system.cpu.branchPred.usedRAS 314 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 265 # Number of indirect predictor lookups. @@ -266,7 +266,7 @@ system.cpu.branchPred.indirectHits 14 # Nu system.cpu.branchPred.indirectMisses 251 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +296,7 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +326,7 @@ system.cpu.checker.dtb.inst_accesses 0 # IT system.cpu.checker.dtb.hits 0 # DTB hits system.cpu.checker.dtb.misses 0 # DTB misses system.cpu.checker.dtb.accesses 0 # DTB accesses -system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +356,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.checker.itb.walker.walks 0 # Table walker walks requested system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,11 +387,11 @@ system.cpu.checker.itb.hits 0 # DT system.cpu.checker.itb.misses 0 # DTB misses system.cpu.checker.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.checker.pwrStateResidencyTicks::ON 17232500 # Cumulative time (in ticks) in various power states +system.cpu.checker.pwrStateResidencyTicks::ON 17458500 # Cumulative time (in ticks) in various power states system.cpu.checker.numCycles 5391 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -421,7 +421,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -451,7 +451,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -481,7 +481,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -511,66 +511,66 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.pwrStateResidencyTicks::ON 17232500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 34466 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 17458500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 34918 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7588 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12295 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2837 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1193 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4873 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 7601 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12293 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2836 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1192 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4902 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 977 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 246 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 248 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1961 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13213 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.120412 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.482171 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1960 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13257 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.116542 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.478893 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10520 79.62% 79.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 264 2.00% 81.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 185 1.40% 83.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 203 1.54% 84.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 282 2.13% 86.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 396 3.00% 89.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 139 1.05% 90.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 173 1.31% 92.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1051 7.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10565 79.69% 79.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 264 1.99% 81.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 184 1.39% 83.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 203 1.53% 84.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 282 2.13% 86.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 396 2.99% 89.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 139 1.05% 90.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 173 1.30% 92.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1051 7.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13213 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.082313 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.356728 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6291 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4311 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2142 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 13257 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.081219 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.352053 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6292 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4354 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2143 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 134 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 334 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 431 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12135 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12137 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 334 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6519 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 770 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2303 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2037 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1250 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11429 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 6521 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 773 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2325 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2036 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1268 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11426 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 166 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 130 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1074 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 11638 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 52321 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12347 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 168 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 132 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1090 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 11634 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 52309 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12345 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 199 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6144 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6140 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 40 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 441 # count of insts added to the skid buffer @@ -578,109 +578,109 @@ system.cpu.memDep0.insertedLoads 2200 # Nu system.cpu.memDep0.insertedStores 1540 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10167 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 10163 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8103 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4832 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12329 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8100 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 40 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4828 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 12342 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13213 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.613260 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.341984 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13257 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.610998 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.340069 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9987 75.58% 75.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1172 8.87% 84.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 771 5.84% 90.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 475 3.59% 93.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 345 2.61% 96.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 273 2.07% 98.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 121 0.92% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10033 75.68% 75.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1170 8.83% 84.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 770 5.81% 90.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 479 3.61% 93.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 341 2.57% 96.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 274 2.07% 98.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 121 0.91% 99.48% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 59 0.45% 99.92% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 10 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13213 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13257 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 6.21% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 65 44.83% 51.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 71 48.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 6.16% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 65 44.52% 50.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 72 49.32% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5027 62.04% 62.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.09% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.16% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1882 23.23% 85.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1184 14.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5026 62.05% 62.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.09% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.17% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1881 23.22% 85.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1183 14.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8103 # Type of FU issued -system.cpu.iq.rate 0.235101 # Inst issue rate -system.cpu.iq.fu_busy_cnt 145 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.017895 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29511 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14929 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7407 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8100 # Type of FU issued +system.cpu.iq.rate 0.231972 # Inst issue rate +system.cpu.iq.fu_busy_cnt 146 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018025 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29552 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14921 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7399 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 91 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8205 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8203 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -694,10 +694,10 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 31 # system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 334 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 683 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 684 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10219 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispatchedInsts 10215 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 130 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2200 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1540 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions @@ -707,41 +707,41 @@ system.cpu.iew.memOrderViolationEvents 19 # Nu system.cpu.iew.predictedTakenIncorrect 94 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 357 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7814 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1772 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 289 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7807 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1773 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 293 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 9 # number of nop insts executed -system.cpu.iew.exec_refs 2923 # number of memory reference insts executed +system.cpu.iew.exec_refs 2920 # number of memory reference insts executed system.cpu.iew.exec_branches 1492 # Number of branches executed -system.cpu.iew.exec_stores 1151 # Number of stores executed -system.cpu.iew.exec_rate 0.226716 # Inst execution rate -system.cpu.iew.wb_sent 7536 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7439 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3504 # num instructions producing a value -system.cpu.iew.wb_consumers 6831 # num instructions consuming a value -system.cpu.iew.wb_rate 0.215836 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.512956 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4840 # The number of squashed insts skipped by commit +system.cpu.iew.exec_stores 1147 # Number of stores executed +system.cpu.iew.exec_rate 0.223581 # Inst execution rate +system.cpu.iew.wb_sent 7528 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7431 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3502 # num instructions producing a value +system.cpu.iew.wb_consumers 6830 # num instructions consuming a value +system.cpu.iew.wb_rate 0.212813 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.512738 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 4836 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 310 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12359 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.435148 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.280013 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12404 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.433570 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.278209 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10307 83.40% 83.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 885 7.16% 90.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 420 3.40% 93.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 217 1.76% 95.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 108 0.87% 96.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 219 1.77% 98.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 55 0.45% 98.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.32% 99.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10353 83.47% 83.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 884 7.13% 90.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 420 3.39% 93.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 217 1.75% 95.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 107 0.86% 96.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 220 1.77% 98.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 55 0.44% 98.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.31% 99.12% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 109 0.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12359 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12404 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -788,52 +788,52 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22311 # The number of ROB reads -system.cpu.rob.rob_writes 21303 # The number of ROB writes +system.cpu.rob.rob_reads 22352 # The number of ROB reads +system.cpu.rob.rob_writes 21294 # The number of ROB writes system.cpu.timesIdled 191 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21253 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 21661 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.505662 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.505662 # CPI: Total CPI of All Threads -system.cpu.ipc 0.133233 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.133233 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7659 # number of integer regfile reads -system.cpu.int_regfile_writes 4270 # number of integer regfile writes +system.cpu.cpi 7.604094 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.604094 # CPI: Total CPI of All Threads +system.cpu.ipc 0.131508 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.131508 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 7649 # number of integer regfile reads +system.cpu.int_regfile_writes 4266 # number of integer regfile writes system.cpu.fp_regfile_reads 32 # number of floating regfile reads -system.cpu.cc_regfile_reads 27801 # number of cc regfile reads -system.cpu.cc_regfile_writes 3276 # number of cc regfile writes -system.cpu.misc_regfile_reads 2980 # number of misc regfile reads +system.cpu.cc_regfile_reads 27780 # number of cc regfile reads +system.cpu.cc_regfile_writes 3273 # number of cc regfile writes +system.cpu.misc_regfile_reads 2976 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 88.359063 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2095 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 88.222961 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2096 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.251701 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.258503 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 88.359063 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021572 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021572 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 88.222961 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021539 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021539 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5339 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5339 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5341 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5341 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 1478 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1478 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2074 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2074 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2074 # number of overall hits -system.cpu.dcache.overall_hits::total 2074 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2075 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2075 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2075 # number of overall hits +system.cpu.dcache.overall_hits::total 2075 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 183 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 183 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses @@ -844,53 +844,53 @@ system.cpu.dcache.demand_misses::cpu.data 499 # n system.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses system.cpu.dcache.overall_misses::total 499 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10736000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10736000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22555500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22555500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 142000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33291500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33291500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33291500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33291500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1660 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1660 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10847000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10847000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22859500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22859500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 144000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 144000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33706500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33706500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33706500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33706500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1661 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1661 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2573 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2573 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2573 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2573 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.110241 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.110241 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2574 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2574 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2574 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2574 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.110175 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.110175 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.193937 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.193937 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.193937 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.193937 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58666.666667 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58666.666667 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71378.164557 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 71378.164557 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66716.432866 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66716.432866 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66716.432866 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66716.432866 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.193862 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.193862 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.193862 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.193862 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59273.224044 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59273.224044 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72340.189873 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72340.189873 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67548.096192 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67548.096192 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67548.096192 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67548.096192 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 147 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 49 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits @@ -910,88 +910,88 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7020000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7020000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3398000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3398000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10418000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10418000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10418000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10418000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.063253 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.063253 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7089000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7089000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3440000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3440000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10529000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10529000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10529000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10529000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.063215 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.063215 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057132 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057132 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057132 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.057132 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66857.142857 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66857.142857 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80904.761905 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80904.761905 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057110 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057110 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057110 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.057110 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67514.285714 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67514.285714 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81904.761905 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81904.761905 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71625.850340 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71625.850340 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71625.850340 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71625.850340 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 150.405898 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 149.958367 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1576 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.363946 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.360544 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 150.405898 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073440 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073440 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 149.958367 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073222 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073222 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4216 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4216 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits -system.cpu.icache.overall_hits::total 1577 # number of overall hits +system.cpu.icache.tags.tag_accesses 4214 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4214 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1576 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1576 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1576 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1576 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1576 # number of overall hits +system.cpu.icache.overall_hits::total 1576 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 384 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 384 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 384 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 384 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 384 # number of overall misses system.cpu.icache.overall_misses::total 384 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26669500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26669500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26669500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26669500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26669500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26669500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1961 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1961 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1961 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1961 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1961 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1961 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195818 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.195818 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.195818 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.195818 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.195818 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.195818 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69451.822917 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69451.822917 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69451.822917 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69451.822917 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69451.822917 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69451.822917 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 423 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 27225000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 27225000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 27225000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 27225000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 27225000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 27225000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1960 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1960 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1960 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1960 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1960 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1960 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195918 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.195918 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.195918 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.195918 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.195918 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.195918 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70898.437500 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70898.437500 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70898.437500 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70898.437500 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70898.437500 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70898.437500 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 84.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 86.600000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 2 # number of writebacks system.cpu.icache.writebacks::total 2 # number of writebacks @@ -1007,43 +1007,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 294 system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21733500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21733500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21733500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21733500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21733500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21733500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149924 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.149924 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.149924 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73923.469388 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73923.469388 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22193500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22193500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22193500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22193500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22193500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22193500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.150000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.150000 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.150000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.150000 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.150000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.150000 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75488.095238 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75488.095238 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75488.095238 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75488.095238 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75488.095238 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75488.095238 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 187.999052 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 215.001500 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.098237 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.158865 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.840188 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004308 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001429 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005737 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.723037 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 74.278463 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004295 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002267 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006561 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3933 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3933 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits @@ -1068,18 +1068,18 @@ system.cpu.l2cache.demand_misses::total 403 # nu system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses system.cpu.l2cache.overall_misses::total 403 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3333000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3333000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21084500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 21084500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6625500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6625500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21084500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9958500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31043000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21084500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9958500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31043000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3375000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3375000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21544500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 21544500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6694500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6694500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21544500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10069500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31614000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21544500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10069500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31614000 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) @@ -1106,18 +1106,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.913832 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938776 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.913832 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79357.142857 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79357.142857 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76393.115942 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76393.115942 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77947.058824 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77947.058824 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76393.115942 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78413.385827 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77029.776675 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76393.115942 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78413.385827 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77029.776675 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80357.142857 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80357.142857 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 78059.782609 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78059.782609 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78758.823529 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78758.823529 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78059.782609 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79287.401575 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78446.650124 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78059.782609 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79287.401575 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78446.650124 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1142,18 +1142,18 @@ system.cpu.l2cache.demand_mshr_misses::total 397 system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2913000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2913000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18324500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18324500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5436000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5436000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18324500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8349000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26673500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18324500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8349000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26673500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2955000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2955000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18784500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18784500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5499000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5499000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18784500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8454000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27238500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18784500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8454000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27238500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadCleanReq accesses @@ -1166,25 +1166,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69357.142857 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69357.142857 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66393.115942 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66393.115942 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68810.126582 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68810.126582 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66393.115942 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66393.115942 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70357.142857 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70357.142857 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68059.782609 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68059.782609 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69607.594937 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69607.594937 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68059.782609 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69867.768595 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68610.831234 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68059.782609 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69867.768595 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68610.831234 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 443 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution @@ -1213,10 +1213,16 @@ system.cpu.toL2Bus.snoop_fanout::total 441 # Re system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 441000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 397 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 355 # Transaction distribution system.membus.trans_dist::ReadExReq 42 # Transaction distribution system.membus.trans_dist::ReadExResp 42 # Transaction distribution @@ -1239,7 +1245,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 397 # Request fanout histogram system.membus.reqLayer0.occupancy 488000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 2101750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 2102000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 7324072b2..bfd96912f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18821000 # Number of ticks simulated -final_tick 18821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19046000 # Number of ticks simulated +final_tick 19046000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81076 # Simulator instruction rate (inst/s) -host_op_rate 94934 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 332169191 # Simulator tick rate (ticks/s) -host_mem_usage 262700 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 51970 # Simulator instruction rate (inst/s) +host_op_rate 60857 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 215490046 # Simulator tick rate (ticks/s) +host_mem_usage 266056 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 18560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8192 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory -system.physmem.bytes_read::total 28352 # Number of bytes read from this memory +system.physmem.bytes_read::total 28480 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 18560 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 18560 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 290 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 126 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 128 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 986132512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 428457574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 91812337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1506402423 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 986132512 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 986132512 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 986132512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 428457574 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 91812337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1506402423 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 443 # Number of read requests accepted +system.physmem.num_reads::total 445 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 974482831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 430116560 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 90727712 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1495327103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 974482831 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 974482831 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 974482831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 430116560 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 90727712 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1495327103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 443 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 445 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28352 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 28480 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28352 # Total read bytes from the system interface side +system.physmem.bytesReadSys 28480 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 101 # Per bank write bursts +system.physmem.perBankRdBursts::0 103 # Per bank write bursts system.physmem.perBankRdBursts::1 48 # Per bank write bursts system.physmem.perBankRdBursts::2 19 # Per bank write bursts system.physmem.perBankRdBursts::3 45 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 18779500 # Total gap between requests +system.physmem.totGap 19004500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 443 # Read request sizes (log2) +system.physmem.readPktSize::6 445 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -96,11 +96,11 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see @@ -192,77 +192,77 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 427.682540 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 292.140083 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 354.445538 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18 28.57% 39.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 429.714286 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 289.613657 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 357.341954 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8 12.70% 12.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17 26.98% 39.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 11 17.46% 57.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 11.11% 68.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1 1.59% 69.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4 6.35% 76.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 1.59% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6 9.52% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.76% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 3.17% 74.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 3.17% 77.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 2 3.17% 80.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 12 19.05% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 3401243 # Total ticks spent queuing -system.physmem.totMemAccLat 11707493 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2215000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7677.75 # Average queueing delay per DRAM burst +system.physmem.totQLat 4296708 # Total ticks spent queuing +system.physmem.totMemAccLat 12640458 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9655.52 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26427.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1506.40 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28405.52 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1495.33 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1506.40 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1495.33 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.77 # Data bus utilization in percentage -system.physmem.busUtilRead 11.77 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.68 # Data bus utilization in percentage +system.physmem.busUtilRead 11.68 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.86 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 371 # Number of row buffer hits during reads +system.physmem.readRowHits 373 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.75 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42391.65 # Average gap between requests -system.physmem.pageHitRate 83.75 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2160600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 42706.74 # Average gap between requests +system.physmem.pageHitRate 83.82 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 287280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 156750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2152800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10755900 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 64500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14453835 # Total energy per rank (pJ) -system.physmem_0.averagePower 912.921838 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 51750 # Time in different power states +system.physmem_0.actBackEnergy 10689210 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 123000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14426160 # Total energy per rank (pJ) +system.physmem_0.averagePower 911.173851 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 148750 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15274500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15177500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 811200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10734525 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 83250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12844740 # Total energy per rank (pJ) -system.physmem_1.averagePower 811.289436 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 945250 # Time in different power states +system.physmem_1.actBackEnergy 10733670 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 84000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12844635 # Total energy per rank (pJ) +system.physmem_1.averagePower 811.282804 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1145250 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15229250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15228250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2438 # Number of BP lookups -system.cpu.branchPred.condPredicted 1442 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 2439 # Number of BP lookups +system.cpu.branchPred.condPredicted 1443 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 524 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 915 # Number of BTB lookups -system.cpu.branchPred.BTBHits 449 # Number of BTB hits +system.cpu.branchPred.BTBHits 448 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 49.071038 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 48.961749 # BTB Hit Percentage system.cpu.branchPred.usedRAS 286 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 163 # Number of indirect predictor lookups. @@ -270,7 +270,7 @@ system.cpu.branchPred.indirectHits 13 # Nu system.cpu.branchPred.indirectMisses 150 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 60 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -300,7 +300,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +330,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +360,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -391,85 +391,85 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 18821000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 37643 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 19046000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 38093 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6083 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11454 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2438 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 748 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 8291 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 6117 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11468 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2439 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 747 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 8723 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1091 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 169 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 272 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3904 # Number of cache lines fetched +system.cpu.fetch.MiscStallCycles 171 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 274 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 416 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 3907 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 178 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15772 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.863365 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.208800 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 16246 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.839530 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.200509 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9389 59.53% 59.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2507 15.90% 75.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 518 3.28% 78.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3358 21.29% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9855 60.66% 60.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2507 15.43% 76.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 520 3.20% 79.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3364 20.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15772 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.064766 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.304280 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5832 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4243 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 16246 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.064028 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.301053 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5842 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4705 # Number of cycles decode is blocked system.cpu.decode.RunCycles 5178 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 133 # Number of cycles decode is unblocking +system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 386 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 373 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 161 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 10169 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1675 # Number of squashed instructions handled by decode +system.cpu.decode.BranchResolved 375 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 10177 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1679 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 386 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6945 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1086 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2318 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4187 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 850 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 9093 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 454 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full +system.cpu.rename.IdleCycles 6957 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1136 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2347 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4188 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1232 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 9097 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 461 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 24 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 744 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9450 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 41121 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9999 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 1125 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9457 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 41127 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9997 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3956 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3963 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 29 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 331 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1823 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1291 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 333 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1824 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1284 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 8515 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7234 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 175 # Number of squashed instructions issued +system.cpu.iq.iqInstsIssued 7229 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 177 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 3175 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8237 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 8254 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15772 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.458661 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.847067 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 16246 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.444971 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.838160 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11502 72.93% 72.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1999 12.67% 85.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1621 10.28% 95.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 607 3.85% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 43 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11980 73.74% 73.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1997 12.29% 86.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1618 9.96% 95.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 608 3.74% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 43 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -477,105 +477,105 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15772 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 16246 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 415 28.78% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 474 32.87% 61.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 553 38.35% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 416 28.89% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 475 32.99% 61.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 549 38.12% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4534 62.68% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1605 22.19% 84.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1087 15.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4534 62.72% 62.72% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1606 22.22% 85.05% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1081 14.95% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7234 # Type of FU issued -system.cpu.iq.rate 0.192174 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1442 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.199336 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31813 # Number of integer instruction queue reads +system.cpu.iq.FU_type_0::total 7229 # Type of FU issued +system.cpu.iq.rate 0.189772 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1440 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.199198 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 32277 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 11719 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6621 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 6614 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8648 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8641 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 12 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 796 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 797 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 353 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 346 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 386 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 336 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 339 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 8566 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1823 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1291 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 1824 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1284 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall @@ -583,41 +583,41 @@ system.cpu.iew.memOrderViolationEvents 7 # Nu system.cpu.iew.predictedTakenIncorrect 59 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6824 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1421 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 410 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 6820 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1423 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 409 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 13 # number of nop insts executed -system.cpu.iew.exec_refs 2451 # number of memory reference insts executed -system.cpu.iew.exec_branches 1299 # Number of branches executed -system.cpu.iew.exec_stores 1030 # Number of stores executed -system.cpu.iew.exec_rate 0.181282 # Inst execution rate -system.cpu.iew.wb_sent 6681 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6637 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2986 # num instructions producing a value -system.cpu.iew.wb_consumers 5424 # num instructions consuming a value -system.cpu.iew.wb_rate 0.176314 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.550516 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 2706 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 2448 # number of memory reference insts executed +system.cpu.iew.exec_branches 1296 # Number of branches executed +system.cpu.iew.exec_stores 1025 # Number of stores executed +system.cpu.iew.exec_rate 0.179036 # Inst execution rate +system.cpu.iew.wb_sent 6675 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6630 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2985 # num instructions producing a value +system.cpu.iew.wb_consumers 5422 # num instructions consuming a value +system.cpu.iew.wb_rate 0.174048 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.550535 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 2710 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 365 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 15204 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.353723 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 0.993092 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 15677 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.343050 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.979995 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 12538 82.47% 82.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1405 9.24% 91.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 597 3.93% 95.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 300 1.97% 97.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 170 1.12% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 79 0.52% 99.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 44 0.29% 99.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 28 0.18% 99.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 43 0.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 13011 82.99% 82.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1405 8.96% 91.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 598 3.81% 95.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 299 1.91% 97.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 169 1.08% 98.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 80 0.51% 99.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 44 0.28% 99.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 28 0.18% 99.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 43 0.27% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 15204 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 15677 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -664,40 +664,40 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 23088 # The number of ROB reads -system.cpu.rob.rob_writes 16743 # The number of ROB writes -system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21871 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23565 # The number of ROB reads +system.cpu.rob.rob_writes 16751 # The number of ROB writes +system.cpu.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 21847 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.197517 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.197517 # CPI: Total CPI of All Threads -system.cpu.ipc 0.121988 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.121988 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6777 # number of integer regfile reads -system.cpu.int_regfile_writes 3787 # number of integer regfile writes +system.cpu.cpi 8.295514 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.295514 # CPI: Total CPI of All Threads +system.cpu.ipc 0.120547 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.120547 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 6772 # number of integer regfile reads +system.cpu.int_regfile_writes 3788 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 24229 # number of cc regfile reads -system.cpu.cc_regfile_writes 2921 # number of cc regfile writes -system.cpu.misc_regfile_reads 2564 # number of misc regfile reads +system.cpu.cc_regfile_reads 24217 # number of cc regfile reads +system.cpu.cc_regfile_writes 2924 # number of cc regfile writes +system.cpu.misc_regfile_reads 2559 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.368926 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 84.349867 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1930 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.496503 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.368926 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.164783 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.164783 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.349867 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.164746 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.164746 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4723 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4723 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tag_accesses 4725 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4725 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1188 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1188 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits @@ -710,76 +710,76 @@ system.cpu.dcache.demand_hits::cpu.data 1910 # nu system.cpu.dcache.demand_hits::total 1910 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 1910 # number of overall hits system.cpu.dcache.overall_hits::total 1910 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 168 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 168 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses -system.cpu.dcache.overall_misses::total 358 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10679500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10679500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7608000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7608000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 125000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18287500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18287500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18287500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18287500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1355 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1355 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 359 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 359 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 359 # number of overall misses +system.cpu.dcache.overall_misses::total 359 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10937500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10937500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9601000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9601000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 127000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 127000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20538500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20538500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20538500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20538500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1356 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1356 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2268 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2268 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2268 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2268 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123247 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.123247 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2269 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2269 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2269 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2269 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123894 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.123894 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.157848 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.157848 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.157848 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.157848 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63949.101796 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63949.101796 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39832.460733 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39832.460733 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 51082.402235 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 51082.402235 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 51082.402235 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 51082.402235 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.158219 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.158219 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.158219 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.158219 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65104.166667 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 65104.166667 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 50267.015707 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 50267.015707 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 57210.306407 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 57210.306407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 57210.306407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 57210.306407 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 818 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1304 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 45.444444 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 72.444444 # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 1 # number of writebacks system.cpu.dcache.writebacks::total 1 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 214 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 214 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 214 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 214 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 215 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 215 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 215 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -788,189 +788,187 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 144 system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6934000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6934000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2433000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2433000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9367000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9367000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9367000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9367000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076015 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076015 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7149000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7149000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2700500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2700500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9849500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9849500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9849500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9849500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075959 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075959 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063492 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063492 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67320.388350 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67320.388350 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59341.463415 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59341.463415 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65048.611111 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65048.611111 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063464 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063464 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063464 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063464 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69407.766990 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69407.766990 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65865.853659 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65865.853659 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68399.305556 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68399.305556 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68399.305556 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68399.305556 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 44 # number of replacements -system.cpu.icache.tags.tagsinuse 137.890102 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3540 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 137.872552 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3542 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.839465 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.846154 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 137.890102 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.269317 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.269317 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 137.872552 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.269282 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.269282 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 255 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 8101 # Number of tag accesses -system.cpu.icache.tags.data_accesses 8101 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 3540 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3540 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3540 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3540 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3540 # number of overall hits -system.cpu.icache.overall_hits::total 3540 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 361 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 361 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 361 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 361 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 361 # number of overall misses -system.cpu.icache.overall_misses::total 361 # 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average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62331.469613 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62331.469613 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62331.469613 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62331.469613 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62331.469613 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8558 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 35 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 95 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 88.568421 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 90.084211 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 35 # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 44 # number of writebacks system.cpu.icache.writebacks::total 44 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 62 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 62 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 62 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 63 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19775992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19775992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19775992 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19775992 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076647 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.076647 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.076647 # 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average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66344.454849 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66344.454849 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66344.454849 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66344.454849 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66344.454849 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # 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Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 41 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.073171 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 10.572819 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.233490 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000645 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000564 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.001209 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 9.233331 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.162055 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000564 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000498 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.001062 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 13 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 # 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Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 10 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 10 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 8 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 8 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 13 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 21 # 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number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses +system.cpu.l2cache.overall_misses::total 425 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2572500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2572500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 19478500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 19478500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6989500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6989500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 19478500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9562000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 29040500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 19478500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9562000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 29040500 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) @@ -985,116 +983,117 @@ system.cpu.l2cache.demand_accesses::total 443 # n system.cpu.l2cache.overall_accesses::cpu.inst 299 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 144 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 443 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.731707 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.731707 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.756098 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.756098 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.973244 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.973244 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.980583 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.980583 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.973244 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.909722 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.952596 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.930556 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.959368 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.973244 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.909722 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.952596 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76633.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76633.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 66726.804124 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 66726.804124 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66935.643564 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66935.643564 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66726.804124 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69156.488550 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67481.042654 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66726.804124 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69156.488550 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67481.042654 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.930556 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.959368 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82983.870968 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82983.870968 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 66936.426117 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 66936.426117 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 67859.223301 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 67859.223301 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66936.426117 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71358.208955 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68330.588235 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66936.426117 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71358.208955 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68330.588235 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 53 # number of HardPFReq MSHR misses system.cpu.l2cache.HardPFReq_mshr_misses::total 53 # number of HardPFReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 30 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 30 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 290 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 290 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 98 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 98 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 126 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 128 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 418 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 128 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 53 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1908926 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1908926 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2119000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2119000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 17622000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 17622000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5892000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5892000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17622000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8011000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25633000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17622000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8011000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1908926 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27541926 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 471 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 3053926 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 3053926 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2154000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2154000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 17682000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 17682000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6104000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6104000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17682000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8258000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25940000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17682000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8258000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 3053926 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28993926 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.969900 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.932039 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.932039 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.951456 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.951456 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.875000 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.939052 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.888889 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.943567 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.875000 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.888889 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1.058691 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 36017.471698 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 36017.471698 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70633.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70633.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 60765.517241 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 60765.517241 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61375 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61375 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60765.517241 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63579.365079 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61617.788462 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60765.517241 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63579.365079 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 36017.471698 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58724.788913 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 1.063205 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 57621.245283 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 57621.245283 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71800 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71800 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 60972.413793 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 60972.413793 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62285.714286 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62285.714286 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60972.413793 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64515.625000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62057.416268 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60972.413793 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64515.625000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 57621.245283 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61558.229299 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 411 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 370 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 41 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.snoop_filter.tot_snoops 26 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 24 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 45 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 385 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution @@ -1106,49 +1105,55 @@ system.cpu.toL2Bus.pkt_count::total 930 # Pa system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21952 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 454 # Total snoops (count) +system.cpu.toL2Bus.snoops 69 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 897 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.549610 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.582523 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 512 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.134766 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.353072 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 445 49.61% 49.61% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 411 45.82% 95.43% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41 4.57% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 445 86.91% 86.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 65 12.70% 99.61% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 2 0.39% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 897 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 512 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 289000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 448999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 216995 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 412 # Transaction distribution +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 35 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 414 # Transaction distribution system.membus.trans_dist::ReadExReq 30 # Transaction distribution system.membus.trans_dist::ReadExResp 30 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 413 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 885 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 885 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28288 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 415 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 889 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 889 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 443 # Request fanout histogram +system.membus.snoop_fanout::samples 445 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 443 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 445 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 443 # Request fanout histogram -system.membus.reqLayer0.occupancy 561444 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 445 # Request fanout histogram +system.membus.reqLayer0.occupancy 562944 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2329257 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 2340257 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 55d542711..83c02dd61 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2695000 # Number of ticks simulated final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 427598 # Simulator instruction rate (inst/s) -host_op_rate 499586 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 249859240 # Simulator tick rate (ticks/s) -host_mem_usage 254616 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 207093 # Simulator instruction rate (inst/s) +host_op_rate 242387 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 121392563 # Simulator tick rate (ticks/s) +host_mem_usage 259512 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -344,6 +344,12 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5391 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 5597 # Transaction distribution system.membus.trans_dist::ReadResp 5608 # Transaction distribution @@ -361,14 +367,14 @@ system.membus.pkt_size::total 26559 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 6532 # Request fanout histogram -system.membus.snoop_fanout::mean 0.704991 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.456082 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1927 29.50% 29.50% # Request fanout histogram -system.membus.snoop_fanout::1 4605 70.50% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 6532 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 6532 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index 43260b12f..b8117da74 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2695000 # Number of ticks simulated final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 433184 # Simulator instruction rate (inst/s) -host_op_rate 506134 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 253162440 # Simulator tick rate (ticks/s) -host_mem_usage 254364 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 213878 # Simulator instruction rate (inst/s) +host_op_rate 250318 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 125362190 # Simulator tick rate (ticks/s) +host_mem_usage 258232 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -220,6 +220,12 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5391 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 5597 # Transaction distribution system.membus.trans_dist::ReadResp 5608 # Transaction distribution @@ -237,14 +243,14 @@ system.membus.pkt_size::total 26559 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 6532 # Request fanout histogram -system.membus.snoop_fanout::mean 0.704991 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.456082 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1927 29.50% 29.50% # Request fanout histogram -system.membus.snoop_fanout::1 4605 70.50% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 6532 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 6532 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 40170ff2c..6ed816eb8 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 28298500 # Number of ticks simulated -final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000029 # Number of seconds simulated +sim_ticks 28648500 # Number of ticks simulated +final_tick 28648500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 246555 # Simulator instruction rate (inst/s) -host_op_rate 287459 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1524533550 # Simulator tick rate (ticks/s) -host_mem_usage 264352 # Number of bytes of host memory used +host_inst_rate 192730 # Simulator instruction rate (inst/s) +host_op_rate 224907 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1208517164 # Simulator tick rate (ticks/s) +host_mem_usage 267456 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 4566 # Number of instructions simulated sim_ops 5330 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory system.physmem.bytes_read::total 22400 # Number of bytes read from this memory @@ -22,17 +22,17 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 508860894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 282700496 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 791561390 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 508860894 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 508860894 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 508860894 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 282700496 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 791561390 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 502644117 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 279246732 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 781890849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 502644117 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 502644117 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 502644117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 279246732 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 781890849 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -62,7 +62,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -92,7 +92,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -122,7 +122,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -153,8 +153,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 28298500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 56597 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 28648500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 57297 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4566 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 1965 # nu system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 56596.998000 # Number of busy cycles +system.cpu.num_busy_cycles 57296.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1008 # Number of branches fetched @@ -214,23 +214,23 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5391 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.647245 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 82.616265 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.647245 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020178 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020178 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 82.616265 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020170 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020170 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits @@ -251,14 +251,14 @@ system.cpu.dcache.demand_misses::cpu.data 141 # n system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses system.cpu.dcache.overall_misses::total 141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5308000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5308000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2666000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2666000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7974000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7974000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7974000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7974000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5390000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5390000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2709000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2709000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8099000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8099000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8099000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8099000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -279,14 +279,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54163.265306 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54163.265306 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56553.191489 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56553.191489 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 57439.716312 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 57439.716312 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 57439.716312 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 57439.716312 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -301,14 +301,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5210000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5210000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2623000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2623000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7833000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7833000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7833000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7833000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5292000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5292000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2666000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2666000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7958000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7958000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7958000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7958000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses @@ -317,31 +317,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53163.265306 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53163.265306 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56439.716312 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 56439.716312 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56439.716312 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 56439.716312 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 114.043293 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 113.995886 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 114.043293 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.055685 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.055685 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 113.995886 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.055662 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.055662 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses system.cpu.icache.tags.data_accesses 9453 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits @@ -354,12 +354,12 @@ system.cpu.icache.demand_misses::cpu.inst 241 # n system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses system.cpu.icache.overall_misses::total 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14179500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14179500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14179500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14179500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14179500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14179500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14404500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14404500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14404500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14404500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14404500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14404500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses @@ -372,12 +372,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052323 system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58836.099585 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 58836.099585 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 58836.099585 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 58836.099585 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59769.709544 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 59769.709544 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 59769.709544 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 59769.709544 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 59769.709544 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 59769.709544 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -392,43 +392,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 241 system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13938500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13938500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13938500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13938500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13938500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13938500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14163500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14163500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14163500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14163500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14163500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14163500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 57836.099585 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 57836.099585 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 58769.709544 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 58769.709544 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 58769.709544 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 58769.709544 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 58769.709544 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 58769.709544 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 153.328645 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 180.559791 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.091429 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.330622 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 47.998022 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003214 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001465 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004679 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.285464 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 75.274327 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003213 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002297 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005510 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 16 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits @@ -451,18 +451,18 @@ system.cpu.l2cache.demand_misses::total 350 # nu system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses system.cpu.l2cache.overall_misses::total 350 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2558500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2558500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13393000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 13393000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4879000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4879000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13393000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7437500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20830500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13393000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7437500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20830500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2601500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2601500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13618000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 13618000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4961000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4961000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 13618000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7562500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21180500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 13618000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7562500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21180500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 241 # number of ReadCleanReq accesses(hits+misses) @@ -487,18 +487,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.916230 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59524.444444 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59524.444444 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59515.714286 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59515.714286 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60524.444444 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60524.444444 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60524.444444 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60515.714286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60524.444444 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60515.714286 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -517,18 +517,18 @@ system.cpu.l2cache.demand_mshr_misses::total 350 system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2128500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2128500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11143000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11143000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4059000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4059000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11143000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6187500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17330500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11143000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6187500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17330500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2171500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2171500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11368000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11368000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4141000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4141000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11368000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6312500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17680500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11368000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6312500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17680500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadCleanReq accesses @@ -541,25 +541,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49524.444444 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49524.444444 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50524.444444 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50524.444444 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50524.444444 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50515.714286 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50524.444444 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50515.714286 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -591,7 +591,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 361500 # La system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 350 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 307 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution @@ -613,8 +619,8 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 350 # Request fanout histogram system.membus.reqLayer0.occupancy 355500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) system.membus.respLayer1.occupancy 1750000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.2 # Layer utilization (%) +system.membus.respLayer1.utilization 6.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index ba0daa415..fce732112 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000023 # Number of seconds simulated -sim_ticks 22532000 # Number of ticks simulated -final_tick 22532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 22838000 # Number of ticks simulated +final_tick 22838000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94024 # Simulator instruction rate (inst/s) -host_op_rate 93989 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 423490323 # Simulator tick rate (ticks/s) -host_mem_usage 248172 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 76246 # Simulator instruction rate (inst/s) +host_op_rate 76230 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 348191953 # Simulator tick rate (ticks/s) +host_mem_usage 252304 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 4999 # Number of instructions simulated sim_ops 4999 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 21056 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory system.physmem.bytes_read::total 30016 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 21056 # Nu system.physmem.num_reads::cpu.inst 329 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory system.physmem.num_reads::total 469 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 934493165 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 397656666 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1332149831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 934493165 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 934493165 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 934493165 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 397656666 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1332149831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 921972152 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 392328575 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1314300727 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 921972152 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 921972152 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 921972152 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 392328575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1314300727 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 469 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22446500 # Total gap between requests +system.physmem.totGap 22751500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see @@ -187,32 +187,32 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 106 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 257.207547 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 176.154447 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 250.139569 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 32 30.19% 30.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 32 30.19% 60.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 19 17.92% 78.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 9 8.49% 86.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 3.77% 90.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 1.89% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 1.89% 94.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6 5.66% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 106 # Bytes accessed per row activation -system.physmem.totQLat 4611250 # Total ticks spent queuing -system.physmem.totMemAccLat 13405000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 105 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 259.047619 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.738362 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 250.145511 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 30 28.57% 28.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 33 31.43% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 19 18.10% 78.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 9 8.57% 86.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 3.81% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 1.90% 92.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 1.90% 94.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6 5.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 105 # Bytes accessed per row activation +system.physmem.totQLat 4619250 # Total ticks spent queuing +system.physmem.totMemAccLat 13413000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9832.09 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9849.15 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28582.09 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1332.15 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28599.15 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1314.30 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1332.15 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1314.30 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.41 # Data bus utilization in percentage -system.physmem.busUtilRead 10.41 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.27 # Data bus utilization in percentage +system.physmem.busUtilRead 10.27 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,49 +220,49 @@ system.physmem.readRowHits 353 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 75.27 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 47860.34 # Average gap between requests +system.physmem.avgGap 48510.66 # Average gap between requests system.physmem.pageHitRate 75.27 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 538200 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 514800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 9591390 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1086000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 12431355 # Total energy per rank (pJ) -system.physmem_0.averagePower 785.179536 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2005750 # Time in different power states +system.physmem_0.actBackEnergy 9522135 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1146750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12399450 # Total energy per rank (pJ) +system.physmem_0.averagePower 783.164377 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1868000 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 13559250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 13458250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 529200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 288750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2176200 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 521640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 284625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2168400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10730250 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 87000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14828520 # Total energy per rank (pJ) -system.physmem_1.averagePower 936.587399 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 103500 # Time in different power states +system.physmem_1.actBackEnergy 10729395 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 87750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14808930 # Total energy per rank (pJ) +system.physmem_1.averagePower 935.350071 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 200750 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15222750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15221750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2183 # Number of BP lookups -system.cpu.branchPred.condPredicted 1455 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 2189 # Number of BP lookups +system.cpu.branchPred.condPredicted 1457 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 425 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1779 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 1784 # Number of BTB lookups system.cpu.branchPred.BTBHits 587 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.996065 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 250 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 32.903587 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 251 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 269 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 270 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 2 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 267 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 268 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 96 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits @@ -284,95 +284,95 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 22532000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 45065 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 22838000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 45677 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 9068 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12986 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2183 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 839 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4746 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 9081 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13012 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2189 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 840 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4774 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 870 # Number of cycles fetch has spent squashing system.cpu.fetch.PendingTrapStallCycles 205 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2047 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14454 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.898436 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.187928 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2050 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14495 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.897689 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.187204 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11097 76.77% 76.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1507 10.43% 87.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 110 0.76% 87.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 162 1.12% 89.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 279 1.93% 91.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 99 0.68% 91.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 140 0.97% 92.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 158 1.09% 93.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 902 6.24% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11134 76.81% 76.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1506 10.39% 87.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 111 0.77% 87.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 162 1.12% 89.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 279 1.92% 91.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 100 0.69% 91.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 142 0.98% 92.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 158 1.09% 93.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 903 6.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14454 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.048441 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.288162 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8443 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2703 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2773 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 14495 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.047923 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.284870 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8449 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2734 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2777 # Number of cycles decode is running system.cpu.decode.UnblockCycles 140 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 395 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 182 # Number of times decode resolved a branch +system.cpu.decode.BranchResolved 183 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 40 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12006 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12026 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 160 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 395 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8593 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 592 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 973 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2745 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1156 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11571 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 8600 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 597 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 983 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2748 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1172 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11590 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 175 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 954 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 6940 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13573 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13340 # Number of integer rename lookups +system.cpu.rename.LQFullEvents 177 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 968 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 6955 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13597 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13364 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3292 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3648 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3663 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 13 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 307 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2471 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2472 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9030 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9034 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 10 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8122 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8125 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4040 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2024 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 4044 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2026 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14454 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.561921 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.290505 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14495 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.560538 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.289389 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11129 77.00% 77.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1334 9.23% 86.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 725 5.02% 91.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 461 3.19% 94.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 340 2.35% 96.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 284 1.96% 98.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 111 0.77% 99.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 51 0.35% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11167 77.04% 77.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1340 9.24% 86.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 721 4.97% 91.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 460 3.17% 94.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 343 2.37% 96.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 283 1.95% 98.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 110 0.76% 99.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 52 0.36% 99.87% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14454 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14495 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 7 3.87% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.87% # attempts to use FU when none available @@ -408,54 +408,54 @@ system.cpu.iq.fu_full::MemWrite 57 31.49% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4782 58.88% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4784 58.88% 58.88% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.93% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2272 27.97% 86.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2273 27.98% 86.94% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1061 13.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8122 # Type of FU issued -system.cpu.iq.rate 0.180229 # Inst issue rate +system.cpu.iq.FU_type_0::total 8125 # Type of FU issued +system.cpu.iq.rate 0.177879 # Inst issue rate system.cpu.iq.fu_busy_cnt 181 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022285 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30894 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 13087 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7350 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.022277 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30941 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 13095 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7347 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8301 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8304 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1336 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1337 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 257 # Number of stores squashed @@ -465,54 +465,54 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 0 # system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 395 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 490 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10642 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 148 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2471 # Number of dispatched load instructions +system.cpu.iew.iewBlockCycles 491 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10646 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 156 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2472 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 10 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 57 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 59 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 338 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 439 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7800 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2128 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 322 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 339 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 440 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7799 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2130 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 326 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 1602 # number of nop insts executed -system.cpu.iew.exec_refs 3177 # number of memory reference insts executed -system.cpu.iew.exec_branches 1369 # Number of branches executed +system.cpu.iew.exec_refs 3179 # number of memory reference insts executed +system.cpu.iew.exec_branches 1368 # Number of branches executed system.cpu.iew.exec_stores 1049 # Number of stores executed -system.cpu.iew.exec_rate 0.173083 # Inst execution rate -system.cpu.iew.wb_sent 7447 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7352 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2874 # num instructions producing a value +system.cpu.iew.exec_rate 0.170742 # Inst execution rate +system.cpu.iew.wb_sent 7444 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7349 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2873 # num instructions producing a value system.cpu.iew.wb_consumers 4285 # num instructions consuming a value -system.cpu.iew.wb_rate 0.163142 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.670712 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4995 # The number of squashed insts skipped by commit +system.cpu.iew.wb_rate 0.160891 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.670478 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 4999 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 385 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13572 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.415561 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.228101 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 13612 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.414340 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.226502 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11381 83.86% 83.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 886 6.53% 90.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 519 3.82% 94.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 254 1.87% 96.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 162 1.19% 97.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 163 1.20% 98.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 62 0.46% 98.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.30% 99.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 104 0.77% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11422 83.91% 83.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 884 6.49% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 520 3.82% 94.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 254 1.87% 96.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 161 1.18% 97.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 165 1.21% 98.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 61 0.45% 98.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.30% 99.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 104 0.76% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13572 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13612 # Number of insts commited each cycle system.cpu.commit.committedInsts 5640 # Number of instructions committed system.cpu.commit.committedOps 5640 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -559,46 +559,46 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5640 # Class of committed instruction system.cpu.commit.bw_lim_events 104 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 24090 # The number of ROB reads -system.cpu.rob.rob_writes 22160 # The number of ROB writes -system.cpu.timesIdled 263 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30611 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 24134 # The number of ROB reads +system.cpu.rob.rob_writes 22169 # The number of ROB writes +system.cpu.timesIdled 264 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 31182 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4999 # Number of Instructions Simulated system.cpu.committedOps 4999 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 9.014803 # CPI: Cycles Per Instruction -system.cpu.cpi_total 9.014803 # CPI: Total CPI of All Threads -system.cpu.ipc 0.110929 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.110929 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10573 # number of integer regfile reads -system.cpu.int_regfile_writes 5151 # number of integer regfile writes +system.cpu.cpi 9.137227 # CPI: Cycles Per Instruction +system.cpu.cpi_total 9.137227 # CPI: Total CPI of All Threads +system.cpu.ipc 0.109442 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.109442 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10569 # number of integer regfile reads +system.cpu.int_regfile_writes 5149 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 160 # number of misc regfile reads -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 90.625823 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2393 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 90.737808 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.092857 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.107143 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 90.625823 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022125 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022125 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 90.737808 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022153 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022153 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5950 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5950 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1837 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1837 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5954 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5954 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 1839 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1839 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2393 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2393 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2393 # number of overall hits -system.cpu.dcache.overall_hits::total 2393 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits +system.cpu.dcache.overall_hits::total 2395 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 345 # number of WriteReq misses @@ -607,43 +607,43 @@ system.cpu.dcache.demand_misses::cpu.data 512 # n system.cpu.dcache.demand_misses::total 512 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 512 # number of overall misses system.cpu.dcache.overall_misses::total 512 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11867500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11867500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24012499 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24012499 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35879999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35879999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35879999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35879999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2004 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2004 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12256500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12256500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24340499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24340499 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36596999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36596999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36596999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36596999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2006 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2006 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2905 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2905 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2905 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2905 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083333 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.083333 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2907 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2907 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2907 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2907 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083250 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.083250 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.382908 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.382908 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.176248 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.176248 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.176248 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.176248 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71062.874251 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71062.874251 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69601.446377 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69601.446377 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70078.123047 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70078.123047 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 70078.123047 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 70078.123047 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 592 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.176127 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.176127 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.176127 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.176127 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73392.215569 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73392.215569 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70552.171014 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70552.171014 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71478.513672 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71478.513672 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71478.513672 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71478.513672 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 600 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits @@ -661,83 +661,83 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 140 system.cpu.dcache.demand_mshr_misses::total 140 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 140 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7550000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7550000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4082999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4082999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11632999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11632999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11632999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11632999 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044910 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044910 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7898000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7898000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4132999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4132999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12030999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12030999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12030999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12030999 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044865 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044865 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048193 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048193 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048193 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048193 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83888.888889 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83888.888889 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81659.980000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81659.980000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83092.850000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83092.850000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048160 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048160 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048160 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048160 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87755.555556 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87755.555556 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82659.980000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82659.980000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 85935.707143 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 85935.707143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 85935.707143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 85935.707143 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 158.780297 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1610 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 158.952170 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1612 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 332 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.849398 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.855422 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 158.780297 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077529 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077529 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 158.952170 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077613 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077613 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 315 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.153809 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4426 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4426 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1610 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1610 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1610 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1610 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1610 # number of overall hits -system.cpu.icache.overall_hits::total 1610 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses -system.cpu.icache.overall_misses::total 437 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32774000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32774000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32774000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32774000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32774000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32774000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2047 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2047 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2047 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2047 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2047 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2047 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.213483 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.213483 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.213483 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.213483 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.213483 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.213483 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74997.711670 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74997.711670 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74997.711670 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74997.711670 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74997.711670 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74997.711670 # average overall miss latency +system.cpu.icache.tags.tag_accesses 4432 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4432 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1612 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1612 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1612 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1612 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1612 # number of overall hits +system.cpu.icache.overall_hits::total 1612 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 438 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 438 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 438 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 438 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 438 # number of overall misses +system.cpu.icache.overall_misses::total 438 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 33275000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 33275000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 33275000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 33275000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 33275000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 33275000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2050 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2050 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2050 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2050 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2050 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2050 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.213659 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.213659 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.213659 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.213659 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.213659 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.213659 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75970.319635 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75970.319635 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75970.319635 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75970.319635 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75970.319635 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75970.319635 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -746,55 +746,55 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 17 # number of writebacks system.cpu.icache.writebacks::total 17 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 105 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 105 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 105 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 105 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 105 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 105 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 106 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 106 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 106 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 106 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 106 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 106 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 332 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 332 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 332 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26055500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26055500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26055500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26055500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26055500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 26055500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.162189 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.162189 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.162189 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.162189 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162189 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.162189 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78480.421687 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78480.421687 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78480.421687 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78480.421687 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26133000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26133000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26133000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26133000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26133000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26133000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161951 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.161951 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.161951 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78713.855422 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78713.855422 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78713.855422 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 78713.855422 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78713.855422 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 78713.855422 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 218.003826 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 251.694203 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 419 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.047733 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 469 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.042644 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.713393 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.290433 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004905 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001748 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006653 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012787 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.892029 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 90.802174 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004910 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002771 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007681 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 469 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014313 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4381 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 17 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 17 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits @@ -815,18 +815,18 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 329 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 140 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4007000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4007000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25524500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 25524500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7412000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7412000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 25524500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11419000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 36943500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 25524500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11419000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 36943500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4057000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4057000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25602000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 25602000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7760000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7760000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 25602000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11817000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 37419000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 25602000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11817000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 37419000 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) @@ -853,18 +853,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.993644 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990964 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80140 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80140 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77582.066869 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77582.066869 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82355.555556 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82355.555556 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77582.066869 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81564.285714 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78770.788913 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77582.066869 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81564.285714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78770.788913 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81140 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81140 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77817.629179 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77817.629179 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86222.222222 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86222.222222 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77817.629179 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84407.142857 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79784.648188 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77817.629179 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84407.142857 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79784.648188 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -883,18 +883,18 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 329 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3507000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3507000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22234500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22234500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6512000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6512000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22234500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10019000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 32253500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22234500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10019000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 32253500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3557000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3557000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22312000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22312000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6860000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6860000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22312000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10417000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 32729000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22312000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10417000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 32729000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for ReadCleanReq accesses @@ -907,25 +907,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993644 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70140 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70140 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67582.066869 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67582.066869 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72355.555556 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72355.555556 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67582.066869 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71564.285714 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68770.788913 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67582.066869 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71564.285714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68770.788913 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71140 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71140 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67817.629179 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67817.629179 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76222.222222 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76222.222222 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67817.629179 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74407.142857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69784.648188 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67817.629179 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74407.142857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69784.648188 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -952,12 +952,18 @@ system.cpu.toL2Bus.snoop_fanout::min_value 0 # system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 472 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 261500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 498000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 210000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 469 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 419 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution system.membus.trans_dist::ReadExResp 50 # Transaction distribution @@ -978,9 +984,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 469 # Request fanout histogram -system.membus.reqLayer0.occupancy 582000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2494000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.1 # Layer utilization (%) +system.membus.reqLayer0.occupancy 581500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 2494250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 10.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt index 619b5f6ac..fd6e40c23 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2820500 # Number of ticks simulated final_tick 2820500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 890532 # Simulator instruction rate (inst/s) -host_op_rate 888973 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 443763917 # Simulator tick rate (ticks/s) -host_mem_usage 236392 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 280567 # Simulator instruction rate (inst/s) +host_op_rate 280375 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 140096420 # Simulator tick rate (ticks/s) +host_mem_usage 239748 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -116,6 +116,12 @@ system.cpu.op_class::MemWrite 902 15.99% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 2820500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6777 # Transaction distribution system.membus.trans_dist::ReadResp 6777 # Transaction distribution @@ -130,14 +136,14 @@ system.membus.pkt_size::total 30470 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 7678 # Request fanout histogram -system.membus.snoop_fanout::mean 0.734827 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.441454 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2036 26.52% 26.52% # Request fanout histogram -system.membus.snoop_fanout::1 5642 73.48% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7678 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7678 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 29abc2b26..657853e9f 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000034 # Number of seconds simulated -sim_ticks 33932500 # Number of ticks simulated -final_tick 33932500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 34362500 # Number of ticks simulated +final_tick 34362500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 18620 # Simulator instruction rate (inst/s) -host_op_rate 18619 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 111991731 # Simulator tick rate (ticks/s) -host_mem_usage 246380 # Number of bytes of host memory used -host_seconds 0.30 # Real time elapsed on the host +host_inst_rate 251821 # Simulator instruction rate (inst/s) +host_op_rate 251667 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1532173253 # Simulator tick rate (ticks/s) +host_mem_usage 250252 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8768 # Number of bytes read from this memory system.physmem.bytes_read::total 27520 # Number of bytes read from this memory @@ -22,15 +22,15 @@ system.physmem.bytes_inst_read::total 18752 # Nu system.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory system.physmem.num_reads::total 430 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 552626538 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 258395344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 811021882 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 552626538 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 552626538 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 552626538 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 258395344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 811021882 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 545711168 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 255161877 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 800873045 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 545711168 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 545711168 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 545711168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 255161877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 800873045 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -51,8 +51,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 33932500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 67865 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 34362500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 68725 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5641 # Number of instructions committed @@ -71,7 +71,7 @@ system.cpu.num_mem_refs 2037 # nu system.cpu.num_load_insts 1135 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 67865 # Number of busy cycles +system.cpu.num_busy_cycles 68725 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 886 # Number of branches fetched @@ -110,23 +110,23 @@ system.cpu.op_class::MemWrite 902 15.99% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.030444 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 86.019878 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.030444 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021004 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021004 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.019878 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021001 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021001 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits @@ -143,14 +143,14 @@ system.cpu.dcache.demand_misses::cpu.data 137 # n system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses system.cpu.dcache.overall_misses::total 137 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5394000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5394000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3100000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3100000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8494000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8494000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8494000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8494000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5481000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5481000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3150000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3150000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8631000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8631000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8631000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8631000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) @@ -167,14 +167,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.067289 system.cpu.dcache.demand_miss_rate::total 0.067289 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.067289 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.067289 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -189,14 +189,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 137 system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5307000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5307000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3050000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3050000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8357000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8357000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8357000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8357000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5394000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5394000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3100000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3100000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8494000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8494000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8494000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8494000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076652 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076652 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses @@ -205,31 +205,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067289 system.cpu.dcache.demand_mshr_miss_rate::total 0.067289 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.067289 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 128.953338 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 128.944610 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5348 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.128814 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 128.953338 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.062965 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.062965 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 128.944610 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.062961 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.062961 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 11581 # Number of tag accesses system.cpu.icache.tags.data_accesses 11581 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 5348 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5348 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5348 # number of demand (read+write) hits @@ -242,12 +242,12 @@ system.cpu.icache.demand_misses::cpu.inst 295 # n system.cpu.icache.demand_misses::total 295 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 295 # number of overall misses system.cpu.icache.overall_misses::total 295 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18192500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18192500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18192500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18192500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18192500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18192500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18485500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18485500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18485500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18485500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18485500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18485500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5643 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5643 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5643 # number of demand (read+write) accesses @@ -260,12 +260,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052277 system.cpu.icache.demand_miss_rate::total 0.052277 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052277 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052277 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61669.491525 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61669.491525 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61669.491525 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61669.491525 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62662.711864 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62662.711864 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62662.711864 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62662.711864 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62662.711864 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62662.711864 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -280,43 +280,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 295 system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17897500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17897500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17897500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17897500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17897500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17897500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18190500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 18190500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18190500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 18190500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18190500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 18190500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052277 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052277 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052277 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60669.491525 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60669.491525 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61662.711864 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61662.711864 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61662.711864 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61662.711864 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61662.711864 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61662.711864 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 183.490494 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 216.139082 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.039474 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 430 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.034884 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.087016 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 53.403478 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.077342 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 86.061740 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003970 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001630 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005600 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011597 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002626 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006596 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013123 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3990 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3990 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 13 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 13 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits @@ -337,18 +337,18 @@ system.cpu.l2cache.demand_misses::total 430 # nu system.cpu.l2cache.overall_misses::cpu.inst 293 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses system.cpu.l2cache.overall_misses::total 430 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2975000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2975000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 17434000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 17434000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5176500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 5176500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 17434000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8151500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 25585500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 17434000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8151500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 25585500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3025000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3025000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 17727000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 17727000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5263500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 5263500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 17727000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8288500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 26015500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 17727000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8288500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 26015500 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 13 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 13 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) @@ -375,18 +375,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.995370 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993220 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995370 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.706485 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.706485 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.706485 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59501.162791 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.706485 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59501.162791 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.706485 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.706485 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.706485 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60501.162791 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.706485 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60501.162791 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -405,18 +405,18 @@ system.cpu.l2cache.demand_mshr_misses::total 430 system.cpu.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2475000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2475000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14504000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14504000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4306500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4306500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14504000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6781500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 21285500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14504000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6781500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 21285500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2525000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2525000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14797000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14797000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4393500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4393500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14797000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6918500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21715500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14797000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6918500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21715500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for ReadCleanReq accesses @@ -429,25 +429,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995370 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995370 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.706485 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.706485 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.706485 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.706485 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.706485 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.162791 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.706485 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.162791 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 13 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 13 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -479,7 +479,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 442500 # La system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 430 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 380 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution system.membus.trans_dist::ReadExResp 50 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index a1b1af10d..ee06020dc 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19908000 # Number of ticks simulated -final_tick 19908000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20159000 # Number of ticks simulated +final_tick 20159000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79311 # Simulator instruction rate (inst/s) -host_op_rate 79299 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 272523705 # Simulator tick rate (ticks/s) -host_mem_usage 246096 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 70194 # Simulator instruction rate (inst/s) +host_op_rate 70182 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 244226628 # Simulator tick rate (ticks/s) +host_mem_usage 249960 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 6400 # Number of bytes read from this memory system.physmem.bytes_read::total 28352 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 21952 # Nu system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 100 # Number of read requests responded to by this memory system.physmem.num_reads::total 443 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1102672293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 321478802 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1424151095 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1102672293 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1102672293 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1102672293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 321478802 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1424151095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1088942904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 317476065 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1406418969 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1088942904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1088942904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1088942904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 317476065 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1406418969 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 445 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 445 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 19857500 # Total gap between requests +system.physmem.totGap 20108500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -189,31 +189,30 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 341.894737 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 206.686426 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 337.291153 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 25 32.89% 32.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 22.37% 55.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10 13.16% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 206.930275 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 338.261263 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24 31.58% 31.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 25.00% 56.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 11.84% 68.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 3 3.95% 72.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 4 5.26% 77.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 4 5.26% 82.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 1.32% 84.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 3.95% 88.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 11.84% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5 6.58% 89.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8 10.53% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation -system.physmem.totQLat 3759500 # Total ticks spent queuing -system.physmem.totMemAccLat 12103250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3790750 # Total ticks spent queuing +system.physmem.totMemAccLat 12134500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8448.31 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8518.54 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27198.31 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1430.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27268.54 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1412.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1430.58 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1412.77 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.18 # Data bus utilization in percentage -system.physmem.busUtilRead 11.18 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.04 # Data bus utilization in percentage +system.physmem.busUtilRead 11.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.78 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -221,37 +220,37 @@ system.physmem.readRowHits 360 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.90 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 44623.60 # Average gap between requests +system.physmem.avgGap 45187.64 # Average gap between requests system.physmem.pageHitRate 80.90 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 438480 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 239250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2511600 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 2496000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10783260 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 40500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 15030210 # Total energy per rank (pJ) -system.physmem_0.averagePower 949.326386 # Core power per rank (mW) +system.physmem_0.actBackEnergy 10814895 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 15037995 # Total energy per rank (pJ) +system.physmem_0.averagePower 947.872361 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15347250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 68040 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 37125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 288600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 7632585 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2804250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 11847720 # Total energy per rank (pJ) -system.physmem_1.averagePower 748.316438 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 6301750 # Time in different power states +system.physmem_1.actBackEnergy 7519725 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2903250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 11833860 # Total energy per rank (pJ) +system.physmem_1.averagePower 747.441023 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 6690750 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 10721750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 10557750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 2407 # Number of BP lookups system.cpu.branchPred.condPredicted 1979 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 409 # Number of conditional branches incorrect @@ -285,96 +284,96 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 19908000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 39817 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 20159000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 40319 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7705 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13362 # Number of instructions fetch has processed +system.cpu.fetch.icacheStallCycles 7699 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13357 # Number of instructions fetch has processed system.cpu.fetch.Branches 2407 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 936 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3591 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 4134 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 847 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 146 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1856 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 289 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11892 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.123613 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.518960 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1855 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 288 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12429 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.074664 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.474276 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9557 80.36% 80.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 166 1.40% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 217 1.82% 83.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 147 1.24% 84.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 245 2.06% 86.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 147 1.24% 88.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 275 2.31% 90.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 148 1.24% 91.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 990 8.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10095 81.22% 81.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 166 1.34% 82.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 217 1.75% 84.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 147 1.18% 85.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 245 1.97% 87.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 146 1.17% 88.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 275 2.21% 90.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 148 1.19% 92.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 990 7.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11892 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.060452 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.335585 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7298 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2243 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 12429 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.059699 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.331283 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7289 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2789 # Number of cycles decode is blocked system.cpu.decode.RunCycles 1948 # Number of cycles decode is running system.cpu.decode.UnblockCycles 128 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 275 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 323 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 149 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11471 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 450 # Number of squashed instructions handled by decode +system.cpu.decode.DecodedInsts 11479 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 451 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 275 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7466 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 800 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 447 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1898 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1006 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11040 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 7458 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 805 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 449 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1896 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1546 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11044 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 965 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9709 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17887 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17861 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 1504 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9711 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17893 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17867 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4711 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4713 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 354 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 365 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 1936 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1591 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10171 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 10175 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8811 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8810 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4442 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3468 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 4446 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3475 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11892 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.740918 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.536831 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12429 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.708826 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.510537 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8764 73.70% 73.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 985 8.28% 81.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 659 5.54% 87.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 457 3.84% 91.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 433 3.64% 95.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 285 2.40% 97.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 215 1.81% 99.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 62 0.52% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 32 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9301 74.83% 74.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 985 7.93% 82.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 659 5.30% 88.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 457 3.68% 91.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 433 3.48% 95.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 286 2.30% 97.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 214 1.72% 99.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 62 0.50% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 32 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11892 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12429 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 12 6.35% 6.35% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 6.35% # attempts to use FU when none available @@ -413,66 +412,66 @@ system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Ty system.cpu.iq.FU_type_0::IntAlu 5533 62.80% 62.80% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.80% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1812 20.57% 83.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1811 20.56% 83.38% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1464 16.62% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8811 # Type of FU issued -system.cpu.iq.rate 0.221287 # Inst issue rate +system.cpu.iq.FU_type_0::total 8810 # Type of FU issued +system.cpu.iq.rate 0.218507 # Inst issue rate system.cpu.iq.fu_busy_cnt 189 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021450 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29694 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14646 # Number of integer instruction queue writes +system.cpu.iq.fu_busy_rate 0.021453 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30229 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14654 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 8112 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8966 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8965 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 83 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 975 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 545 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 546 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 275 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 716 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 721 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 77 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10234 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 10238 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 1936 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1591 # Number of dispatched store instructions +system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 53 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 66 # Number of times the LSQ has become full, causing a stall @@ -482,39 +481,39 @@ system.cpu.iew.predictedNotTakenIncorrect 256 # N system.cpu.iew.branchMispredicts 324 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 8460 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 1699 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 351 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 350 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iew.exec_refs 3077 # number of memory reference insts executed -system.cpu.iew.exec_branches 1357 # Number of branches executed +system.cpu.iew.exec_branches 1359 # Number of branches executed system.cpu.iew.exec_stores 1378 # Number of stores executed -system.cpu.iew.exec_rate 0.212472 # Inst execution rate +system.cpu.iew.exec_rate 0.209827 # Inst execution rate system.cpu.iew.wb_sent 8239 # cumulative count of insts sent to commit system.cpu.iew.wb_count 8139 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4434 # num instructions producing a value -system.cpu.iew.wb_consumers 7122 # num instructions consuming a value -system.cpu.iew.wb_rate 0.204410 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.622578 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4444 # The number of squashed insts skipped by commit +system.cpu.iew.wb_producers 4432 # num instructions producing a value +system.cpu.iew.wb_consumers 7119 # num instructions consuming a value +system.cpu.iew.wb_rate 0.201865 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.622559 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 4448 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 270 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11191 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.517559 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.381685 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11727 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.493903 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.354058 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9014 80.55% 80.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 859 7.68% 88.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 529 4.73% 92.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 217 1.94% 94.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 185 1.65% 96.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 107 0.96% 97.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 121 1.08% 98.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 49 0.44% 99.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 110 0.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9550 81.44% 81.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 859 7.32% 88.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 529 4.51% 93.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 217 1.85% 95.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 185 1.58% 96.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 107 0.91% 97.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 121 1.03% 98.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 49 0.42% 99.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 110 0.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11191 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11727 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -561,37 +560,37 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5792 # Class of committed instruction system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 21317 # The number of ROB reads -system.cpu.rob.rob_writes 21174 # The number of ROB writes -system.cpu.timesIdled 231 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27925 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21857 # The number of ROB reads +system.cpu.rob.rob_writes 21183 # The number of ROB writes +system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27890 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.874482 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.874482 # CPI: Total CPI of All Threads -system.cpu.ipc 0.145466 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.145466 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13370 # number of integer regfile reads -system.cpu.int_regfile_writes 7150 # number of integer regfile writes +system.cpu.cpi 6.961153 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.961153 # CPI: Total CPI of All Threads +system.cpu.ipc 0.143654 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.143654 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13369 # number of integer regfile reads +system.cpu.int_regfile_writes 7149 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 64.466372 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 64.445386 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2199 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 21.558824 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 64.466372 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.015739 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.015739 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 64.445386 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.015734 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.015734 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 75 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 5374 # Number of tag accesses system.cpu.dcache.tags.data_accesses 5374 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits @@ -608,14 +607,14 @@ system.cpu.dcache.demand_misses::cpu.data 437 # n system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses system.cpu.dcache.overall_misses::total 437 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7807000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7807000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23805496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23805496 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31612496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31612496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31612496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31612496 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7904000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7904000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 32053496 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 32053496 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39957496 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39957496 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39957496 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39957496 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1590 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1590 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -632,19 +631,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.165781 system.cpu.dcache.demand_miss_rate::total 0.165781 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.165781 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.165781 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69088.495575 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 69088.495575 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73473.753086 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73473.753086 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72339.807780 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72339.807780 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72339.807780 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72339.807780 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 598 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69946.902655 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 69946.902655 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 98930.543210 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 98930.543210 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 91435.917620 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 91435.917620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 91435.917620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 91435.917620 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 604 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 100.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits @@ -662,14 +661,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 104 system.cpu.dcache.demand_mshr_misses::total 104 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 104 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 104 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4432500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4432500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4005998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4005998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8438498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8438498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8438498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8438498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4485500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4485500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4548998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4548998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9034498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9034498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9034498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9034498 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035849 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035849 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses @@ -678,72 +677,72 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.039454 system.cpu.dcache.demand_mshr_miss_rate::total 0.039454 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.039454 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.039454 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77763.157895 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77763.157895 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85234 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85234 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81139.403846 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81139.403846 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78692.982456 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78692.982456 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 96787.191489 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 96787.191489 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86870.173077 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 86870.173077 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86870.173077 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 86870.173077 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 169.073673 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1420 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 169.030938 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1419 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.068768 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.065903 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 169.073673 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.082556 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.082556 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 169.030938 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082535 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082535 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4061 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4061 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1420 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1420 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1420 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1420 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1420 # number of overall hits -system.cpu.icache.overall_hits::total 1420 # number of overall hits +system.cpu.icache.tags.tag_accesses 4059 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4059 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1419 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1419 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1419 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1419 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1419 # number of overall hits +system.cpu.icache.overall_hits::total 1419 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 436 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 436 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 436 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 436 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 436 # number of overall misses system.cpu.icache.overall_misses::total 436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32169000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32169000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32169000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32169000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32169000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32169000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1856 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1856 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1856 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1856 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1856 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1856 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234914 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.234914 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.234914 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.234914 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.234914 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.234914 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73782.110092 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 73782.110092 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 73782.110092 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 73782.110092 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 73782.110092 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73782.110092 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 497 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31654500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31654500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31654500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31654500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31654500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31654500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1855 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1855 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1855 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1855 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1855 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1855 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.235040 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.235040 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.235040 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.235040 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.235040 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.235040 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72602.064220 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72602.064220 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72602.064220 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72602.064220 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72602.064220 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72602.064220 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 507 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 99.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 101.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits @@ -757,43 +756,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 350 system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26574000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26574000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26574000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26574000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26574000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 26574000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188578 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188578 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188578 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.188578 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188578 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.188578 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75925.714286 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75925.714286 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75925.714286 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75925.714286 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26454000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26454000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26454000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26454000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26454000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26454000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188679 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188679 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188679 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.188679 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188679 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.188679 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75582.857143 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75582.857143 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75582.857143 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75582.857143 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75582.857143 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75582.857143 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 199.665471 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 231.417144 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 396 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.020202 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 443 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.018059 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.879354 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.786117 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005123 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000970 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006093 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012085 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.835616 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 63.581529 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005122 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001940 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007062 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 443 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013519 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4075 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4075 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 6 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 6 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits @@ -816,18 +815,18 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 102 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3932000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25981000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 25981000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4326000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4326000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 25981000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8258000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34239000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 25981000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8258000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34239000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4475000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4475000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25861000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 25861000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4379000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4379000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 25861000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8854000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34715000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 25861000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8854000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34715000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 350 # number of ReadCleanReq accesses(hits+misses) @@ -852,18 +851,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.982379 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982857 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.980769 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.982379 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83659.574468 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83659.574468 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75526.162791 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75526.162791 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78654.545455 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78654.545455 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75526.162791 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80960.784314 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76769.058296 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75526.162791 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80960.784314 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76769.058296 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95212.765957 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95212.765957 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75177.325581 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75177.325581 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79618.181818 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79618.181818 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75177.325581 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86803.921569 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77836.322870 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75177.325581 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86803.921569 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77836.322870 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -882,18 +881,18 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3462000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3462000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22551000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22551000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3796000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3796000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22551000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7258000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29809000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22551000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7258000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 29809000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4005000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4005000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22431000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22431000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3849000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3849000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22431000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7854000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30285000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22431000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7854000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30285000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadCleanReq accesses @@ -906,25 +905,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.982379 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980769 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.982379 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73659.574468 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73659.574468 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65555.232558 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65555.232558 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69018.181818 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69018.181818 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65555.232558 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71156.862745 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66836.322870 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65555.232558 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71156.862745 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66836.322870 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85212.765957 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85212.765957 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65206.395349 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65206.395349 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69981.818182 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69981.818182 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65206.395349 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67903.587444 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65206.395349 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67903.587444 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 454 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 8 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution @@ -955,7 +954,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 523500 # La system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 396 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution system.membus.trans_dist::ReadExResp 47 # Transaction distribution @@ -977,8 +982,8 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 445 # Request fanout histogram system.membus.reqLayer0.occupancy 553500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 2338750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.7 # Layer utilization (%) +system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 2340000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt index c2dda4058..55872626c 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2896000 # Number of ticks simulated final_tick 2896000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 667625 # Simulator instruction rate (inst/s) -host_op_rate 666766 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 332924076 # Simulator tick rate (ticks/s) -host_mem_usage 235336 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 247008 # Simulator instruction rate (inst/s) +host_op_rate 246868 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 123347407 # Simulator tick rate (ticks/s) +host_mem_usage 238692 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5793 # Number of instructions simulated sim_ops 5793 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -116,6 +116,12 @@ system.cpu.op_class::MemWrite 1046 18.06% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5793 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 2896000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6754 # Transaction distribution system.membus.trans_dist::ReadResp 6754 # Transaction distribution @@ -130,14 +136,14 @@ system.membus.pkt_size::total 31101 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 7800 # Request fanout histogram -system.membus.snoop_fanout::mean 0.742692 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.437178 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2007 25.73% 25.73% # Request fanout histogram -system.membus.snoop_fanout::1 5793 74.27% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7800 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7800 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt index c6c8dc595..7638ef846 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 588885 # Simulator instruction rate (inst/s) -host_op_rate 587162 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 296343205 # Simulator tick rate (ticks/s) -host_mem_usage 237088 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 238347 # Simulator instruction rate (inst/s) +host_op_rate 238214 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 120430561 # Simulator tick rate (ticks/s) +host_mem_usage 240180 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -98,6 +98,12 @@ system.cpu.op_class::MemWrite 678 12.63% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5370 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 2694500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6085 # Transaction distribution system.membus.trans_dist::ReadResp 6085 # Transaction distribution @@ -112,14 +118,14 @@ system.membus.pkt_size::total 31147 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 6758 # Request fanout histogram -system.membus.snoop_fanout::mean 0.794614 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.404013 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1388 20.54% 20.54% # Request fanout histogram -system.membus.snoop_fanout::1 5370 79.46% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 6758 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 6758 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index 61bfb723b..9112c70f3 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 30526500 # Number of ticks simulated -final_tick 30526500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 30915500 # Number of ticks simulated +final_tick 30915500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 232577 # Simulator instruction rate (inst/s) -host_op_rate 232336 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1330299281 # Simulator tick rate (ticks/s) -host_mem_usage 247080 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 184246 # Simulator instruction rate (inst/s) +host_op_rate 184150 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1068222426 # Simulator tick rate (ticks/s) +host_mem_usage 250688 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory system.physmem.bytes_read::total 24896 # Number of bytes read from this memory @@ -22,19 +22,19 @@ system.physmem.bytes_inst_read::total 16320 # Nu system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 389 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 534617464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 280936236 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 815553699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 534617464 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 534617464 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 534617464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 280936236 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 815553699 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 527890540 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 277401304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 805291844 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 527890540 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 527890540 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 527890540 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 277401304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 805291844 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 30526500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 61053 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 30915500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 61831 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5327 # Number of instructions committed @@ -53,7 +53,7 @@ system.cpu.num_mem_refs 1401 # nu system.cpu.num_load_insts 723 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 61052.998000 # Number of busy cycles +system.cpu.num_busy_cycles 61830.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1121 # Number of branches fetched @@ -92,23 +92,23 @@ system.cpu.op_class::MemWrite 678 12.63% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5370 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.961543 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 81.942328 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.961543 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020010 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020010 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 81.942328 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020005 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020005 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits @@ -125,14 +125,14 @@ system.cpu.dcache.demand_misses::cpu.data 135 # n system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses system.cpu.dcache.overall_misses::total 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3300000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3300000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5022000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5022000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8322000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8322000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8322000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8322000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3353000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3353000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5103000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5103000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8456000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8456000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8456000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8456000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -149,14 +149,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61111.111111 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61111.111111 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61644.444444 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61644.444444 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61644.444444 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61644.444444 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62092.592593 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62092.592593 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62637.037037 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62637.037037 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62637.037037 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62637.037037 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -171,14 +171,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3246000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3246000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4941000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4941000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8187000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8187000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8187000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8187000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3299000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3299000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5022000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5022000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8321000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8321000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8321000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8321000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -187,31 +187,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60111.111111 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60111.111111 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61092.592593 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61092.592593 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61637.037037 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 61637.037037 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61637.037037 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 61637.037037 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 116.865384 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 116.844047 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 116.865384 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057063 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057063 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 116.844047 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057053 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057053 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.125488 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 10999 # Number of tag accesses system.cpu.icache.tags.data_accesses 10999 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits @@ -224,12 +224,12 @@ system.cpu.icache.demand_misses::cpu.inst 257 # n system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses system.cpu.icache.overall_misses::total 257 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15838500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15838500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15838500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15838500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15838500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15838500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16093500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16093500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16093500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16093500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16093500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16093500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses @@ -242,12 +242,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.047850 system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61628.404669 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61628.404669 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61628.404669 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61628.404669 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61628.404669 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61628.404669 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62620.622568 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62620.622568 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62620.622568 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62620.622568 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62620.622568 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62620.622568 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -260,43 +260,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 257 system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15581500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15581500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15581500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15581500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15581500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15581500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15836500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15836500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15836500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15836500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15836500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15836500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60628.404669 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60628.404669 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61620.622568 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61620.622568 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61620.622568 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61620.622568 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61620.622568 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61620.622568 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 141.950442 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 197.305193 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 389 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.007712 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.319383 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 25.631059 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003550 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000782 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004332 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009399 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.297024 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 81.008169 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003549 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002472 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006021 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011871 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3525 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3525 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits @@ -319,18 +319,18 @@ system.cpu.l2cache.demand_misses::total 389 # nu system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 389 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4819500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4819500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15173000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 15173000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3153500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3153500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15173000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7973000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23146000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15173000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7973000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23146000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4900500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4900500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15428000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 15428000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3206500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3206500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15428000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8107000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23535000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15428000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8107000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23535000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 257 # number of ReadCleanReq accesses(hits+misses) @@ -355,18 +355,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.992347 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.960784 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.960784 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.960784 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59501.285347 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.960784 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59501.285347 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.960784 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.960784 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.960784 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60501.285347 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.960784 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60501.285347 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -385,18 +385,18 @@ system.cpu.l2cache.demand_mshr_misses::total 389 system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4009500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4009500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12623000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12623000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2623500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2623500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12623000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6633000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19256000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12623000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6633000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19256000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4090500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4090500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12878000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12878000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2676500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2676500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12878000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6767000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19645000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12878000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6767000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19645000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadCleanReq accesses @@ -409,25 +409,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.960784 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.960784 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.960784 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.285347 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.960784 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.285347 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.960784 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.960784 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.960784 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.285347 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.960784 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.285347 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 392 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 3 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution @@ -455,10 +455,16 @@ system.cpu.toL2Bus.snoop_fanout::total 392 # Re system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 389 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 308 # Transaction distribution system.membus.trans_dist::ReadExReq 81 # Transaction distribution system.membus.trans_dist::ReadExResp 81 # Transaction distribution @@ -482,6 +488,6 @@ system.membus.snoop_fanout::total 389 # Re system.membus.reqLayer0.occupancy 389500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) system.membus.respLayer1.occupancy 1945000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.4 # Layer utilization (%) +system.membus.respLayer1.utilization 6.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 07049f339..401e565b1 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21273500 # Number of ticks simulated -final_tick 21273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21382500 # Number of ticks simulated +final_tick 21382500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 32077 # Simulator instruction rate (inst/s) -host_op_rate 58109 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 126812951 # Simulator tick rate (ticks/s) -host_mem_usage 266996 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 21602 # Simulator instruction rate (inst/s) +host_op_rate 39134 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 85845466 # Simulator tick rate (ticks/s) +host_mem_usage 271116 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8896 # Number of bytes read from this memory -system.physmem.bytes_read::total 26624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 139 # Number of read requests responded to by this memory -system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 833337251 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 418172844 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1251510095 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 833337251 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 833337251 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 833337251 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 418172844 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1251510095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 416 # Number of read requests accepted +system.physmem.num_reads::total 417 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 832082310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 416041155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1248123465 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 832082310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 832082310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 832082310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 416041155 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1248123465 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 417 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 416 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26624 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 26688 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26624 # Total read bytes from the system interface side +system.physmem.bytesReadSys 26688 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -56,7 +56,7 @@ system.physmem.perBankRdBursts::10 64 # Pe system.physmem.perBankRdBursts::11 16 # Per bank write bursts system.physmem.perBankRdBursts::12 2 # Per bank write bursts system.physmem.perBankRdBursts::13 19 # Per bank write bursts -system.physmem.perBankRdBursts::14 6 # Per bank write bursts +system.physmem.perBankRdBursts::14 7 # Per bank write bursts system.physmem.perBankRdBursts::15 17 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21151500 # Total gap between requests +system.physmem.totGap 21259500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 416 # Read request sizes (log2) +system.physmem.readPktSize::6 417 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -188,317 +188,317 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 97 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 250.721649 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 162.086023 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 265.276929 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 37 38.14% 38.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 25 25.77% 63.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 18 18.56% 82.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3 3.09% 85.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 248.742268 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 161.877699 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 262.561948 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 36 37.11% 37.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 27 27.84% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 16 16.49% 81.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4 4.12% 85.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 2 2.06% 87.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 2.06% 89.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 4.12% 93.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4 4.12% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 2.06% 93.81% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 1 1.03% 94.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 5.15% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 97 # Bytes accessed per row activation -system.physmem.totQLat 4187000 # Total ticks spent queuing -system.physmem.totMemAccLat 11987000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2080000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10064.90 # Average queueing delay per DRAM burst +system.physmem.totQLat 5040250 # Total ticks spent queuing +system.physmem.totMemAccLat 12859000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12086.93 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28814.90 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1251.51 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30836.93 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1248.12 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1251.51 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1248.12 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.78 # Data bus utilization in percentage -system.physmem.busUtilRead 9.78 # Data bus utilization in percentage for reads +system.physmem.busUtil 9.75 # Data bus utilization in percentage +system.physmem.busUtilRead 9.75 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.63 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.67 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 309 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.28 # Row buffer hit rate for reads +system.physmem.readRowHitRate 74.10 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 50844.95 # Average gap between requests -system.physmem.pageHitRate 74.28 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 181440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 99000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 920400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 50982.01 # Average gap between requests +system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 173880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 94875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 912600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 13042875 # Total energy per rank (pJ) -system.physmem_0.averagePower 823.803884 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states +system.physmem_0.totalEnergy 13023390 # Total energy per rank (pJ) +system.physmem_0.averagePower 822.573188 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 13750 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 415800 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 226875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1521000 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 1497600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10696905 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 116250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13993950 # Total energy per rank (pJ) -system.physmem_1.averagePower 883.874941 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 262750 # Time in different power states +system.physmem_1.actBackEnergy 10696050 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 117000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13970445 # Total energy per rank (pJ) +system.physmem_1.averagePower 882.390336 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 103000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15224250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15223250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 3510 # Number of BP lookups -system.cpu.branchPred.condPredicted 3510 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 564 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2934 # Number of BTB lookups +system.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 3511 # Number of BP lookups +system.cpu.branchPred.condPredicted 3511 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 567 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2933 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 413 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 93 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2934 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 493 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2441 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 404 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 414 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 94 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 2933 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 496 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2437 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 406 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 21273500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 42548 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 21382500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 42766 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 11447 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 15916 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3510 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 906 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9652 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1329 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 11494 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15919 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3511 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 910 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9718 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1335 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 93 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1405 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1414 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 15 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 2036 # Number of cache lines fetched +system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 2042 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 273 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 23302 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.230495 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.752458 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 23431 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.223593 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.745730 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19034 81.68% 81.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 165 0.71% 82.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 157 0.67% 83.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 234 1.00% 84.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 217 0.93% 85.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 212 0.91% 85.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 264 1.13% 87.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 172 0.74% 87.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2847 12.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19161 81.78% 81.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 166 0.71% 82.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 156 0.67% 83.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 235 1.00% 84.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 218 0.93% 85.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 215 0.92% 86.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 266 1.14% 87.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 168 0.72% 87.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2846 12.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 23302 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.082495 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.374072 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11533 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7244 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3404 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 457 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 664 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 26617 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 664 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 11798 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1942 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1135 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3557 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4206 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 25098 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full +system.cpu.fetch.rateDist::total 23431 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.082098 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.372235 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11586 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7313 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3407 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 458 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 667 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 26631 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 667 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 11849 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2059 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1032 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3561 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4263 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 25112 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 80 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 4073 # Number of times rename has blocked due to SQ full +system.cpu.rename.SQFullEvents 4127 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 28145 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 61205 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 35038 # Number of integer rename lookups +system.cpu.rename.RenameLookups 61260 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 35084 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 17082 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1412 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2736 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1550 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads. +system.cpu.rename.serializingInsts 24 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 1417 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2745 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1552 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21864 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 18142 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 143 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12140 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16726 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 23302 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.778560 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.752623 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 21890 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 18162 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 138 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12165 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16733 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 23431 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.775127 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.748484 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 18136 77.83% 77.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1211 5.20% 83.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 861 3.69% 86.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 568 2.44% 89.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 833 3.57% 92.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 596 2.56% 95.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 620 2.66% 97.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 343 1.47% 99.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 134 0.58% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 18255 77.91% 77.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1208 5.16% 83.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 874 3.73% 86.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 566 2.42% 89.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 836 3.57% 92.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 600 2.56% 95.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 613 2.62% 97.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 346 1.48% 99.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 133 0.57% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 23302 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 23431 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 211 76.17% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 50 18.05% 94.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 16 5.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 213 76.07% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 51 18.21% 94.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 16 5.71% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14465 79.73% 79.74% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.03% 79.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7 0.04% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2325 12.82% 92.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1337 7.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14483 79.74% 79.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6 0.03% 79.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.04% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2327 12.81% 92.64% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1337 7.36% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 18142 # Type of FU issued -system.cpu.iq.rate 0.426389 # Inst issue rate -system.cpu.iq.fu_busy_cnt 277 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015268 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 59998 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 34032 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16436 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 18162 # Type of FU issued +system.cpu.iq.rate 0.424683 # Inst issue rate +system.cpu.iq.fu_busy_cnt 280 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015417 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 60165 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 34082 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16453 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18413 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 18436 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 190 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 200 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1683 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1692 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 615 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 617 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 664 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1478 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 139 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21887 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 667 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1486 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 141 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 21912 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 9 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2736 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1550 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispLoadInsts 2745 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1552 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 138 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 140 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 119 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 682 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 801 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 17060 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2081 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1082 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 120 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 685 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 805 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 17078 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2088 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1084 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3326 # number of memory reference insts executed -system.cpu.iew.exec_branches 1722 # Number of branches executed +system.cpu.iew.exec_refs 3333 # number of memory reference insts executed +system.cpu.iew.exec_branches 1727 # Number of branches executed system.cpu.iew.exec_stores 1245 # Number of stores executed -system.cpu.iew.exec_rate 0.400959 # Inst execution rate -system.cpu.iew.wb_sent 16760 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16440 # cumulative count of insts written-back -system.cpu.iew.wb_producers 11045 # num instructions producing a value -system.cpu.iew.wb_consumers 17238 # num instructions consuming a value -system.cpu.iew.wb_rate 0.386387 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.640736 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 12139 # The number of squashed insts skipped by commit +system.cpu.iew.exec_rate 0.399336 # Inst execution rate +system.cpu.iew.wb_sent 16776 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16457 # cumulative count of insts written-back +system.cpu.iew.wb_producers 11050 # num instructions producing a value +system.cpu.iew.wb_consumers 17247 # num instructions consuming a value +system.cpu.iew.wb_rate 0.384815 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.640691 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 12164 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 652 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 21245 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.458790 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.350767 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 655 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 21365 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.456213 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.347578 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17995 84.70% 84.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 991 4.66% 89.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 576 2.71% 92.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 726 3.42% 95.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 383 1.80% 97.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 128 0.60% 97.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 121 0.57% 98.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 72 0.34% 98.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 253 1.19% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 18118 84.80% 84.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 989 4.63% 89.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 572 2.68% 92.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 729 3.41% 95.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 380 1.78% 97.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 132 0.62% 97.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 120 0.56% 98.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 73 0.34% 98.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 252 1.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 21245 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 21365 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -544,101 +544,101 @@ system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 9747 # Class of committed instruction -system.cpu.commit.bw_lim_events 253 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 42878 # The number of ROB reads -system.cpu.rob.rob_writes 45859 # The number of ROB writes -system.cpu.timesIdled 160 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19246 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 252 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 43024 # The number of ROB reads +system.cpu.rob.rob_writes 45919 # The number of ROB writes +system.cpu.timesIdled 159 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19335 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.908550 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.908550 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126445 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126445 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 21687 # number of integer regfile reads -system.cpu.int_regfile_writes 13280 # number of integer regfile writes +system.cpu.cpi 7.949071 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.949071 # CPI: Total CPI of All Threads +system.cpu.ipc 0.125801 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.125801 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 21733 # number of integer regfile reads +system.cpu.int_regfile_writes 13291 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.cc_regfile_reads 8296 # number of cc regfile reads +system.cpu.cc_regfile_reads 8307 # number of cc regfile reads system.cpu.cc_regfile_writes 5092 # number of cc regfile writes -system.cpu.misc_regfile_reads 7660 # number of misc regfile reads +system.cpu.misc_regfile_reads 7667 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.534494 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2583 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 81.328051 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2579 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 139 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 18.582734 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 18.553957 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.534494 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019906 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019906 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 81.328051 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.019855 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.019855 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 139 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.033936 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5685 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5685 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1723 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1723 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5679 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5679 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 1719 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1719 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 860 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 860 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2583 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2583 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2583 # number of overall hits -system.cpu.dcache.overall_hits::total 2583 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2579 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2579 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2579 # number of overall hits +system.cpu.dcache.overall_hits::total 2579 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 116 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 116 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 75 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 75 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 190 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 190 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 190 # number of overall misses -system.cpu.dcache.overall_misses::total 190 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9038500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9038500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6225500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6225500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15264000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15264000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15264000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15264000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1838 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1838 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 191 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 191 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 191 # number of overall misses +system.cpu.dcache.overall_misses::total 191 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9465500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9465500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6317000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6317000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15782500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15782500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15782500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15782500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1835 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1835 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2773 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2773 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2773 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2773 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062568 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.062568 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2770 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2770 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2770 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2770 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.063215 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.063215 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080214 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.080214 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.068518 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.068518 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.068518 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.068518 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78595.652174 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 78595.652174 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83006.666667 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 83006.666667 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80336.842105 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80336.842105 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80336.842105 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80336.842105 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 122 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.068953 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.068953 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.068953 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.068953 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81599.137931 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 81599.137931 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84226.666667 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 84226.666667 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 82630.890052 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 82630.890052 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 82630.890052 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 82630.890052 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 124 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 41.333333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 51 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 51 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 51 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 51 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 52 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 52 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 52 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 52 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 75 # number of WriteReq MSHR misses @@ -647,88 +647,88 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 139 system.cpu.dcache.demand_mshr_misses::total 139 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 139 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 139 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5459500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5459500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6150500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6150500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11610000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11610000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11610000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11610000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034820 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034820 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5739000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5739000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6242000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6242000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11981000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11981000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11981000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11981000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034877 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034877 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.080214 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.080214 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.050126 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.050126 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.050126 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.050126 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85304.687500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85304.687500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82006.666667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82006.666667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83525.179856 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 83525.179856 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83525.179856 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 83525.179856 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.050181 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.050181 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.050181 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.050181 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89671.875000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89671.875000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83226.666667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83226.666667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86194.244604 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 86194.244604 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86194.244604 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 86194.244604 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 130.801873 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1651 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 278 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.938849 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 130.610950 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1656 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.935484 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 130.801873 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063868 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063868 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 278 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 130.610950 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.063775 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063775 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 148 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.135742 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4350 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4350 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1651 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1651 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1651 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1651 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1651 # number of overall hits -system.cpu.icache.overall_hits::total 1651 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 385 # 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number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2036 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2036 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2036 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2036 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2036 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.189096 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.189096 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.189096 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.189096 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.189096 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.189096 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74068.831169 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74068.831169 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74068.831169 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74068.831169 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74068.831169 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74068.831169 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 142 # number of cycles access was blocked +system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4363 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4363 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1656 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1656 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1656 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1656 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1656 # number of overall hits +system.cpu.icache.overall_hits::total 1656 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 386 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 386 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 386 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 386 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 386 # number of overall misses +system.cpu.icache.overall_misses::total 386 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 29282500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 29282500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 29282500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 29282500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 29282500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 29282500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2042 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2042 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2042 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2042 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2042 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2042 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.189030 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.189030 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.189030 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.189030 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.189030 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.189030 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75861.398964 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75861.398964 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75861.398964 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75861.398964 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75861.398964 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75861.398964 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 121 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 47.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 40.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.ReadReq_mshr_hits::cpu.inst 107 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits @@ -736,49 +736,49 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 107 system.cpu.icache.demand_mshr_hits::total 107 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 107 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 107 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 278 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 278 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21868500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21868500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21868500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21868500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21868500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21868500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136542 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136542 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136542 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.136542 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136542 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.136542 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78663.669065 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78663.669065 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78663.669065 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 78663.669065 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78663.669065 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 78663.669065 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22839500 # 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mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.136631 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81862.007168 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81862.007168 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81862.007168 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 81862.007168 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81862.007168 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 81862.007168 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 163.058861 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 212.046379 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 341 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002933 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 417 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002398 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.841735 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32.217126 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003993 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000983 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004976 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 341 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010406 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3752 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3752 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.650071 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 81.396308 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003987 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002484 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006471 # 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number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 279 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 64 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 278 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 139 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 417 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 278 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 139 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 417 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996403 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996403 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996416 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996403 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997602 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996403 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.997608 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997602 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77398.916968 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77398.916968 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83789.062500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83789.062500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77398.916968 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82014.388489 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78941.105769 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77398.916968 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82014.388489 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78941.105769 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997608 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81720 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81720 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80607.913669 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80607.913669 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88156.250000 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88156.250000 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80607.913669 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84683.453237 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81966.426859 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80607.913669 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84683.453237 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81966.426859 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -853,115 +853,121 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 75 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 75 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 277 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 277 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 64 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 64 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 139 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 417 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 139 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5287500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5287500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18669500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18669500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4722500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4722500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18669500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10010000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28679500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18669500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10010000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28679500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5379000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5379000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19629000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19629000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5002000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5002000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19629000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10381000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30010000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19629000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10381000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30010000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996403 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996416 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997602 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997602 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67398.916968 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67398.916968 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73789.062500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73789.062500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67398.916968 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72014.388489 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68941.105769 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67398.916968 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72014.388489 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68941.105769 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 417 # Total number of requests made to the snoop filter. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71720 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71720 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70607.913669 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70607.913669 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78156.250000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78156.250000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70607.913669 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74683.453237 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71966.426859 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70607.913669 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74683.453237 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71966.426859 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 342 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 343 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 75 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 75 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 278 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 279 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 64 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 556 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 278 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 834 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 417 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002398 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.048970 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002392 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.048912 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 416 99.76% 99.76% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 417 99.76% 99.76% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 1 0.24% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 417 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 208500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 417000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 208500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 341 # Transaction distribution +system.membus.snoop_filter.tot_requests 417 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 342 # Transaction distribution system.membus.trans_dist::ReadExReq 75 # Transaction distribution system.membus.trans_dist::ReadExResp 75 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 341 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 832 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 342 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 834 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 834 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 834 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 416 # Request fanout histogram +system.membus.snoop_fanout::samples 417 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 416 # Request fanout histogram -system.membus.reqLayer0.occupancy 502000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 417 # Request fanout histogram +system.membus.reqLayer0.occupancy 503500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 2222250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2228500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 10.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index 563e9e0f5..f34005614 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000006 # Nu sim_ticks 5615000 # Number of ticks simulated final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 290053 # Simulator instruction rate (inst/s) -host_op_rate 524918 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 302085986 # Simulator tick rate (ticks/s) -host_mem_usage 255208 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 127315 # Simulator instruction rate (inst/s) +host_op_rate 230565 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 132772406 # Simulator tick rate (ticks/s) +host_mem_usage 258816 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -104,6 +104,12 @@ system.cpu.op_class::MemWrite 935 9.59% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 9748 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7917 # Transaction distribution system.membus.trans_dist::ReadResp 7917 # Transaction distribution @@ -122,14 +128,14 @@ system.membus.pkt_size::total 69090 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 8852 # Request fanout histogram -system.membus.snoop_fanout::mean 0.775418 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.417330 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1988 22.46% 22.46% # Request fanout histogram -system.membus.snoop_fanout::1 6864 77.54% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 8852 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 8852 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 9047321d1..afc430970 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 30886500 # Number of ticks simulated -final_tick 30886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 31247500 # Number of ticks simulated +final_tick 31247500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 211795 # Simulator instruction rate (inst/s) -host_op_rate 383429 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1214135841 # Simulator tick rate (ticks/s) -host_mem_usage 263924 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 85405 # Simulator instruction rate (inst/s) +host_op_rate 154687 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 495766938 # Simulator tick rate (ticks/s) +host_mem_usage 269328 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory system.physmem.bytes_read::total 23104 # Number of bytes read from this memory @@ -22,23 +22,23 @@ system.physmem.bytes_inst_read::total 14528 # Nu system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 361 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 470367313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 277661762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 748029074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 470367313 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 470367313 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 470367313 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 277661762 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 748029074 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 464933195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 274453956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 739387151 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 464933195 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 464933195 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 464933195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 274453956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 739387151 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 30886500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 61773 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 31247500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 62495 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5381 # Number of instructions committed @@ -59,7 +59,7 @@ system.cpu.num_mem_refs 1988 # nu system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 61772.998000 # Number of busy cycles +system.cpu.num_busy_cycles 62494.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched @@ -98,23 +98,23 @@ system.cpu.op_class::MemWrite 935 9.59% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 9748 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 80.558239 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 80.527852 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 80.558239 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019668 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019668 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 80.527852 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.019660 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.019660 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits @@ -131,14 +131,14 @@ system.cpu.dcache.demand_misses::cpu.data 134 # n system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses system.cpu.dcache.overall_misses::total 134 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3410000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3410000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4898000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4898000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8308000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8308000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8308000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8308000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3465000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3465000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4977000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4977000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8442000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8442000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8442000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8442000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) @@ -155,14 +155,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -177,14 +177,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 134 system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3355000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3355000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4819000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4819000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8174000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8174000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8174000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8174000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3410000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3410000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4898000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4898000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8308000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8308000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8308000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8308000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses @@ -193,31 +193,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 105.267613 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 105.231814 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 105.267613 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.051400 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.051400 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 105.231814 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.051383 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.051383 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 13956 # Number of tag accesses system.cpu.icache.tags.data_accesses 13956 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 6636 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6636 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6636 # number of demand (read+write) hits @@ -230,12 +230,12 @@ system.cpu.icache.demand_misses::cpu.inst 228 # n system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses system.cpu.icache.overall_misses::total 228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14088500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14088500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14088500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14088500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14088500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14088500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14315500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14315500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14315500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14315500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14315500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14315500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses @@ -248,12 +248,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.033217 system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61791.666667 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61791.666667 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61791.666667 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61791.666667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61791.666667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61791.666667 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62787.280702 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62787.280702 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62787.280702 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62787.280702 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62787.280702 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62787.280702 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -266,43 +266,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 228 system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13860500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13860500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13860500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13860500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13860500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13860500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14087500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14087500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14087500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14087500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14087500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14087500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60791.666667 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60791.666667 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61787.280702 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61787.280702 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61787.280702 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61787.280702 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61787.280702 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61787.280702 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 133.672095 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 185.792229 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 361 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002770 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.256135 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.415959 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003212 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000867 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004079 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008606 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.219349 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 80.572880 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003211 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002459 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005670 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 361 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 247 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011017 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3257 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -321,18 +321,18 @@ system.cpu.l2cache.demand_misses::total 361 # nu system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 361 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4700500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4700500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13507000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 13507000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3272500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3272500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13507000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7973000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21480000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13507000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7973000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21480000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4779500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4779500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13734000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 13734000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3327500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3327500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 13734000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8107000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21841000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 13734000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8107000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21841000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 228 # number of ReadCleanReq accesses(hits+misses) @@ -357,18 +357,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.997238 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59502.202643 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59502.202643 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59502.202643 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59501.385042 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59502.202643 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59501.385042 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.202643 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.202643 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.202643 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60501.385042 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.202643 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60501.385042 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -387,18 +387,18 @@ system.cpu.l2cache.demand_mshr_misses::total 361 system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3910500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3910500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11237000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11237000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2722500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2722500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11237000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6633000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17870000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11237000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6633000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17870000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3989500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3989500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11464000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11464000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2777500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2777500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11464000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6767000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18231000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11464000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6767000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18231000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadCleanReq accesses @@ -411,25 +411,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49502.202643 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49502.202643 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.202643 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.202643 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.202643 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.385042 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.202643 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.385042 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution @@ -459,8 +459,14 @@ system.cpu.toL2Bus.reqLayer0.utilization 0.6 # La system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 361 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 282 # Transaction distribution system.membus.trans_dist::ReadExReq 79 # Transaction distribution system.membus.trans_dist::ReadExResp 79 # Transaction distribution |