diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-06-10 06:46:20 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-06-10 06:46:20 -0500 |
| commit | 247e4e9ab41bafcfcbde725bb40e6a7b5628f1de (patch) | |
| tree | b4312f540772ef437b5b962cc1fff4bb54d90ce4 /tests/quick/se/00.hello/ref | |
| parent | d32ee94231251b8d07bb811142f6759f8655962b (diff) | |
| download | gem5-247e4e9ab41bafcfcbde725bb40e6a7b5628f1de.tar.xz | |
stats: updates due to changes to ruby
Ruby's controller statistics have been mostly moved to stats.txt now.
Plus stats.txt for solaris/t1000-simple-atomic and arm/20.parser are
also being updated.
Diffstat (limited to 'tests/quick/se/00.hello/ref')
25 files changed, 1100 insertions, 7243 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats index bdfda8e2d..0b9ca4b9f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -1,26 +1,24 @@ -Real time: Mar/06/2013 20:38:34 +Real time: Jun/08/2013 14:12:32 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.68 -Virtual_time_in_minutes: 0.0113333 -Virtual_time_in_hours: 0.000188889 -Virtual_time_in_days: 7.87037e-06 +Virtual_time_in_seconds: 0.6 +Virtual_time_in_minutes: 0.01 +Virtual_time_in_hours: 0.000166667 +Virtual_time_in_days: 6.94444e-06 Ruby_current_time: 138616 Ruby_start_time: 0 Ruby_cycles: 138616 -mbytes_resident: 55.9375 -mbytes_total: 148.203 -resident_ratio: 0.377491 - -ruby_cycles_executed: [ 138617 ] +mbytes_resident: 56.3281 +mbytes_total: 144.332 +resident_ratio: 0.390322 Busy Controller Counts: L1Cache-0:0 @@ -61,7 +59,6 @@ Request vs. RubySystem State Profile -------------------------------- -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- @@ -82,7 +79,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11604 +page_reclaims: 11627 page_faults: 0 swaps: 0 block_inputs: 0 @@ -160,458 +157,3 @@ links_utilized_percent_switch_3: 4.89085 outgoing_messages_switch_3_link_2_Response_Data: 277 19944 [ 0 277 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Response_Control: 1175 9400 [ 0 1175 0 0 0 0 0 0 0 0 ] base_latency: 1 - --- L1Cache --- - - Event Counts - -Load [1183 ] 1183 -Ifetch [6400 ] 6400 -Store [865 ] 865 -Inv [1041 ] 1041 -L1_Replacement [1354 ] 1354 -Fwd_GETX [0 ] 0 -Fwd_GETS [0 ] 0 -Fwd_GET_INSTR [0 ] 0 -Data [0 ] 0 -Data_Exclusive [583 ] 583 -DataS_fromL1 [0 ] 0 -Data_all_Acks [907 ] 907 -Ack [0 ] 0 -Ack_all [0 ] 0 -WB_Ack [436 ] 436 -PF_Load [0 ] 0 -PF_Ifetch [0 ] 0 -PF_Store [0 ] 0 - - - Transitions - -NP Load [525 ] 525 -NP Ifetch [646 ] 646 -NP Store [191 ] 191 -NP Inv [356 ] 356 -NP L1_Replacement [0 ] 0 -NP PF_Load [0 ] 0 -NP PF_Ifetch [0 ] 0 -NP PF_Store [0 ] 0 - -I Load [58 ] 58 -I Ifetch [45 ] 45 -I Store [25 ] 25 -I Inv [0 ] 0 -I L1_Replacement [556 ] 556 -I PF_Load [0 ] 0 -I PF_Ifetch [0 ] 0 -I PF_Store [0 ] 0 - -S Load [0 ] 0 -S Ifetch [5709 ] 5709 -S Store [0 ] 0 -S Inv [325 ] 325 -S L1_Replacement [362 ] 362 -S PF_Load [0 ] 0 -S PF_Store [0 ] 0 - -E Load [452 ] 452 -E Ifetch [0 ] 0 -E Store [71 ] 71 -E Inv [219 ] 219 -E L1_Replacement [291 ] 291 -E Fwd_GETX [0 ] 0 -E Fwd_GETS [0 ] 0 -E Fwd_GET_INSTR [0 ] 0 -E PF_Load [0 ] 0 -E PF_Store [0 ] 0 - -M Load [148 ] 148 -M Ifetch [0 ] 0 -M Store [578 ] 578 -M Inv [141 ] 141 -M L1_Replacement [145 ] 145 -M Fwd_GETX [0 ] 0 -M Fwd_GETS [0 ] 0 -M Fwd_GET_INSTR [0 ] 0 -M PF_Load [0 ] 0 -M PF_Store [0 ] 0 - -IS Load [0 ] 0 -IS Ifetch [0 ] 0 -IS Store [0 ] 0 -IS Inv [0 ] 0 -IS L1_Replacement [0 ] 0 -IS Data_Exclusive [583 ] 583 -IS DataS_fromL1 [0 ] 0 -IS Data_all_Acks [691 ] 691 -IS PF_Load [0 ] 0 -IS PF_Store [0 ] 0 - -IM Load [0 ] 0 -IM Ifetch [0 ] 0 -IM Store [0 ] 0 -IM Inv [0 ] 0 -IM L1_Replacement [0 ] 0 -IM Data [0 ] 0 -IM Data_all_Acks [216 ] 216 -IM Ack [0 ] 0 -IM PF_Load [0 ] 0 -IM PF_Store [0 ] 0 - -SM Load [0 ] 0 -SM Ifetch [0 ] 0 -SM Store [0 ] 0 -SM Inv [0 ] 0 -SM L1_Replacement [0 ] 0 -SM Ack [0 ] 0 -SM Ack_all [0 ] 0 -SM PF_Load [0 ] 0 -SM PF_Store [0 ] 0 - -IS_I Load [0 ] 0 -IS_I Ifetch [0 ] 0 -IS_I Store [0 ] 0 -IS_I Inv [0 ] 0 -IS_I L1_Replacement [0 ] 0 -IS_I Data_Exclusive [0 ] 0 -IS_I DataS_fromL1 [0 ] 0 -IS_I Data_all_Acks [0 ] 0 -IS_I PF_Load [0 ] 0 -IS_I PF_Store [0 ] 0 - -M_I Load [0 ] 0 -M_I Ifetch [0 ] 0 -M_I Store [0 ] 0 -M_I Inv [0 ] 0 -M_I L1_Replacement [0 ] 0 -M_I Fwd_GETX [0 ] 0 -M_I Fwd_GETS [0 ] 0 -M_I Fwd_GET_INSTR [0 ] 0 -M_I WB_Ack [436 ] 436 -M_I PF_Load [0 ] 0 -M_I PF_Store [0 ] 0 - -SINK_WB_ACK Load [0 ] 0 -SINK_WB_ACK Ifetch [0 ] 0 -SINK_WB_ACK Store [0 ] 0 -SINK_WB_ACK Inv [0 ] 0 -SINK_WB_ACK L1_Replacement [0 ] 0 -SINK_WB_ACK WB_Ack [0 ] 0 -SINK_WB_ACK PF_Load [0 ] 0 -SINK_WB_ACK PF_Store [0 ] 0 - -PF_IS Load [0 ] 0 -PF_IS Ifetch [0 ] 0 -PF_IS Store [0 ] 0 -PF_IS Inv [0 ] 0 -PF_IS L1_Replacement [0 ] 0 -PF_IS Data_Exclusive [0 ] 0 -PF_IS DataS_fromL1 [0 ] 0 -PF_IS Data_all_Acks [0 ] 0 -PF_IS PF_Load [0 ] 0 -PF_IS PF_Store [0 ] 0 - -PF_IM Load [0 ] 0 -PF_IM Ifetch [0 ] 0 -PF_IM Store [0 ] 0 -PF_IM Inv [0 ] 0 -PF_IM L1_Replacement [0 ] 0 -PF_IM Data [0 ] 0 -PF_IM Data_all_Acks [0 ] 0 -PF_IM Ack [0 ] 0 -PF_IM PF_Load [0 ] 0 -PF_IM PF_Store [0 ] 0 - -PF_SM Load [0 ] 0 -PF_SM Ifetch [0 ] 0 -PF_SM Store [0 ] 0 -PF_SM Inv [0 ] 0 -PF_SM L1_Replacement [0 ] 0 -PF_SM Ack [0 ] 0 -PF_SM Ack_all [0 ] 0 - -PF_IS_I Load [0 ] 0 -PF_IS_I Store [0 ] 0 -PF_IS_I Inv [0 ] 0 -PF_IS_I L1_Replacement [0 ] 0 -PF_IS_I Data_Exclusive [0 ] 0 -PF_IS_I DataS_fromL1 [0 ] 0 -PF_IS_I Data_all_Acks [0 ] 0 - - --- L2Cache --- - - Event Counts - -L1_GET_INSTR [691 ] 691 -L1_GETS [583 ] 583 -L1_GETX [216 ] 216 -L1_UPGRADE [0 ] 0 -L1_PUTX [436 ] 436 -L1_PUTX_old [0 ] 0 -Fwd_L1_GETX [0 ] 0 -Fwd_L1_GETS [0 ] 0 -Fwd_L1_GET_INSTR [0 ] 0 -L2_Replacement [142 ] 142 -L2_Replacement_clean [1310 ] 1310 -Mem_Data [1460 ] 1460 -Mem_Ack [1452 ] 1452 -WB_Data [141 ] 141 -WB_Data_clean [0 ] 0 -Ack [0 ] 0 -Ack_all [900 ] 900 -Unblock [0 ] 0 -Unblock_Cancel [0 ] 0 -Exclusive_Unblock [799 ] 799 -MEM_Inv [0 ] 0 - - - Transitions - -NP L1_GET_INSTR [686 ] 686 -NP L1_GETS [570 ] 570 -NP L1_GETX [204 ] 204 -NP L1_PUTX [0 ] 0 -NP L1_PUTX_old [0 ] 0 - -SS L1_GET_INSTR [5 ] 5 -SS L1_GETS [0 ] 0 -SS L1_GETX [0 ] 0 -SS L1_UPGRADE [0 ] 0 -SS L1_PUTX [0 ] 0 -SS L1_PUTX_old [0 ] 0 -SS L2_Replacement [0 ] 0 -SS L2_Replacement_clean [681 ] 681 -SS MEM_Inv [0 ] 0 - -M L1_GET_INSTR [0 ] 0 -M L1_GETS [13 ] 13 -M L1_GETX [12 ] 12 -M L1_PUTX [0 ] 0 -M L1_PUTX_old [0 ] 0 -M L2_Replacement [134 ] 134 -M L2_Replacement_clean [277 ] 277 -M MEM_Inv [0 ] 0 - -MT L1_GET_INSTR [0 ] 0 -MT L1_GETS [0 ] 0 -MT L1_GETX [0 ] 0 -MT L1_PUTX [436 ] 436 -MT L1_PUTX_old [0 ] 0 -MT L2_Replacement [8 ] 8 -MT L2_Replacement_clean [352 ] 352 -MT MEM_Inv [0 ] 0 - -M_I L1_GET_INSTR [0 ] 0 -M_I L1_GETS [0 ] 0 -M_I L1_GETX [0 ] 0 -M_I L1_UPGRADE [0 ] 0 -M_I L1_PUTX [0 ] 0 -M_I L1_PUTX_old [0 ] 0 -M_I Mem_Ack [1452 ] 1452 -M_I MEM_Inv [0 ] 0 - -MT_I L1_GET_INSTR [0 ] 0 -MT_I L1_GETS [0 ] 0 -MT_I L1_GETX [0 ] 0 -MT_I L1_UPGRADE [0 ] 0 -MT_I L1_PUTX [0 ] 0 -MT_I L1_PUTX_old [0 ] 0 -MT_I WB_Data [6 ] 6 -MT_I WB_Data_clean [0 ] 0 -MT_I Ack_all [2 ] 2 -MT_I MEM_Inv [0 ] 0 - -MCT_I L1_GET_INSTR [0 ] 0 -MCT_I L1_GETS [0 ] 0 -MCT_I L1_GETX [0 ] 0 -MCT_I L1_UPGRADE [0 ] 0 -MCT_I L1_PUTX [0 ] 0 -MCT_I L1_PUTX_old [0 ] 0 -MCT_I WB_Data [135 ] 135 -MCT_I WB_Data_clean [0 ] 0 -MCT_I Ack_all [217 ] 217 - -I_I L1_GET_INSTR [0 ] 0 -I_I L1_GETS [0 ] 0 -I_I L1_GETX [0 ] 0 -I_I L1_UPGRADE [0 ] 0 -I_I L1_PUTX [0 ] 0 -I_I L1_PUTX_old [0 ] 0 -I_I Ack [0 ] 0 -I_I Ack_all [681 ] 681 - -S_I L1_GET_INSTR [0 ] 0 -S_I L1_GETS [0 ] 0 -S_I L1_GETX [0 ] 0 -S_I L1_UPGRADE [0 ] 0 -S_I L1_PUTX [0 ] 0 -S_I L1_PUTX_old [0 ] 0 -S_I Ack [0 ] 0 -S_I Ack_all [0 ] 0 -S_I MEM_Inv [0 ] 0 - -ISS L1_GET_INSTR [0 ] 0 -ISS L1_GETS [0 ] 0 -ISS L1_GETX [0 ] 0 -ISS L1_PUTX [0 ] 0 -ISS L1_PUTX_old [0 ] 0 -ISS L2_Replacement [0 ] 0 -ISS L2_Replacement_clean [0 ] 0 -ISS Mem_Data [570 ] 570 -ISS MEM_Inv [0 ] 0 - -IS L1_GET_INSTR [0 ] 0 -IS L1_GETS [0 ] 0 -IS L1_GETX [0 ] 0 -IS L1_PUTX [0 ] 0 -IS L1_PUTX_old [0 ] 0 -IS L2_Replacement [0 ] 0 -IS L2_Replacement_clean [0 ] 0 -IS Mem_Data [686 ] 686 -IS MEM_Inv [0 ] 0 - -IM L1_GET_INSTR [0 ] 0 -IM L1_GETS [0 ] 0 -IM L1_GETX [0 ] 0 -IM L1_PUTX [0 ] 0 -IM L1_PUTX_old [0 ] 0 -IM L2_Replacement [0 ] 0 -IM L2_Replacement_clean [0 ] 0 -IM Mem_Data [204 ] 204 -IM MEM_Inv [0 ] 0 - -SS_MB L1_GET_INSTR [0 ] 0 -SS_MB L1_GETS [0 ] 0 -SS_MB L1_GETX [0 ] 0 -SS_MB L1_UPGRADE [0 ] 0 -SS_MB L1_PUTX [0 ] 0 -SS_MB L1_PUTX_old [0 ] 0 -SS_MB L2_Replacement [0 ] 0 -SS_MB L2_Replacement_clean [0 ] 0 -SS_MB Unblock_Cancel [0 ] 0 -SS_MB Exclusive_Unblock [0 ] 0 -SS_MB MEM_Inv [0 ] 0 - -MT_MB L1_GET_INSTR [0 ] 0 -MT_MB L1_GETS [0 ] 0 -MT_MB L1_GETX [0 ] 0 -MT_MB L1_UPGRADE [0 ] 0 -MT_MB L1_PUTX [0 ] 0 -MT_MB L1_PUTX_old [0 ] 0 -MT_MB L2_Replacement [0 ] 0 -MT_MB L2_Replacement_clean [0 ] 0 -MT_MB Unblock_Cancel [0 ] 0 -MT_MB Exclusive_Unblock [799 ] 799 -MT_MB MEM_Inv [0 ] 0 - -MT_IIB L1_GET_INSTR [0 ] 0 -MT_IIB L1_GETS [0 ] 0 -MT_IIB L1_GETX [0 ] 0 -MT_IIB L1_UPGRADE [0 ] 0 -MT_IIB L1_PUTX [0 ] 0 -MT_IIB L1_PUTX_old [0 ] 0 -MT_IIB L2_Replacement [0 ] 0 -MT_IIB L2_Replacement_clean [0 ] 0 -MT_IIB WB_Data [0 ] 0 -MT_IIB WB_Data_clean [0 ] 0 -MT_IIB Unblock [0 ] 0 -MT_IIB MEM_Inv [0 ] 0 - -MT_IB L1_GET_INSTR [0 ] 0 -MT_IB L1_GETS [0 ] 0 -MT_IB L1_GETX [0 ] 0 -MT_IB L1_UPGRADE [0 ] 0 -MT_IB L1_PUTX [0 ] 0 -MT_IB L1_PUTX_old [0 ] 0 -MT_IB L2_Replacement [0 ] 0 -MT_IB L2_Replacement_clean [0 ] 0 -MT_IB WB_Data [0 ] 0 -MT_IB WB_Data_clean [0 ] 0 -MT_IB Unblock_Cancel [0 ] 0 -MT_IB MEM_Inv [0 ] 0 - -MT_SB L1_GET_INSTR [0 ] 0 -MT_SB L1_GETS [0 ] 0 -MT_SB L1_GETX [0 ] 0 -MT_SB L1_UPGRADE [0 ] 0 -MT_SB L1_PUTX [0 ] 0 -MT_SB L1_PUTX_old [0 ] 0 -MT_SB L2_Replacement [0 ] 0 -MT_SB L2_Replacement_clean [0 ] 0 -MT_SB Unblock [0 ] 0 -MT_SB MEM_Inv [0 ] 0 - -Memory controller: system.ruby.dir_cntrl0.memBuffer: - memory_total_requests: 1737 - memory_reads: 1460 - memory_writes: 277 - memory_refreshes: 963 - memory_total_request_delays: 341 - memory_delays_per_request: 0.196315 - memory_delays_in_input_queue: 0 - memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 341 - memory_stalls_for_bank_busy: 166 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 24 - memory_stalls_for_bus: 147 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 4 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 92 21 45 54 57 174 48 18 19 22 35 37 56 59 44 36 41 24 22 28 32 48 122 36 32 25 35 96 114 185 19 61 - - --- Directory --- - - Event Counts - -Fetch [1460 ] 1460 -Data [277 ] 277 -Memory_Data [1460 ] 1460 -Memory_Ack [277 ] 277 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -CleanReplacement [1175 ] 1175 - - - Transitions - -I Fetch [1460 ] 1460 -I DMA_READ [0 ] 0 -I DMA_WRITE [0 ] 0 - -ID Fetch [0 ] 0 -ID Data [0 ] 0 -ID Memory_Data [0 ] 0 -ID DMA_READ [0 ] 0 -ID DMA_WRITE [0 ] 0 - -ID_W Fetch [0 ] 0 -ID_W Data [0 ] 0 -ID_W Memory_Ack [0 ] 0 -ID_W DMA_READ [0 ] 0 -ID_W DMA_WRITE [0 ] 0 - -M Data [277 ] 277 -M DMA_READ [0 ] 0 -M DMA_WRITE [0 ] 0 -M CleanReplacement [1175 ] 1175 - -IM Fetch [0 ] 0 -IM Data [0 ] 0 -IM Memory_Data [1460 ] 1460 -IM DMA_READ [0 ] 0 -IM DMA_WRITE [0 ] 0 - -MI Fetch [0 ] 0 -MI Data [0 ] 0 -MI Memory_Ack [277 ] 277 -MI DMA_READ [0 ] 0 -MI DMA_WRITE [0 ] 0 - -M_DRD Data [0 ] 0 -M_DRD DMA_READ [0 ] 0 -M_DRD DMA_WRITE [0 ] 0 - -M_DRDI Fetch [0 ] 0 -M_DRDI Data [0 ] 0 -M_DRDI Memory_Ack [0 ] 0 -M_DRDI DMA_READ [0 ] 0 -M_DRDI DMA_WRITE [0 ] 0 - -M_DWR Data [0 ] 0 -M_DWR DMA_READ [0 ] 0 -M_DWR DMA_WRITE [0 ] 0 - -M_DWRI Fetch [0 ] 0 -M_DWRI Data [0 ] 0 -M_DWRI Memory_Ack [0 ] 0 -M_DWRI DMA_READ [0 ] 0 -M_DWRI DMA_WRITE [0 ] 0 - diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt index ffef61c0e..53a8460e0 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000139 # Nu sim_ticks 138616 # Number of ticks simulated final_tick 138616 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 20262 # Simulator instruction rate (inst/s) -host_op_rate 20260 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 439475 # Simulator tick rate (ticks/s) -host_mem_usage 154624 # Number of bytes of host memory used -host_seconds 0.32 # Real time elapsed on the host +host_inst_rate 33803 # Simulator instruction rate (inst/s) +host_op_rate 33800 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 733103 # Simulator tick rate (ticks/s) +host_mem_usage 147800 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits @@ -29,6 +29,20 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.dir_cntrl0.memBuffer.memReq 1737 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 1460 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 277 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 963 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 341 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 341 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.196315 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 166 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 147 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 4 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 24 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 92 5.30% 5.30% | 21 1.21% 6.51% | 45 2.59% 9.10% | 54 3.11% 12.20% | 57 3.28% 15.49% | 174 10.02% 25.50% | 48 2.76% 28.27% | 18 1.04% 29.30% | 19 1.09% 30.40% | 22 1.27% 31.66% | 35 2.01% 33.68% | 37 2.13% 35.81% | 56 3.22% 39.03% | 59 3.40% 42.43% | 44 2.53% 44.96% | 36 2.07% 47.04% | 41 2.36% 49.40% | 24 1.38% 50.78% | 22 1.27% 52.04% | 28 1.61% 53.66% | 32 1.84% 55.50% | 48 2.76% 58.26% | 122 7.02% 65.28% | 36 2.07% 67.36% | 32 1.84% 69.20% | 25 1.44% 70.64% | 35 2.01% 72.65% | 96 5.53% 78.18% | 114 6.56% 84.74% | 185 10.65% 95.39% | 19 1.09% 96.49% | 61 3.51% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1737 # Number of accesses per bank + system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -84,5 +98,79 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 138616 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles +system.ruby.l2_cntrl0.L1_GET_INSTR 691 0.00% 0.00% +system.ruby.l2_cntrl0.L1_GETS 583 0.00% 0.00% +system.ruby.l2_cntrl0.L1_GETX 216 0.00% 0.00% +system.ruby.l2_cntrl0.L1_PUTX 436 0.00% 0.00% +system.ruby.l2_cntrl0.L2_Replacement 142 0.00% 0.00% +system.ruby.l2_cntrl0.L2_Replacement_clean 1310 0.00% 0.00% +system.ruby.l2_cntrl0.Mem_Data 1460 0.00% 0.00% +system.ruby.l2_cntrl0.Mem_Ack 1452 0.00% 0.00% +system.ruby.l2_cntrl0.WB_Data 141 0.00% 0.00% +system.ruby.l2_cntrl0.Ack_all 900 0.00% 0.00% +system.ruby.l2_cntrl0.Exclusive_Unblock 799 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GET_INSTR 686 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETS 570 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETX 204 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_GET_INSTR 5 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L2_Replacement_clean 681 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETS 13 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETX 12 0.00% 0.00% +system.ruby.l2_cntrl0.M.L2_Replacement 134 0.00% 0.00% +system.ruby.l2_cntrl0.M.L2_Replacement_clean 277 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L1_PUTX 436 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L2_Replacement 8 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L2_Replacement_clean 352 0.00% 0.00% +system.ruby.l2_cntrl0.M_I.Mem_Ack 1452 0.00% 0.00% +system.ruby.l2_cntrl0.MT_I.WB_Data 6 0.00% 0.00% +system.ruby.l2_cntrl0.MT_I.Ack_all 2 0.00% 0.00% +system.ruby.l2_cntrl0.MCT_I.WB_Data 135 0.00% 0.00% +system.ruby.l2_cntrl0.MCT_I.Ack_all 217 0.00% 0.00% +system.ruby.l2_cntrl0.I_I.Ack_all 681 0.00% 0.00% +system.ruby.l2_cntrl0.ISS.Mem_Data 570 0.00% 0.00% +system.ruby.l2_cntrl0.IS.Mem_Data 686 0.00% 0.00% +system.ruby.l2_cntrl0.IM.Mem_Data 204 0.00% 0.00% +system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 799 0.00% 0.00% +system.ruby.l1_cntrl0.Load 1183 0.00% 0.00% +system.ruby.l1_cntrl0.Ifetch 6400 0.00% 0.00% +system.ruby.l1_cntrl0.Store 865 0.00% 0.00% +system.ruby.l1_cntrl0.Inv 1041 0.00% 0.00% +system.ruby.l1_cntrl0.L1_Replacement 1354 0.00% 0.00% +system.ruby.l1_cntrl0.Data_Exclusive 583 0.00% 0.00% +system.ruby.l1_cntrl0.Data_all_Acks 907 0.00% 0.00% +system.ruby.l1_cntrl0.WB_Ack 436 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Load 525 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Ifetch 646 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Store 191 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Inv 356 0.00% 0.00% +system.ruby.l1_cntrl0.I.Load 58 0.00% 0.00% +system.ruby.l1_cntrl0.I.Ifetch 45 0.00% 0.00% +system.ruby.l1_cntrl0.I.Store 25 0.00% 0.00% +system.ruby.l1_cntrl0.I.L1_Replacement 556 0.00% 0.00% +system.ruby.l1_cntrl0.S.Ifetch 5709 0.00% 0.00% +system.ruby.l1_cntrl0.S.Inv 325 0.00% 0.00% +system.ruby.l1_cntrl0.S.L1_Replacement 362 0.00% 0.00% +system.ruby.l1_cntrl0.E.Load 452 0.00% 0.00% +system.ruby.l1_cntrl0.E.Store 71 0.00% 0.00% +system.ruby.l1_cntrl0.E.Inv 219 0.00% 0.00% +system.ruby.l1_cntrl0.E.L1_Replacement 291 0.00% 0.00% +system.ruby.l1_cntrl0.M.Load 148 0.00% 0.00% +system.ruby.l1_cntrl0.M.Store 578 0.00% 0.00% +system.ruby.l1_cntrl0.M.Inv 141 0.00% 0.00% +system.ruby.l1_cntrl0.M.L1_Replacement 145 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data_Exclusive 583 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data_all_Acks 691 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Data_all_Acks 216 0.00% 0.00% +system.ruby.l1_cntrl0.M_I.WB_Ack 436 0.00% 0.00% +system.ruby.dir_cntrl0.Fetch 1460 0.00% 0.00% +system.ruby.dir_cntrl0.Data 277 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 1460 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 277 0.00% 0.00% +system.ruby.dir_cntrl0.CleanReplacement 1175 0.00% 0.00% +system.ruby.dir_cntrl0.I.Fetch 1460 0.00% 0.00% +system.ruby.dir_cntrl0.M.Data 277 0.00% 0.00% +system.ruby.dir_cntrl0.M.CleanReplacement 1175 0.00% 0.00% +system.ruby.dir_cntrl0.IM.Memory_Data 1460 0.00% 0.00% +system.ruby.dir_cntrl0.MI.Memory_Ack 277 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats index 0ce1fd4ab..f903fa47c 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats @@ -1,26 +1,24 @@ -Real time: Mar/06/2013 20:42:21 +Real time: Jun/08/2013 14:12:54 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.82 -Virtual_time_in_minutes: 0.0136667 -Virtual_time_in_hours: 0.000227778 -Virtual_time_in_days: 9.49074e-06 +Virtual_time_in_seconds: 0.64 +Virtual_time_in_minutes: 0.0106667 +Virtual_time_in_hours: 0.000177778 +Virtual_time_in_days: 7.40741e-06 Ruby_current_time: 117611 Ruby_start_time: 0 Ruby_cycles: 117611 -mbytes_resident: 56.1211 -mbytes_total: 148.367 -resident_ratio: 0.378311 - -ruby_cycles_executed: [ 117612 ] +mbytes_resident: 57.9688 +mbytes_total: 145.379 +resident_ratio: 0.398796 Busy Controller Counts: L1Cache-0:0 @@ -61,7 +59,6 @@ Request vs. RubySystem State Profile -------------------------------- -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- @@ -82,11 +79,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 13682 +page_reclaims: 11522 page_faults: 0 swaps: 0 -block_inputs: 0 -block_outputs: 96 +block_inputs: 8 +block_outputs: 88 Network Stats ------------- @@ -164,1246 +161,3 @@ links_utilized_percent_switch_3: 6.64705 outgoing_messages_switch_3_link_2_Writeback_Control: 1992 15936 [ 0 1093 899 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Unblock_Control: 1109 8872 [ 0 0 1109 0 0 0 0 0 0 0 ] base_latency: 1 - --- L1Cache --- - - Event Counts - -Load [1183 ] 1183 -Ifetch [6400 ] 6400 -Store [865 ] 865 -L1_Replacement [1379 ] 1379 -Own_GETX [0 ] 0 -Fwd_GETX [0 ] 0 -Fwd_GETS [0 ] 0 -Fwd_DMA [0 ] 0 -Inv [0 ] 0 -Ack [0 ] 0 -Data [0 ] 0 -Exclusive_Data [1362 ] 1362 -Writeback_Ack [0 ] 0 -Writeback_Ack_Data [1354 ] 1354 -Writeback_Nack [0 ] 0 -All_acks [191 ] 191 -Use_Timeout [1361 ] 1361 - - - Transitions - -I Load [525 ] 525 -I Ifetch [646 ] 646 -I Store [191 ] 191 -I L1_Replacement [0 ] 0 -I Inv [0 ] 0 - -S Load [0 ] 0 -S Ifetch [0 ] 0 -S Store [0 ] 0 -S L1_Replacement [0 ] 0 -S Fwd_GETS [0 ] 0 -S Fwd_DMA [0 ] 0 -S Inv [0 ] 0 - -O Load [0 ] 0 -O Ifetch [0 ] 0 -O Store [0 ] 0 -O L1_Replacement [0 ] 0 -O Fwd_GETX [0 ] 0 -O Fwd_GETS [0 ] 0 -O Fwd_DMA [0 ] 0 - -M Load [305 ] 305 -M Ifetch [3467 ] 3467 -M Store [51 ] 51 -M L1_Replacement [1086 ] 1086 -M Fwd_GETX [0 ] 0 -M Fwd_GETS [0 ] 0 -M Fwd_DMA [0 ] 0 - -M_W Load [112 ] 112 -M_W Ifetch [2287 ] 2287 -M_W Store [27 ] 27 -M_W L1_Replacement [17 ] 17 -M_W Own_GETX [0 ] 0 -M_W Fwd_GETX [0 ] 0 -M_W Fwd_GETS [0 ] 0 -M_W Fwd_DMA [0 ] 0 -M_W Inv [0 ] 0 -M_W Use_Timeout [1143 ] 1143 - -MM Load [234 ] 234 -MM Ifetch [0 ] 0 -MM Store [339 ] 339 -MM L1_Replacement [268 ] 268 -MM Fwd_GETX [0 ] 0 -MM Fwd_GETS [0 ] 0 -MM Fwd_DMA [0 ] 0 - -MM_W Load [7 ] 7 -MM_W Ifetch [0 ] 0 -MM_W Store [257 ] 257 -MM_W L1_Replacement [8 ] 8 -MM_W Own_GETX [0 ] 0 -MM_W Fwd_GETX [0 ] 0 -MM_W Fwd_GETS [0 ] 0 -MM_W Fwd_DMA [0 ] 0 -MM_W Inv [0 ] 0 -MM_W Use_Timeout [218 ] 218 - -IM Load [0 ] 0 -IM Ifetch [0 ] 0 -IM Store [0 ] 0 -IM L1_Replacement [0 ] 0 -IM Inv [0 ] 0 -IM Ack [0 ] 0 -IM Data [0 ] 0 -IM Exclusive_Data [191 ] 191 - -SM Load [0 ] 0 -SM Ifetch [0 ] 0 -SM Store [0 ] 0 -SM L1_Replacement [0 ] 0 -SM Fwd_GETS [0 ] 0 -SM Fwd_DMA [0 ] 0 -SM Inv [0 ] 0 -SM Ack [0 ] 0 -SM Data [0 ] 0 -SM Exclusive_Data [0 ] 0 - -OM Load [0 ] 0 -OM Ifetch [0 ] 0 -OM Store [0 ] 0 -OM L1_Replacement [0 ] 0 -OM Own_GETX [0 ] 0 -OM Fwd_GETX [0 ] 0 -OM Fwd_GETS [0 ] 0 -OM Fwd_DMA [0 ] 0 -OM Ack [0 ] 0 -OM All_acks [191 ] 191 - -IS Load [0 ] 0 -IS Ifetch [0 ] 0 -IS Store [0 ] 0 -IS L1_Replacement [0 ] 0 -IS Inv [0 ] 0 -IS Data [0 ] 0 -IS Exclusive_Data [1171 ] 1171 - -SI Load [0 ] 0 -SI Ifetch [0 ] 0 -SI Store [0 ] 0 -SI L1_Replacement [0 ] 0 -SI Fwd_GETS [0 ] 0 -SI Fwd_DMA [0 ] 0 -SI Inv [0 ] 0 -SI Writeback_Ack [0 ] 0 -SI Writeback_Ack_Data [0 ] 0 -SI Writeback_Nack [0 ] 0 - -OI Load [0 ] 0 -OI Ifetch [0 ] 0 -OI Store [0 ] 0 -OI L1_Replacement [0 ] 0 -OI Fwd_GETX [0 ] 0 -OI Fwd_GETS [0 ] 0 -OI Fwd_DMA [0 ] 0 -OI Writeback_Ack [0 ] 0 -OI Writeback_Ack_Data [0 ] 0 -OI Writeback_Nack [0 ] 0 - -MI Load [0 ] 0 -MI Ifetch [0 ] 0 -MI Store [0 ] 0 -MI L1_Replacement [0 ] 0 -MI Fwd_GETX [0 ] 0 -MI Fwd_GETS [0 ] 0 -MI Fwd_DMA [0 ] 0 -MI Writeback_Ack [0 ] 0 -MI Writeback_Ack_Data [1354 ] 1354 -MI Writeback_Nack [0 ] 0 - -II Load [0 ] 0 -II Ifetch [0 ] 0 -II Store [0 ] 0 -II L1_Replacement [0 ] 0 -II Inv [0 ] 0 -II Writeback_Ack [0 ] 0 -II Writeback_Ack_Data [0 ] 0 -II Writeback_Nack [0 ] 0 - - --- L2Cache --- - - Event Counts - -L1_GETS [1171 ] 1171 -L1_GETX [191 ] 191 -L1_PUTO [0 ] 0 -L1_PUTX [1354 ] 1354 -L1_PUTS_only [0 ] 0 -L1_PUTS [0 ] 0 -Fwd_GETX [0 ] 0 -Fwd_GETS [0 ] 0 -Fwd_DMA [0 ] 0 -Own_GETX [0 ] 0 -Inv [0 ] 0 -IntAck [0 ] 0 -ExtAck [0 ] 0 -All_Acks [130 ] 130 -Data [130 ] 130 -Data_Exclusive [979 ] 979 -L1_WBCLEANDATA [1058 ] 1058 -L1_WBDIRTYDATA [296 ] 296 -Writeback_Ack [1093 ] 1093 -Writeback_Nack [0 ] 0 -Unblock [0 ] 0 -Exclusive_Unblock [1362 ] 1362 -DmaAck [0 ] 0 -L2_Replacement [1093 ] 1093 - - - Transitions - -NP L1_GETS [979 ] 979 -NP L1_GETX [130 ] 130 -NP L1_PUTO [0 ] 0 -NP L1_PUTX [0 ] 0 -NP L1_PUTS [0 ] 0 -NP Inv [0 ] 0 - -I L1_GETS [0 ] 0 -I L1_GETX [0 ] 0 -I L1_PUTO [0 ] 0 -I L1_PUTX [0 ] 0 -I L1_PUTS [0 ] 0 -I Inv [0 ] 0 -I L2_Replacement [0 ] 0 - -ILS L1_GETS [0 ] 0 -ILS L1_GETX [0 ] 0 -ILS L1_PUTO [0 ] 0 -ILS L1_PUTX [0 ] 0 -ILS L1_PUTS_only [0 ] 0 -ILS L1_PUTS [0 ] 0 -ILS Inv [0 ] 0 -ILS L2_Replacement [0 ] 0 - -ILX L1_GETS [0 ] 0 -ILX L1_GETX [0 ] 0 -ILX L1_PUTO [0 ] 0 -ILX L1_PUTX [1354 ] 1354 -ILX L1_PUTS_only [0 ] 0 -ILX L1_PUTS [0 ] 0 -ILX Fwd_GETX [0 ] 0 -ILX Fwd_GETS [0 ] 0 -ILX Fwd_DMA [0 ] 0 -ILX Inv [0 ] 0 -ILX Data [0 ] 0 -ILX L2_Replacement [0 ] 0 - -ILO L1_GETS [0 ] 0 -ILO L1_GETX [0 ] 0 -ILO L1_PUTO [0 ] 0 -ILO L1_PUTX [0 ] 0 -ILO L1_PUTS [0 ] 0 -ILO Fwd_GETX [0 ] 0 -ILO Fwd_GETS [0 ] 0 -ILO Fwd_DMA [0 ] 0 -ILO Inv [0 ] 0 -ILO Data [0 ] 0 -ILO L2_Replacement [0 ] 0 - -ILOX L1_GETS [0 ] 0 -ILOX L1_GETX [0 ] 0 -ILOX L1_PUTO [0 ] 0 -ILOX L1_PUTX [0 ] 0 -ILOX L1_PUTS [0 ] 0 -ILOX Fwd_GETX [0 ] 0 -ILOX Fwd_GETS [0 ] 0 -ILOX Fwd_DMA [0 ] 0 -ILOX Data [0 ] 0 - -ILOS L1_GETS [0 ] 0 -ILOS L1_GETX [0 ] 0 -ILOS L1_PUTO [0 ] 0 -ILOS L1_PUTX [0 ] 0 -ILOS L1_PUTS_only [0 ] 0 -ILOS L1_PUTS [0 ] 0 -ILOS Fwd_GETX [0 ] 0 -ILOS Fwd_GETS [0 ] 0 -ILOS Fwd_DMA [0 ] 0 -ILOS Data [0 ] 0 -ILOS L2_Replacement [0 ] 0 - -ILOSX L1_GETS [0 ] 0 -ILOSX L1_GETX [0 ] 0 -ILOSX L1_PUTO [0 ] 0 -ILOSX L1_PUTX [0 ] 0 -ILOSX L1_PUTS_only [0 ] 0 -ILOSX L1_PUTS [0 ] 0 -ILOSX Fwd_GETX [0 ] 0 -ILOSX Fwd_GETS [0 ] 0 -ILOSX Fwd_DMA [0 ] 0 -ILOSX Data [0 ] 0 - -S L1_GETS [0 ] 0 -S L1_GETX [0 ] 0 -S L1_PUTX [0 ] 0 -S L1_PUTS [0 ] 0 -S Inv [0 ] 0 -S L2_Replacement [0 ] 0 - -O L1_GETS [0 ] 0 -O L1_GETX [0 ] 0 -O L1_PUTX [0 ] 0 -O Fwd_GETX [0 ] 0 -O Fwd_GETS [0 ] 0 -O Fwd_DMA [0 ] 0 -O L2_Replacement [0 ] 0 - -OLS L1_GETS [0 ] 0 -OLS L1_GETX [0 ] 0 -OLS L1_PUTX [0 ] 0 -OLS L1_PUTS_only [0 ] 0 -OLS L1_PUTS [0 ] 0 -OLS Fwd_GETX [0 ] 0 -OLS Fwd_GETS [0 ] 0 -OLS Fwd_DMA [0 ] 0 -OLS L2_Replacement [0 ] 0 - -OLSX L1_GETS [0 ] 0 -OLSX L1_GETX [0 ] 0 -OLSX L1_PUTO [0 ] 0 -OLSX L1_PUTX [0 ] 0 -OLSX L1_PUTS_only [0 ] 0 -OLSX L1_PUTS [0 ] 0 -OLSX Fwd_GETX [0 ] 0 -OLSX Fwd_GETS [0 ] 0 -OLSX Fwd_DMA [0 ] 0 -OLSX L2_Replacement [0 ] 0 - -SLS L1_GETS [0 ] 0 -SLS L1_GETX [0 ] 0 -SLS L1_PUTX [0 ] 0 -SLS L1_PUTS_only [0 ] 0 -SLS L1_PUTS [0 ] 0 -SLS Inv [0 ] 0 -SLS L2_Replacement [0 ] 0 - -M L1_GETS [192 ] 192 -M L1_GETX [61 ] 61 -M L1_PUTO [0 ] 0 -M L1_PUTX [0 ] 0 -M L1_PUTS [0 ] 0 -M Fwd_GETX [0 ] 0 -M Fwd_GETS [0 ] 0 -M Fwd_DMA [0 ] 0 -M L2_Replacement [1093 ] 1093 - -IFGX L1_GETS [0 ] 0 -IFGX L1_GETX [0 ] 0 -IFGX L1_PUTO [0 ] 0 -IFGX L1_PUTX [0 ] 0 -IFGX L1_PUTS_only [0 ] 0 -IFGX L1_PUTS [0 ] 0 -IFGX Fwd_GETX [0 ] 0 -IFGX Fwd_GETS [0 ] 0 -IFGX Fwd_DMA [0 ] 0 -IFGX Inv [0 ] 0 -IFGX Data [0 ] 0 -IFGX Data_Exclusive [0 ] 0 -IFGX L2_Replacement [0 ] 0 - -IFGS L1_GETS [0 ] 0 -IFGS L1_GETX [0 ] 0 -IFGS L1_PUTO [0 ] 0 -IFGS L1_PUTX [0 ] 0 -IFGS L1_PUTS_only [0 ] 0 -IFGS L1_PUTS [0 ] 0 -IFGS Fwd_GETX [0 ] 0 -IFGS Fwd_GETS [0 ] 0 -IFGS Fwd_DMA [0 ] 0 -IFGS Inv [0 ] 0 -IFGS Data [0 ] 0 -IFGS Data_Exclusive [0 ] 0 -IFGS L2_Replacement [0 ] 0 - -ISFGS L1_GETS [0 ] 0 -ISFGS L1_GETX [0 ] 0 -ISFGS L1_PUTO [0 ] 0 -ISFGS L1_PUTX [0 ] 0 -ISFGS L1_PUTS_only [0 ] 0 -ISFGS L1_PUTS [0 ] 0 -ISFGS Fwd_GETX [0 ] 0 -ISFGS Fwd_GETS [0 ] 0 -ISFGS Fwd_DMA [0 ] 0 -ISFGS Inv [0 ] 0 -ISFGS Data [0 ] 0 -ISFGS L2_Replacement [0 ] 0 - -IFGXX L1_GETS [0 ] 0 -IFGXX L1_GETX [0 ] 0 -IFGXX L1_PUTO [0 ] 0 -IFGXX L1_PUTX [0 ] 0 -IFGXX L1_PUTS_only [0 ] 0 -IFGXX L1_PUTS [0 ] 0 -IFGXX Fwd_GETX [0 ] 0 -IFGXX Fwd_GETS [0 ] 0 -IFGXX Fwd_DMA [0 ] 0 -IFGXX Inv [0 ] 0 -IFGXX IntAck [0 ] 0 -IFGXX All_Acks [0 ] 0 -IFGXX Data_Exclusive [0 ] 0 -IFGXX L2_Replacement [0 ] 0 - -OFGX L1_GETS [0 ] 0 -OFGX L1_GETX [0 ] 0 -OFGX L1_PUTO [0 ] 0 -OFGX L1_PUTX [0 ] 0 -OFGX L1_PUTS_only [0 ] 0 -OFGX L1_PUTS [0 ] 0 -OFGX Fwd_GETX [0 ] 0 -OFGX Fwd_GETS [0 ] 0 -OFGX Fwd_DMA [0 ] 0 -OFGX Inv [0 ] 0 -OFGX L2_Replacement [0 ] 0 - -OLSF L1_GETS [0 ] 0 -OLSF L1_GETX [0 ] 0 -OLSF L1_PUTO [0 ] 0 -OLSF L1_PUTX [0 ] 0 -OLSF L1_PUTS_only [0 ] 0 -OLSF L1_PUTS [0 ] 0 -OLSF Fwd_GETX [0 ] 0 -OLSF Fwd_GETS [0 ] 0 -OLSF Fwd_DMA [0 ] 0 -OLSF Inv [0 ] 0 -OLSF IntAck [0 ] 0 -OLSF All_Acks [0 ] 0 -OLSF L2_Replacement [0 ] 0 - -ILOW L1_GETS [0 ] 0 -ILOW L1_GETX [0 ] 0 -ILOW L1_PUTO [0 ] 0 -ILOW L1_PUTX [0 ] 0 -ILOW L1_PUTS_only [0 ] 0 -ILOW L1_PUTS [0 ] 0 -ILOW Fwd_GETX [0 ] 0 -ILOW Fwd_GETS [0 ] 0 -ILOW Fwd_DMA [0 ] 0 -ILOW Inv [0 ] 0 -ILOW L1_WBCLEANDATA [0 ] 0 -ILOW L1_WBDIRTYDATA [0 ] 0 -ILOW Unblock [0 ] 0 -ILOW L2_Replacement [0 ] 0 - -ILOXW L1_GETS [0 ] 0 -ILOXW L1_GETX [0 ] 0 -ILOXW L1_PUTO [0 ] 0 -ILOXW L1_PUTX [0 ] 0 -ILOXW L1_PUTS_only [0 ] 0 -ILOXW L1_PUTS [0 ] 0 -ILOXW Fwd_GETX [0 ] 0 -ILOXW Fwd_GETS [0 ] 0 -ILOXW Fwd_DMA [0 ] 0 -ILOXW Inv [0 ] 0 -ILOXW L1_WBCLEANDATA [0 ] 0 -ILOXW L1_WBDIRTYDATA [0 ] 0 -ILOXW Unblock [0 ] 0 -ILOXW L2_Replacement [0 ] 0 - -ILOSW L1_GETS [0 ] 0 -ILOSW L1_GETX [0 ] 0 -ILOSW L1_PUTO [0 ] 0 -ILOSW L1_PUTX [0 ] 0 -ILOSW L1_PUTS_only [0 ] 0 -ILOSW L1_PUTS [0 ] 0 -ILOSW Fwd_GETX [0 ] 0 -ILOSW Fwd_GETS [0 ] 0 -ILOSW Fwd_DMA [0 ] 0 -ILOSW Inv [0 ] 0 -ILOSW L1_WBCLEANDATA [0 ] 0 -ILOSW L1_WBDIRTYDATA [0 ] 0 -ILOSW Unblock [0 ] 0 -ILOSW L2_Replacement [0 ] 0 - -ILOSXW L1_GETS [0 ] 0 -ILOSXW L1_GETX [0 ] 0 -ILOSXW L1_PUTO [0 ] 0 -ILOSXW L1_PUTX [0 ] 0 -ILOSXW L1_PUTS_only [0 ] 0 -ILOSXW L1_PUTS [0 ] 0 -ILOSXW Fwd_GETX [0 ] 0 -ILOSXW Fwd_GETS [0 ] 0 -ILOSXW Fwd_DMA [0 ] 0 -ILOSXW Inv [0 ] 0 -ILOSXW L1_WBCLEANDATA [0 ] 0 -ILOSXW L1_WBDIRTYDATA [0 ] 0 -ILOSXW Unblock [0 ] 0 -ILOSXW L2_Replacement [0 ] 0 - -SLSW L1_GETS [0 ] 0 -SLSW L1_GETX [0 ] 0 -SLSW L1_PUTO [0 ] 0 -SLSW L1_PUTX [0 ] 0 -SLSW L1_PUTS_only [0 ] 0 -SLSW L1_PUTS [0 ] 0 -SLSW Fwd_GETX [0 ] 0 -SLSW Fwd_GETS [0 ] 0 -SLSW Fwd_DMA [0 ] 0 -SLSW Inv [0 ] 0 -SLSW Unblock [0 ] 0 -SLSW L2_Replacement [0 ] 0 - -OLSW L1_GETS [0 ] 0 -OLSW L1_GETX [0 ] 0 -OLSW L1_PUTO [0 ] 0 -OLSW L1_PUTX [0 ] 0 -OLSW L1_PUTS_only [0 ] 0 -OLSW L1_PUTS [0 ] 0 -OLSW Fwd_GETX [0 ] 0 -OLSW Fwd_GETS [0 ] 0 -OLSW Fwd_DMA [0 ] 0 -OLSW Inv [0 ] 0 -OLSW Unblock [0 ] 0 -OLSW L2_Replacement [0 ] 0 - -ILSW L1_GETS [0 ] 0 -ILSW L1_GETX [0 ] 0 -ILSW L1_PUTO [0 ] 0 -ILSW L1_PUTX [0 ] 0 -ILSW L1_PUTS_only [0 ] 0 -ILSW L1_PUTS [0 ] 0 -ILSW Fwd_GETX [0 ] 0 -ILSW Fwd_GETS [0 ] 0 -ILSW Fwd_DMA [0 ] 0 -ILSW Inv [0 ] 0 -ILSW L1_WBCLEANDATA [0 ] 0 -ILSW Unblock [0 ] 0 -ILSW L2_Replacement [0 ] 0 - -IW L1_GETS [0 ] 0 -IW L1_GETX [0 ] 0 -IW L1_PUTO [0 ] 0 -IW L1_PUTX [0 ] 0 -IW L1_PUTS_only [0 ] 0 -IW L1_PUTS [0 ] 0 -IW Fwd_GETX [0 ] 0 -IW Fwd_GETS [0 ] 0 -IW Fwd_DMA [0 ] 0 -IW Inv [0 ] 0 -IW L1_WBCLEANDATA [0 ] 0 -IW L2_Replacement [0 ] 0 - -OW L1_GETS [0 ] 0 -OW L1_GETX [0 ] 0 -OW L1_PUTO [0 ] 0 -OW L1_PUTX [0 ] 0 -OW L1_PUTS_only [0 ] 0 -OW L1_PUTS [0 ] 0 -OW Fwd_GETX [0 ] 0 -OW Fwd_GETS [0 ] 0 -OW Fwd_DMA [0 ] 0 -OW Inv [0 ] 0 -OW Unblock [0 ] 0 -OW L2_Replacement [0 ] 0 - -SW L1_GETS [0 ] 0 -SW L1_GETX [0 ] 0 -SW L1_PUTO [0 ] 0 -SW L1_PUTX [0 ] 0 -SW L1_PUTS_only [0 ] 0 -SW L1_PUTS [0 ] 0 -SW Fwd_GETX [0 ] 0 -SW Fwd_GETS [0 ] 0 -SW Fwd_DMA [0 ] 0 -SW Inv [0 ] 0 -SW Unblock [0 ] 0 -SW L2_Replacement [0 ] 0 - -OXW L1_GETS [0 ] 0 -OXW L1_GETX [0 ] 0 -OXW L1_PUTO [0 ] 0 -OXW L1_PUTX [0 ] 0 -OXW L1_PUTS_only [0 ] 0 -OXW L1_PUTS [0 ] 0 -OXW Fwd_GETX [0 ] 0 -OXW Fwd_GETS [0 ] 0 -OXW Fwd_DMA [0 ] 0 -OXW Inv [0 ] 0 -OXW Unblock [0 ] 0 -OXW L2_Replacement [0 ] 0 - -OLSXW L1_GETS [0 ] 0 -OLSXW L1_GETX [0 ] 0 -OLSXW L1_PUTO [0 ] 0 -OLSXW L1_PUTX [0 ] 0 -OLSXW L1_PUTS_only [0 ] 0 -OLSXW L1_PUTS [0 ] 0 -OLSXW Fwd_GETX [0 ] 0 -OLSXW Fwd_GETS [0 ] 0 -OLSXW Fwd_DMA [0 ] 0 -OLSXW Inv [0 ] 0 -OLSXW Unblock [0 ] 0 -OLSXW L2_Replacement [0 ] 0 - -ILXW L1_GETS [0 ] 0 -ILXW L1_GETX [0 ] 0 -ILXW L1_PUTO [0 ] 0 -ILXW L1_PUTX [0 ] 0 -ILXW L1_PUTS_only [0 ] 0 -ILXW L1_PUTS [0 ] 0 -ILXW Fwd_GETX [0 ] 0 -ILXW Fwd_GETS [0 ] 0 -ILXW Fwd_DMA [0 ] 0 -ILXW Inv [0 ] 0 -ILXW Data [0 ] 0 -ILXW L1_WBCLEANDATA [1058 ] 1058 -ILXW L1_WBDIRTYDATA [296 ] 296 -ILXW Unblock [0 ] 0 -ILXW L2_Replacement [0 ] 0 - -IFLS L1_GETS [0 ] 0 -IFLS L1_GETX [0 ] 0 -IFLS L1_PUTO [0 ] 0 -IFLS L1_PUTX [0 ] 0 -IFLS L1_PUTS_only [0 ] 0 -IFLS L1_PUTS [0 ] 0 -IFLS Fwd_GETX [0 ] 0 -IFLS Fwd_GETS [0 ] 0 -IFLS Fwd_DMA [0 ] 0 -IFLS Inv [0 ] 0 -IFLS Unblock [0 ] 0 -IFLS L2_Replacement [0 ] 0 - -IFLO L1_GETS [0 ] 0 -IFLO L1_GETX [0 ] 0 -IFLO L1_PUTO [0 ] 0 -IFLO L1_PUTX [0 ] 0 -IFLO L1_PUTS_only [0 ] 0 -IFLO L1_PUTS [0 ] 0 -IFLO Fwd_GETX [0 ] 0 -IFLO Fwd_GETS [0 ] 0 -IFLO Fwd_DMA [0 ] 0 -IFLO Inv [0 ] 0 -IFLO Unblock [0 ] 0 -IFLO L2_Replacement [0 ] 0 - -IFLOX L1_GETS [0 ] 0 -IFLOX L1_GETX [0 ] 0 -IFLOX L1_PUTO [0 ] 0 -IFLOX L1_PUTX [0 ] 0 -IFLOX L1_PUTS_only [0 ] 0 -IFLOX L1_PUTS [0 ] 0 -IFLOX Fwd_GETX [0 ] 0 -IFLOX Fwd_GETS [0 ] 0 -IFLOX Fwd_DMA [0 ] 0 -IFLOX Inv [0 ] 0 -IFLOX Unblock [0 ] 0 -IFLOX Exclusive_Unblock [0 ] 0 -IFLOX L2_Replacement [0 ] 0 - -IFLOXX L1_GETS [0 ] 0 -IFLOXX L1_GETX [0 ] 0 -IFLOXX L1_PUTO [0 ] 0 -IFLOXX L1_PUTX [0 ] 0 -IFLOXX L1_PUTS_only [0 ] 0 -IFLOXX L1_PUTS [0 ] 0 -IFLOXX Fwd_GETX [0 ] 0 -IFLOXX Fwd_GETS [0 ] 0 -IFLOXX Fwd_DMA [0 ] 0 -IFLOXX Inv [0 ] 0 -IFLOXX Unblock [0 ] 0 -IFLOXX Exclusive_Unblock [0 ] 0 -IFLOXX L2_Replacement [0 ] 0 - -IFLOSX L1_GETS [0 ] 0 -IFLOSX L1_GETX [0 ] 0 -IFLOSX L1_PUTO [0 ] 0 -IFLOSX L1_PUTX [0 ] 0 -IFLOSX L1_PUTS_only [0 ] 0 -IFLOSX L1_PUTS [0 ] 0 -IFLOSX Fwd_GETX [0 ] 0 -IFLOSX Fwd_GETS [0 ] 0 -IFLOSX Fwd_DMA [0 ] 0 -IFLOSX Inv [0 ] 0 -IFLOSX Unblock [0 ] 0 -IFLOSX Exclusive_Unblock [0 ] 0 -IFLOSX L2_Replacement [0 ] 0 - -IFLXO L1_GETS [0 ] 0 -IFLXO L1_GETX [0 ] 0 -IFLXO L1_PUTO [0 ] 0 -IFLXO L1_PUTX [0 ] 0 -IFLXO L1_PUTS_only [0 ] 0 -IFLXO L1_PUTS [0 ] 0 -IFLXO Fwd_GETX [0 ] 0 -IFLXO Fwd_GETS [0 ] 0 -IFLXO Fwd_DMA [0 ] 0 -IFLXO Inv [0 ] 0 -IFLXO Exclusive_Unblock [0 ] 0 -IFLXO L2_Replacement [0 ] 0 - -IGS L1_GETS [0 ] 0 -IGS L1_GETX [0 ] 0 -IGS L1_PUTO [0 ] 0 -IGS L1_PUTX [0 ] 0 -IGS L1_PUTS_only [0 ] 0 -IGS L1_PUTS [0 ] 0 -IGS Fwd_GETX [0 ] 0 -IGS Fwd_GETS [0 ] 0 -IGS Fwd_DMA [0 ] 0 -IGS Own_GETX [0 ] 0 -IGS Inv [0 ] 0 -IGS Data [0 ] 0 -IGS Data_Exclusive [979 ] 979 -IGS Unblock [0 ] 0 -IGS Exclusive_Unblock [979 ] 979 -IGS L2_Replacement [0 ] 0 - -IGM L1_GETS [0 ] 0 -IGM L1_GETX [0 ] 0 -IGM L1_PUTO [0 ] 0 -IGM L1_PUTX [0 ] 0 -IGM L1_PUTS_only [0 ] 0 -IGM L1_PUTS [0 ] 0 -IGM Fwd_GETX [0 ] 0 -IGM Fwd_GETS [0 ] 0 -IGM Fwd_DMA [0 ] 0 -IGM Own_GETX [0 ] 0 -IGM Inv [0 ] 0 -IGM ExtAck [0 ] 0 -IGM Data [130 ] 130 -IGM Data_Exclusive [0 ] 0 -IGM L2_Replacement [0 ] 0 - -IGMLS L1_GETS [0 ] 0 -IGMLS L1_GETX [0 ] 0 -IGMLS L1_PUTO [0 ] 0 -IGMLS L1_PUTX [0 ] 0 -IGMLS L1_PUTS_only [0 ] 0 -IGMLS L1_PUTS [0 ] 0 -IGMLS Inv [0 ] 0 -IGMLS IntAck [0 ] 0 -IGMLS ExtAck [0 ] 0 -IGMLS All_Acks [0 ] 0 -IGMLS Data [0 ] 0 -IGMLS Data_Exclusive [0 ] 0 -IGMLS L2_Replacement [0 ] 0 - -IGMO L1_GETS [0 ] 0 -IGMO L1_GETX [0 ] 0 -IGMO L1_PUTO [0 ] 0 -IGMO L1_PUTX [0 ] 0 -IGMO L1_PUTS_only [0 ] 0 -IGMO L1_PUTS [0 ] 0 -IGMO Fwd_GETX [0 ] 0 -IGMO Fwd_GETS [0 ] 0 -IGMO Fwd_DMA [0 ] 0 -IGMO Own_GETX [0 ] 0 -IGMO ExtAck [0 ] 0 -IGMO All_Acks [130 ] 130 -IGMO Exclusive_Unblock [130 ] 130 -IGMO L2_Replacement [0 ] 0 - -IGMIO L1_GETS [0 ] 0 -IGMIO L1_GETX [0 ] 0 -IGMIO L1_PUTO [0 ] 0 -IGMIO L1_PUTX [0 ] 0 -IGMIO L1_PUTS_only [0 ] 0 -IGMIO L1_PUTS [0 ] 0 -IGMIO Fwd_GETX [0 ] 0 -IGMIO Fwd_GETS [0 ] 0 -IGMIO Fwd_DMA [0 ] 0 -IGMIO Own_GETX [0 ] 0 -IGMIO ExtAck [0 ] 0 -IGMIO All_Acks [0 ] 0 - -OGMIO L1_GETS [0 ] 0 -OGMIO L1_GETX [0 ] 0 -OGMIO L1_PUTO [0 ] 0 -OGMIO L1_PUTX [0 ] 0 -OGMIO L1_PUTS_only [0 ] 0 -OGMIO L1_PUTS [0 ] 0 -OGMIO Fwd_GETX [0 ] 0 -OGMIO Fwd_GETS [0 ] 0 -OGMIO Fwd_DMA [0 ] 0 -OGMIO Own_GETX [0 ] 0 -OGMIO ExtAck [0 ] 0 -OGMIO All_Acks [0 ] 0 - -IGMIOF L1_GETS [0 ] 0 -IGMIOF L1_GETX [0 ] 0 -IGMIOF L1_PUTO [0 ] 0 -IGMIOF L1_PUTX [0 ] 0 -IGMIOF L1_PUTS_only [0 ] 0 -IGMIOF L1_PUTS [0 ] 0 -IGMIOF IntAck [0 ] 0 -IGMIOF All_Acks [0 ] 0 -IGMIOF Data_Exclusive [0 ] 0 - -IGMIOFS L1_GETS [0 ] 0 -IGMIOFS L1_GETX [0 ] 0 -IGMIOFS L1_PUTO [0 ] 0 -IGMIOFS L1_PUTX [0 ] 0 -IGMIOFS L1_PUTS_only [0 ] 0 -IGMIOFS L1_PUTS [0 ] 0 -IGMIOFS Fwd_GETX [0 ] 0 -IGMIOFS Fwd_GETS [0 ] 0 -IGMIOFS Fwd_DMA [0 ] 0 -IGMIOFS Inv [0 ] 0 -IGMIOFS Data [0 ] 0 -IGMIOFS L2_Replacement [0 ] 0 - -OGMIOF L1_GETS [0 ] 0 -OGMIOF L1_GETX [0 ] 0 -OGMIOF L1_PUTO [0 ] 0 -OGMIOF L1_PUTX [0 ] 0 -OGMIOF L1_PUTS_only [0 ] 0 -OGMIOF L1_PUTS [0 ] 0 -OGMIOF IntAck [0 ] 0 -OGMIOF All_Acks [0 ] 0 - -II L1_GETS [0 ] 0 -II L1_GETX [0 ] 0 -II L1_PUTO [0 ] 0 -II L1_PUTX [0 ] 0 -II L1_PUTS_only [0 ] 0 -II L1_PUTS [0 ] 0 -II IntAck [0 ] 0 -II All_Acks [0 ] 0 - -MM L1_GETS [0 ] 0 -MM L1_GETX [0 ] 0 -MM L1_PUTO [0 ] 0 -MM L1_PUTX [0 ] 0 -MM L1_PUTS_only [0 ] 0 -MM L1_PUTS [0 ] 0 -MM Fwd_GETX [0 ] 0 -MM Fwd_GETS [0 ] 0 -MM Fwd_DMA [0 ] 0 -MM Inv [0 ] 0 -MM Exclusive_Unblock [61 ] 61 -MM L2_Replacement [0 ] 0 - -SS L1_GETS [0 ] 0 -SS L1_GETX [0 ] 0 -SS L1_PUTO [0 ] 0 -SS L1_PUTX [0 ] 0 -SS L1_PUTS_only [0 ] 0 -SS L1_PUTS [0 ] 0 -SS Fwd_GETX [0 ] 0 -SS Fwd_GETS [0 ] 0 -SS Fwd_DMA [0 ] 0 -SS Inv [0 ] 0 -SS Unblock [0 ] 0 -SS L2_Replacement [0 ] 0 - -OO L1_GETS [0 ] 0 -OO L1_GETX [0 ] 0 -OO L1_PUTO [0 ] 0 -OO L1_PUTX [0 ] 0 -OO L1_PUTS_only [0 ] 0 -OO L1_PUTS [0 ] 0 -OO Fwd_GETX [0 ] 0 -OO Fwd_GETS [0 ] 0 -OO Fwd_DMA [0 ] 0 -OO Inv [0 ] 0 -OO Unblock [0 ] 0 -OO Exclusive_Unblock [192 ] 192 -OO L2_Replacement [0 ] 0 - -OLSS L1_GETS [0 ] 0 -OLSS L1_GETX [0 ] 0 -OLSS L1_PUTO [0 ] 0 -OLSS L1_PUTX [0 ] 0 -OLSS L1_PUTS_only [0 ] 0 -OLSS L1_PUTS [0 ] 0 -OLSS Fwd_GETX [0 ] 0 -OLSS Fwd_GETS [0 ] 0 -OLSS Fwd_DMA [0 ] 0 -OLSS Inv [0 ] 0 -OLSS Unblock [0 ] 0 -OLSS L2_Replacement [0 ] 0 - -OLSXS L1_GETS [0 ] 0 -OLSXS L1_GETX [0 ] 0 -OLSXS L1_PUTO [0 ] 0 -OLSXS L1_PUTX [0 ] 0 -OLSXS L1_PUTS_only [0 ] 0 -OLSXS L1_PUTS [0 ] 0 -OLSXS Fwd_GETX [0 ] 0 -OLSXS Fwd_GETS [0 ] 0 -OLSXS Fwd_DMA [0 ] 0 -OLSXS Inv [0 ] 0 -OLSXS Unblock [0 ] 0 -OLSXS L2_Replacement [0 ] 0 - -SLSS L1_GETS [0 ] 0 -SLSS L1_GETX [0 ] 0 -SLSS L1_PUTO [0 ] 0 -SLSS L1_PUTX [0 ] 0 -SLSS L1_PUTS_only [0 ] 0 -SLSS L1_PUTS [0 ] 0 -SLSS Fwd_GETX [0 ] 0 -SLSS Fwd_GETS [0 ] 0 -SLSS Fwd_DMA [0 ] 0 -SLSS Inv [0 ] 0 -SLSS Unblock [0 ] 0 -SLSS L2_Replacement [0 ] 0 - -OI L1_GETS [0 ] 0 -OI L1_GETX [0 ] 0 -OI L1_PUTO [0 ] 0 -OI L1_PUTX [0 ] 0 -OI L1_PUTS_only [0 ] 0 -OI L1_PUTS [0 ] 0 -OI Fwd_GETX [0 ] 0 -OI Fwd_GETS [0 ] 0 -OI Fwd_DMA [0 ] 0 -OI Writeback_Ack [0 ] 0 -OI Writeback_Nack [0 ] 0 -OI L2_Replacement [0 ] 0 - -MI L1_GETS [0 ] 0 -MI L1_GETX [0 ] 0 -MI L1_PUTO [0 ] 0 -MI L1_PUTX [0 ] 0 -MI L1_PUTS_only [0 ] 0 -MI L1_PUTS [0 ] 0 -MI Fwd_GETX [0 ] 0 -MI Fwd_GETS [0 ] 0 -MI Fwd_DMA [0 ] 0 -MI Writeback_Ack [1093 ] 1093 -MI L2_Replacement [0 ] 0 - -MII L1_GETS [0 ] 0 -MII L1_GETX [0 ] 0 -MII L1_PUTO [0 ] 0 -MII L1_PUTX [0 ] 0 -MII L1_PUTS_only [0 ] 0 -MII L1_PUTS [0 ] 0 -MII Writeback_Ack [0 ] 0 -MII Writeback_Nack [0 ] 0 -MII L2_Replacement [0 ] 0 - -OLSI L1_GETS [0 ] 0 -OLSI L1_GETX [0 ] 0 -OLSI L1_PUTO [0 ] 0 -OLSI L1_PUTX [0 ] 0 -OLSI L1_PUTS_only [0 ] 0 -OLSI L1_PUTS [0 ] 0 -OLSI Fwd_GETX [0 ] 0 -OLSI Fwd_GETS [0 ] 0 -OLSI Fwd_DMA [0 ] 0 -OLSI Writeback_Ack [0 ] 0 -OLSI L2_Replacement [0 ] 0 - -ILSI L1_GETS [0 ] 0 -ILSI L1_GETX [0 ] 0 -ILSI L1_PUTO [0 ] 0 -ILSI L1_PUTX [0 ] 0 -ILSI L1_PUTS_only [0 ] 0 -ILSI L1_PUTS [0 ] 0 -ILSI IntAck [0 ] 0 -ILSI All_Acks [0 ] 0 -ILSI Writeback_Ack [0 ] 0 -ILSI L2_Replacement [0 ] 0 - -ILOSD L1_GETS [0 ] 0 -ILOSD L1_GETX [0 ] 0 -ILOSD L1_PUTO [0 ] 0 -ILOSD L1_PUTX [0 ] 0 -ILOSD L1_PUTS_only [0 ] 0 -ILOSD L1_PUTS [0 ] 0 -ILOSD Fwd_GETX [0 ] 0 -ILOSD Fwd_GETS [0 ] 0 -ILOSD Fwd_DMA [0 ] 0 -ILOSD Own_GETX [0 ] 0 -ILOSD Inv [0 ] 0 -ILOSD DmaAck [0 ] 0 -ILOSD L2_Replacement [0 ] 0 - -ILOSXD L1_GETS [0 ] 0 -ILOSXD L1_GETX [0 ] 0 -ILOSXD L1_PUTO [0 ] 0 -ILOSXD L1_PUTX [0 ] 0 -ILOSXD L1_PUTS_only [0 ] 0 -ILOSXD L1_PUTS [0 ] 0 -ILOSXD Fwd_GETX [0 ] 0 -ILOSXD Fwd_GETS [0 ] 0 -ILOSXD Fwd_DMA [0 ] 0 -ILOSXD Own_GETX [0 ] 0 -ILOSXD Inv [0 ] 0 -ILOSXD DmaAck [0 ] 0 -ILOSXD L2_Replacement [0 ] 0 - -ILOD L1_GETS [0 ] 0 -ILOD L1_GETX [0 ] 0 -ILOD L1_PUTO [0 ] 0 -ILOD L1_PUTX [0 ] 0 -ILOD L1_PUTS_only [0 ] 0 -ILOD L1_PUTS [0 ] 0 -ILOD Fwd_GETX [0 ] 0 -ILOD Fwd_GETS [0 ] 0 -ILOD Fwd_DMA [0 ] 0 -ILOD Own_GETX [0 ] 0 -ILOD Inv [0 ] 0 -ILOD DmaAck [0 ] 0 -ILOD L2_Replacement [0 ] 0 - -ILXD L1_GETS [0 ] 0 -ILXD L1_GETX [0 ] 0 -ILXD L1_PUTO [0 ] 0 -ILXD L1_PUTX [0 ] 0 -ILXD L1_PUTS_only [0 ] 0 -ILXD L1_PUTS [0 ] 0 -ILXD Fwd_GETX [0 ] 0 -ILXD Fwd_GETS [0 ] 0 -ILXD Fwd_DMA [0 ] 0 -ILXD Own_GETX [0 ] 0 -ILXD Inv [0 ] 0 -ILXD DmaAck [0 ] 0 -ILXD L2_Replacement [0 ] 0 - -ILOXD L1_GETS [0 ] 0 -ILOXD L1_GETX [0 ] 0 -ILOXD L1_PUTO [0 ] 0 -ILOXD L1_PUTX [0 ] 0 -ILOXD L1_PUTS_only [0 ] 0 -ILOXD L1_PUTS [0 ] 0 -ILOXD Fwd_GETX [0 ] 0 -ILOXD Fwd_GETS [0 ] 0 -ILOXD Fwd_DMA [0 ] 0 -ILOXD Own_GETX [0 ] 0 -ILOXD Inv [0 ] 0 -ILOXD DmaAck [0 ] 0 -ILOXD L2_Replacement [0 ] 0 - -Memory controller: system.ruby.dir_cntrl0.memBuffer: - memory_total_requests: 1303 - memory_reads: 1109 - memory_writes: 194 - memory_refreshes: 817 - memory_total_request_delays: 115 - memory_delays_per_request: 0.0882579 - memory_delays_in_input_queue: 0 - memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 115 - memory_stalls_for_bank_busy: 40 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 17 - memory_stalls_for_bus: 55 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 3 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 74 17 45 40 54 99 29 16 19 22 31 34 52 48 38 30 39 21 21 27 28 37 55 22 31 21 32 69 84 103 13 52 - - --- Directory --- - - Event Counts - -GETX [130 ] 130 -GETS [979 ] 979 -PUTX [1093 ] 1093 -PUTO [0 ] 0 -PUTO_SHARERS [0 ] 0 -Unblock [0 ] 0 -Last_Unblock [0 ] 0 -Exclusive_Unblock [1109 ] 1109 -Clean_Writeback [899 ] 899 -Dirty_Writeback [194 ] 194 -Memory_Data [1109 ] 1109 -Memory_Ack [194 ] 194 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -DMA_ACK [0 ] 0 -Data [0 ] 0 - - - Transitions - -I GETX [130 ] 130 -I GETS [979 ] 979 -I PUTX [0 ] 0 -I PUTO [0 ] 0 -I Memory_Data [0 ] 0 -I Memory_Ack [193 ] 193 -I DMA_READ [0 ] 0 -I DMA_WRITE [0 ] 0 - -S GETX [0 ] 0 -S GETS [0 ] 0 -S PUTX [0 ] 0 -S PUTO [0 ] 0 -S Memory_Data [0 ] 0 -S Memory_Ack [0 ] 0 -S DMA_READ [0 ] 0 -S DMA_WRITE [0 ] 0 - -O GETX [0 ] 0 -O GETS [0 ] 0 -O PUTX [0 ] 0 -O PUTO [0 ] 0 -O PUTO_SHARERS [0 ] 0 -O Memory_Data [0 ] 0 -O Memory_Ack [0 ] 0 -O DMA_READ [0 ] 0 -O DMA_WRITE [0 ] 0 - -M GETX [0 ] 0 -M GETS [0 ] 0 -M PUTX [1093 ] 1093 -M PUTO [0 ] 0 -M PUTO_SHARERS [0 ] 0 -M Memory_Data [0 ] 0 -M Memory_Ack [0 ] 0 -M DMA_READ [0 ] 0 -M DMA_WRITE [0 ] 0 - -IS GETX [0 ] 0 -IS GETS [0 ] 0 -IS PUTX [0 ] 0 -IS PUTO [0 ] 0 -IS PUTO_SHARERS [0 ] 0 -IS Unblock [0 ] 0 -IS Exclusive_Unblock [979 ] 979 -IS Memory_Data [979 ] 979 -IS Memory_Ack [1 ] 1 -IS DMA_READ [0 ] 0 -IS DMA_WRITE [0 ] 0 - -SS GETX [0 ] 0 -SS GETS [0 ] 0 -SS PUTX [0 ] 0 -SS PUTO [0 ] 0 -SS PUTO_SHARERS [0 ] 0 -SS Unblock [0 ] 0 -SS Last_Unblock [0 ] 0 -SS Memory_Data [0 ] 0 -SS Memory_Ack [0 ] 0 -SS DMA_READ [0 ] 0 -SS DMA_WRITE [0 ] 0 - -OO GETX [0 ] 0 -OO GETS [0 ] 0 -OO PUTX [0 ] 0 -OO PUTO [0 ] 0 -OO PUTO_SHARERS [0 ] 0 -OO Unblock [0 ] 0 -OO Last_Unblock [0 ] 0 -OO Memory_Data [0 ] 0 -OO Memory_Ack [0 ] 0 -OO DMA_READ [0 ] 0 -OO DMA_WRITE [0 ] 0 - -MO GETX [0 ] 0 -MO GETS [0 ] 0 -MO PUTX [0 ] 0 -MO PUTO [0 ] 0 -MO PUTO_SHARERS [0 ] 0 -MO Unblock [0 ] 0 -MO Exclusive_Unblock [0 ] 0 -MO Memory_Data [0 ] 0 -MO Memory_Ack [0 ] 0 -MO DMA_READ [0 ] 0 -MO DMA_WRITE [0 ] 0 - -MM GETX [0 ] 0 -MM GETS [0 ] 0 -MM PUTX [0 ] 0 -MM PUTO [0 ] 0 -MM PUTO_SHARERS [0 ] 0 -MM Exclusive_Unblock [130 ] 130 -MM Memory_Data [130 ] 130 -MM Memory_Ack [0 ] 0 -MM DMA_READ [0 ] 0 -MM DMA_WRITE [0 ] 0 - - -MI GETX [0 ] 0 -MI GETS [0 ] 0 -MI PUTX [0 ] 0 -MI PUTO [0 ] 0 -MI PUTO_SHARERS [0 ] 0 -MI Unblock [0 ] 0 -MI Clean_Writeback [899 ] 899 -MI Dirty_Writeback [194 ] 194 -MI Memory_Data [0 ] 0 -MI Memory_Ack [0 ] 0 -MI DMA_READ [0 ] 0 -MI DMA_WRITE [0 ] 0 - -MIS GETX [0 ] 0 -MIS GETS [0 ] 0 -MIS PUTX [0 ] 0 -MIS PUTO [0 ] 0 -MIS PUTO_SHARERS [0 ] 0 -MIS Unblock [0 ] 0 -MIS Clean_Writeback [0 ] 0 -MIS Dirty_Writeback [0 ] 0 -MIS Memory_Data [0 ] 0 -MIS Memory_Ack [0 ] 0 -MIS DMA_READ [0 ] 0 -MIS DMA_WRITE [0 ] 0 - -OS GETX [0 ] 0 -OS GETS [0 ] 0 -OS PUTX [0 ] 0 -OS PUTO [0 ] 0 -OS PUTO_SHARERS [0 ] 0 -OS Unblock [0 ] 0 -OS Clean_Writeback [0 ] 0 -OS Dirty_Writeback [0 ] 0 -OS Memory_Data [0 ] 0 -OS Memory_Ack [0 ] 0 -OS DMA_READ [0 ] 0 -OS DMA_WRITE [0 ] 0 - -OSS GETX [0 ] 0 -OSS GETS [0 ] 0 -OSS PUTX [0 ] 0 -OSS PUTO [0 ] 0 -OSS PUTO_SHARERS [0 ] 0 -OSS Unblock [0 ] 0 -OSS Clean_Writeback [0 ] 0 -OSS Dirty_Writeback [0 ] 0 -OSS Memory_Data [0 ] 0 -OSS Memory_Ack [0 ] 0 -OSS DMA_READ [0 ] 0 -OSS DMA_WRITE [0 ] 0 - -XI_M GETX [0 ] 0 -XI_M GETS [0 ] 0 -XI_M PUTX [0 ] 0 -XI_M PUTO [0 ] 0 -XI_M PUTO_SHARERS [0 ] 0 -XI_M Memory_Data [0 ] 0 -XI_M Memory_Ack [0 ] 0 -XI_M DMA_READ [0 ] 0 -XI_M DMA_WRITE [0 ] 0 - -XI_U GETX [0 ] 0 -XI_U GETS [0 ] 0 -XI_U PUTX [0 ] 0 -XI_U PUTO [0 ] 0 -XI_U PUTO_SHARERS [0 ] 0 -XI_U Exclusive_Unblock [0 ] 0 -XI_U Memory_Ack [0 ] 0 -XI_U DMA_READ [0 ] 0 -XI_U DMA_WRITE [0 ] 0 - -OI_D GETX [0 ] 0 -OI_D GETS [0 ] 0 -OI_D PUTX [0 ] 0 -OI_D PUTO [0 ] 0 -OI_D PUTO_SHARERS [0 ] 0 -OI_D DMA_READ [0 ] 0 -OI_D DMA_WRITE [0 ] 0 -OI_D Data [0 ] 0 - -OD GETX [0 ] 0 -OD GETS [0 ] 0 -OD PUTX [0 ] 0 -OD PUTO [0 ] 0 -OD PUTO_SHARERS [0 ] 0 -OD DMA_READ [0 ] 0 -OD DMA_WRITE [0 ] 0 -OD DMA_ACK [0 ] 0 - -MD GETX [0 ] 0 -MD GETS [0 ] 0 -MD PUTX [0 ] 0 -MD PUTO [0 ] 0 -MD PUTO_SHARERS [0 ] 0 -MD DMA_READ [0 ] 0 -MD DMA_WRITE [0 ] 0 -MD DMA_ACK [0 ] 0 - diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index be314d3f7..0f62874a4 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000118 # Nu sim_ticks 117611 # Number of ticks simulated final_tick 117611 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 18838 # Simulator instruction rate (inst/s) -host_op_rate 18837 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 346683 # Simulator tick rate (ticks/s) -host_mem_usage 154776 # Number of bytes of host memory used -host_seconds 0.34 # Real time elapsed on the host +host_inst_rate 28363 # Simulator instruction rate (inst/s) +host_op_rate 28361 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 521945 # Simulator tick rate (ticks/s) +host_mem_usage 148872 # Number of bytes of host memory used +host_seconds 0.23 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.ruby.l2_cntrl0.L2cache.demand_hits 253 # Number of cache demand hits @@ -20,6 +20,20 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses +system.ruby.dir_cntrl0.memBuffer.memReq 1303 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 1109 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 194 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 817 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 115 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 115 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.088258 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 40 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 55 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 3 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 17 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 74 5.68% 5.68% | 17 1.30% 6.98% | 45 3.45% 10.44% | 40 3.07% 13.51% | 54 4.14% 17.65% | 99 7.60% 25.25% | 29 2.23% 27.48% | 16 1.23% 28.70% | 19 1.46% 30.16% | 22 1.69% 31.85% | 31 2.38% 34.23% | 34 2.61% 36.84% | 52 3.99% 40.83% | 48 3.68% 44.51% | 38 2.92% 47.43% | 30 2.30% 49.73% | 39 2.99% 52.72% | 21 1.61% 54.34% | 21 1.61% 55.95% | 27 2.07% 58.02% | 28 2.15% 60.17% | 37 2.84% 63.01% | 55 4.22% 67.23% | 22 1.69% 68.92% | 31 2.38% 71.30% | 21 1.61% 72.91% | 32 2.46% 75.36% | 69 5.30% 80.66% | 84 6.45% 87.11% | 103 7.90% 95.01% | 13 1.00% 96.01% | 52 3.99% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1303 # Number of accesses per bank + system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -75,5 +89,82 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 117611 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles +system.ruby.l2_cntrl0.L1_GETS 1171 0.00% 0.00% +system.ruby.l2_cntrl0.L1_GETX 191 0.00% 0.00% +system.ruby.l2_cntrl0.L1_PUTX 1354 0.00% 0.00% +system.ruby.l2_cntrl0.All_Acks 130 0.00% 0.00% +system.ruby.l2_cntrl0.Data 130 0.00% 0.00% +system.ruby.l2_cntrl0.Data_Exclusive 979 0.00% 0.00% +system.ruby.l2_cntrl0.L1_WBCLEANDATA 1058 0.00% 0.00% +system.ruby.l2_cntrl0.L1_WBDIRTYDATA 296 0.00% 0.00% +system.ruby.l2_cntrl0.Writeback_Ack 1093 0.00% 0.00% +system.ruby.l2_cntrl0.Exclusive_Unblock 1362 0.00% 0.00% +system.ruby.l2_cntrl0.L2_Replacement 1093 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETS 979 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETX 130 0.00% 0.00% +system.ruby.l2_cntrl0.ILX.L1_PUTX 1354 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETS 192 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETX 61 0.00% 0.00% +system.ruby.l2_cntrl0.M.L2_Replacement 1093 0.00% 0.00% +system.ruby.l2_cntrl0.ILXW.L1_WBCLEANDATA 1058 0.00% 0.00% +system.ruby.l2_cntrl0.ILXW.L1_WBDIRTYDATA 296 0.00% 0.00% +system.ruby.l2_cntrl0.IGS.Data_Exclusive 979 0.00% 0.00% +system.ruby.l2_cntrl0.IGS.Exclusive_Unblock 979 0.00% 0.00% +system.ruby.l2_cntrl0.IGM.Data 130 0.00% 0.00% +system.ruby.l2_cntrl0.IGMO.All_Acks 130 0.00% 0.00% +system.ruby.l2_cntrl0.IGMO.Exclusive_Unblock 130 0.00% 0.00% +system.ruby.l2_cntrl0.MM.Exclusive_Unblock 61 0.00% 0.00% +system.ruby.l2_cntrl0.OO.Exclusive_Unblock 192 0.00% 0.00% +system.ruby.l2_cntrl0.MI.Writeback_Ack 1093 0.00% 0.00% +system.ruby.l1_cntrl0.Load 1183 0.00% 0.00% +system.ruby.l1_cntrl0.Ifetch 6400 0.00% 0.00% +system.ruby.l1_cntrl0.Store 865 0.00% 0.00% +system.ruby.l1_cntrl0.L1_Replacement 1379 0.00% 0.00% +system.ruby.l1_cntrl0.Exclusive_Data 1362 0.00% 0.00% +system.ruby.l1_cntrl0.Writeback_Ack_Data 1354 0.00% 0.00% +system.ruby.l1_cntrl0.All_acks 191 0.00% 0.00% +system.ruby.l1_cntrl0.Use_Timeout 1361 0.00% 0.00% +system.ruby.l1_cntrl0.I.Load 525 0.00% 0.00% +system.ruby.l1_cntrl0.I.Ifetch 646 0.00% 0.00% +system.ruby.l1_cntrl0.I.Store 191 0.00% 0.00% +system.ruby.l1_cntrl0.M.Load 305 0.00% 0.00% +system.ruby.l1_cntrl0.M.Ifetch 3467 0.00% 0.00% +system.ruby.l1_cntrl0.M.Store 51 0.00% 0.00% +system.ruby.l1_cntrl0.M.L1_Replacement 1086 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.Load 112 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.Ifetch 2287 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.Store 27 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.L1_Replacement 17 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.Use_Timeout 1143 0.00% 0.00% +system.ruby.l1_cntrl0.MM.Load 234 0.00% 0.00% +system.ruby.l1_cntrl0.MM.Store 339 0.00% 0.00% +system.ruby.l1_cntrl0.MM.L1_Replacement 268 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.Load 7 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.Store 257 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.L1_Replacement 8 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.Use_Timeout 218 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Exclusive_Data 191 0.00% 0.00% +system.ruby.l1_cntrl0.OM.All_acks 191 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Exclusive_Data 1171 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Writeback_Ack_Data 1354 0.00% 0.00% +system.ruby.dir_cntrl0.GETX 130 0.00% 0.00% +system.ruby.dir_cntrl0.GETS 979 0.00% 0.00% +system.ruby.dir_cntrl0.PUTX 1093 0.00% 0.00% +system.ruby.dir_cntrl0.Exclusive_Unblock 1109 0.00% 0.00% +system.ruby.dir_cntrl0.Clean_Writeback 899 0.00% 0.00% +system.ruby.dir_cntrl0.Dirty_Writeback 194 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 1109 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 194 0.00% 0.00% +system.ruby.dir_cntrl0.I.GETX 130 0.00% 0.00% +system.ruby.dir_cntrl0.I.GETS 979 0.00% 0.00% +system.ruby.dir_cntrl0.I.Memory_Ack 193 0.00% 0.00% +system.ruby.dir_cntrl0.M.PUTX 1093 0.00% 0.00% +system.ruby.dir_cntrl0.IS.Exclusive_Unblock 979 0.00% 0.00% +system.ruby.dir_cntrl0.IS.Memory_Data 979 0.00% 0.00% +system.ruby.dir_cntrl0.IS.Memory_Ack 1 0.00% 0.00% +system.ruby.dir_cntrl0.MM.Exclusive_Unblock 130 0.00% 0.00% +system.ruby.dir_cntrl0.MM.Memory_Data 130 0.00% 0.00% +system.ruby.dir_cntrl0.MI.Clean_Writeback 899 0.00% 0.00% +system.ruby.dir_cntrl0.MI.Dirty_Writeback 194 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats index 6541fb769..1ce3a3a21 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats @@ -1,26 +1,24 @@ -Real time: Mar/06/2013 20:46:06 +Real time: Jun/08/2013 14:14:35 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.61 -Virtual_time_in_minutes: 0.0101667 -Virtual_time_in_hours: 0.000169444 -Virtual_time_in_days: 7.06019e-06 +Virtual_time_in_seconds: 0.54 +Virtual_time_in_minutes: 0.009 +Virtual_time_in_hours: 0.00015 +Virtual_time_in_days: 6.25e-06 Ruby_current_time: 113627 Ruby_start_time: 0 Ruby_cycles: 113627 -mbytes_resident: 54.6523 -mbytes_total: 146.188 -resident_ratio: 0.373878 - -ruby_cycles_executed: [ 113628 ] +mbytes_resident: 55.1719 +mbytes_total: 142.258 +resident_ratio: 0.387885 Busy Controller Counts: L1Cache-0:0 @@ -69,7 +67,6 @@ Request vs. RubySystem State Profile -------------------------------- -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- @@ -90,10 +87,10 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10779 +page_reclaims: 11340 page_faults: 0 swaps: 0 -block_inputs: 0 +block_inputs: 16 block_outputs: 96 Network Stats @@ -160,805 +157,3 @@ links_utilized_percent_switch_3: 4.4341 outgoing_messages_switch_3_link_2_Writeback_Data: 229 16488 [ 0 0 0 0 229 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Writeback_Control: 967 7736 [ 0 0 0 0 967 0 0 0 0 0 ] base_latency: 1 - --- L1Cache --- - - Event Counts - -Load [1183 ] 1183 -Ifetch [6400 ] 6400 -Store [865 ] 865 -Atomic [0 ] 0 -L1_Replacement [1364 ] 1364 -Data_Shared [161 ] 161 -Data_Owner [0 ] 0 -Data_All_Tokens [1221 ] 1221 -Ack [1 ] 1 -Ack_All_Tokens [0 ] 0 -Transient_GETX [0 ] 0 -Transient_Local_GETX [0 ] 0 -Transient_GETS [0 ] 0 -Transient_Local_GETS [0 ] 0 -Transient_GETS_Last_Token [0 ] 0 -Transient_Local_GETS_Last_Token [0 ] 0 -Persistent_GETX [0 ] 0 -Persistent_GETS [0 ] 0 -Persistent_GETS_Last_Token [0 ] 0 -Own_Lock_or_Unlock [0 ] 0 -Request_Timeout [0 ] 0 -Use_TimeoutStarverX [0 ] 0 -Use_TimeoutStarverS [0 ] 0 -Use_TimeoutNoStarvers [1220 ] 1220 -Use_TimeoutNoStarvers_NoMig [0 ] 0 - - - Transitions - -NP Load [525 ] 525 -NP Ifetch [646 ] 646 -NP Store [191 ] 191 -NP Atomic [0 ] 0 -NP Data_Shared [0 ] 0 -NP Data_Owner [0 ] 0 -NP Data_All_Tokens [0 ] 0 -NP Ack [0 ] 0 -NP Transient_GETX [0 ] 0 -NP Transient_Local_GETX [0 ] 0 -NP Transient_GETS [0 ] 0 -NP Transient_Local_GETS [0 ] 0 -NP Persistent_GETX [0 ] 0 -NP Persistent_GETS [0 ] 0 -NP Persistent_GETS_Last_Token [0 ] 0 -NP Own_Lock_or_Unlock [0 ] 0 - -I Load [0 ] 0 -I Ifetch [0 ] 0 -I Store [0 ] 0 -I Atomic [0 ] 0 -I L1_Replacement [0 ] 0 -I Data_Shared [0 ] 0 -I Data_Owner [0 ] 0 -I Data_All_Tokens [0 ] 0 -I Ack [0 ] 0 -I Transient_GETX [0 ] 0 -I Transient_Local_GETX [0 ] 0 -I Transient_GETS [0 ] 0 -I Transient_Local_GETS [0 ] 0 -I Transient_GETS_Last_Token [0 ] 0 -I Transient_Local_GETS_Last_Token [0 ] 0 -I Persistent_GETX [0 ] 0 -I Persistent_GETS [0 ] 0 -I Persistent_GETS_Last_Token [0 ] 0 -I Own_Lock_or_Unlock [0 ] 0 - -S Load [153 ] 153 -S Ifetch [331 ] 331 -S Store [20 ] 20 -S Atomic [0 ] 0 -S L1_Replacement [141 ] 141 -S Data_Shared [0 ] 0 -S Data_Owner [0 ] 0 -S Data_All_Tokens [0 ] 0 -S Ack [0 ] 0 -S Transient_GETX [0 ] 0 -S Transient_Local_GETX [0 ] 0 -S Transient_GETS [0 ] 0 -S Transient_Local_GETS [0 ] 0 -S Transient_GETS_Last_Token [0 ] 0 -S Transient_Local_GETS_Last_Token [0 ] 0 -S Persistent_GETX [0 ] 0 -S Persistent_GETS [0 ] 0 -S Persistent_GETS_Last_Token [0 ] 0 -S Own_Lock_or_Unlock [0 ] 0 - -O Load [0 ] 0 -O Ifetch [0 ] 0 -O Store [0 ] 0 -O Atomic [0 ] 0 -O L1_Replacement [0 ] 0 -O Data_Shared [0 ] 0 -O Data_All_Tokens [0 ] 0 -O Ack [0 ] 0 -O Ack_All_Tokens [0 ] 0 -O Transient_GETX [0 ] 0 -O Transient_Local_GETX [0 ] 0 -O Transient_GETS [0 ] 0 -O Transient_Local_GETS [0 ] 0 -O Transient_GETS_Last_Token [0 ] 0 -O Transient_Local_GETS_Last_Token [0 ] 0 -O Persistent_GETX [0 ] 0 -O Persistent_GETS [0 ] 0 -O Persistent_GETS_Last_Token [0 ] 0 -O Own_Lock_or_Unlock [0 ] 0 - -M Load [184 ] 184 -M Ifetch [3308 ] 3308 -M Store [33 ] 33 -M Atomic [0 ] 0 -M L1_Replacement [945 ] 945 -M Transient_GETX [0 ] 0 -M Transient_Local_GETX [0 ] 0 -M Transient_GETS [0 ] 0 -M Transient_Local_GETS [0 ] 0 -M Persistent_GETX [0 ] 0 -M Persistent_GETS [0 ] 0 -M Own_Lock_or_Unlock [0 ] 0 - -MM Load [220 ] 220 -MM Ifetch [0 ] 0 -MM Store [330 ] 330 -MM Atomic [0 ] 0 -MM L1_Replacement [268 ] 268 -MM Transient_GETX [0 ] 0 -MM Transient_Local_GETX [0 ] 0 -MM Transient_GETS [0 ] 0 -MM Transient_Local_GETS [0 ] 0 -MM Persistent_GETX [0 ] 0 -MM Persistent_GETS [0 ] 0 -MM Own_Lock_or_Unlock [0 ] 0 - -M_W Load [80 ] 80 -M_W Ifetch [2115 ] 2115 -M_W Store [25 ] 25 -M_W Atomic [0 ] 0 -M_W L1_Replacement [6 ] 6 -M_W Transient_GETX [0 ] 0 -M_W Transient_Local_GETX [0 ] 0 -M_W Transient_GETS [0 ] 0 -M_W Transient_Local_GETS [0 ] 0 -M_W Persistent_GETX [0 ] 0 -M_W Persistent_GETS [0 ] 0 -M_W Own_Lock_or_Unlock [0 ] 0 -M_W Use_TimeoutStarverX [0 ] 0 -M_W Use_TimeoutStarverS [0 ] 0 -M_W Use_TimeoutNoStarvers [984 ] 984 -M_W Use_TimeoutNoStarvers_NoMig [0 ] 0 - -MM_W Load [21 ] 21 -MM_W Ifetch [0 ] 0 -MM_W Store [266 ] 266 -MM_W Atomic [0 ] 0 -MM_W L1_Replacement [4 ] 4 -MM_W Transient_GETX [0 ] 0 -MM_W Transient_Local_GETX [0 ] 0 -MM_W Transient_GETS [0 ] 0 -MM_W Transient_Local_GETS [0 ] 0 -MM_W Persistent_GETX [0 ] 0 -MM_W Persistent_GETS [0 ] 0 -MM_W Own_Lock_or_Unlock [0 ] 0 -MM_W Use_TimeoutStarverX [0 ] 0 -MM_W Use_TimeoutStarverS [0 ] 0 -MM_W Use_TimeoutNoStarvers [236 ] 236 -MM_W Use_TimeoutNoStarvers_NoMig [0 ] 0 - -IM Load [0 ] 0 -IM Ifetch [0 ] 0 -IM Store [0 ] 0 -IM Atomic [0 ] 0 -IM L1_Replacement [0 ] 0 -IM Data_Shared [0 ] 0 -IM Data_Owner [0 ] 0 -IM Data_All_Tokens [191 ] 191 -IM Ack [1 ] 1 -IM Transient_GETX [0 ] 0 -IM Transient_Local_GETX [0 ] 0 -IM Transient_GETS [0 ] 0 -IM Transient_Local_GETS [0 ] 0 -IM Transient_GETS_Last_Token [0 ] 0 -IM Transient_Local_GETS_Last_Token [0 ] 0 -IM Persistent_GETX [0 ] 0 -IM Persistent_GETS [0 ] 0 -IM Persistent_GETS_Last_Token [0 ] 0 -IM Own_Lock_or_Unlock [0 ] 0 -IM Request_Timeout [0 ] 0 - -SM Load [0 ] 0 -SM Ifetch [0 ] 0 -SM Store [0 ] 0 -SM Atomic [0 ] 0 -SM L1_Replacement [0 ] 0 -SM Data_Shared [0 ] 0 -SM Data_Owner [0 ] 0 -SM Data_All_Tokens [20 ] 20 -SM Ack [0 ] 0 -SM Transient_GETX [0 ] 0 -SM Transient_Local_GETX [0 ] 0 -SM Transient_GETS [0 ] 0 -SM Transient_Local_GETS [0 ] 0 -SM Transient_GETS_Last_Token [0 ] 0 -SM Transient_Local_GETS_Last_Token [0 ] 0 -SM Persistent_GETX [0 ] 0 -SM Persistent_GETS [0 ] 0 -SM Persistent_GETS_Last_Token [0 ] 0 -SM Own_Lock_or_Unlock [0 ] 0 -SM Request_Timeout [0 ] 0 - -OM Load [0 ] 0 -OM Ifetch [0 ] 0 -OM Store [0 ] 0 -OM Atomic [0 ] 0 -OM L1_Replacement [0 ] 0 -OM Data_Shared [0 ] 0 -OM Data_All_Tokens [0 ] 0 -OM Ack [0 ] 0 -OM Ack_All_Tokens [0 ] 0 -OM Transient_GETX [0 ] 0 -OM Transient_Local_GETX [0 ] 0 -OM Transient_GETS [0 ] 0 -OM Transient_Local_GETS [0 ] 0 -OM Transient_GETS_Last_Token [0 ] 0 -OM Transient_Local_GETS_Last_Token [0 ] 0 -OM Persistent_GETX [0 ] 0 -OM Persistent_GETS [0 ] 0 -OM Persistent_GETS_Last_Token [0 ] 0 -OM Own_Lock_or_Unlock [0 ] 0 -OM Request_Timeout [0 ] 0 - -IS Load [0 ] 0 -IS Ifetch [0 ] 0 -IS Store [0 ] 0 -IS Atomic [0 ] 0 -IS L1_Replacement [0 ] 0 -IS Data_Shared [161 ] 161 -IS Data_Owner [0 ] 0 -IS Data_All_Tokens [1010 ] 1010 -IS Ack [0 ] 0 -IS Transient_GETX [0 ] 0 -IS Transient_Local_GETX [0 ] 0 -IS Transient_GETS [0 ] 0 -IS Transient_Local_GETS [0 ] 0 -IS Transient_GETS_Last_Token [0 ] 0 -IS Transient_Local_GETS_Last_Token [0 ] 0 -IS Persistent_GETX [0 ] 0 -IS Persistent_GETS [0 ] 0 -IS Persistent_GETS_Last_Token [0 ] 0 -IS Own_Lock_or_Unlock [0 ] 0 -IS Request_Timeout [0 ] 0 - -I_L Load [0 ] 0 -I_L Ifetch [0 ] 0 -I_L Store [0 ] 0 -I_L Atomic [0 ] 0 -I_L L1_Replacement [0 ] 0 -I_L Data_Shared [0 ] 0 -I_L Data_Owner [0 ] 0 -I_L Data_All_Tokens [0 ] 0 -I_L Ack [0 ] 0 -I_L Transient_GETX [0 ] 0 -I_L Transient_Local_GETX [0 ] 0 -I_L Transient_GETS [0 ] 0 -I_L Transient_Local_GETS [0 ] 0 -I_L Transient_GETS_Last_Token [0 ] 0 -I_L Transient_Local_GETS_Last_Token [0 ] 0 -I_L Persistent_GETX [0 ] 0 -I_L Persistent_GETS [0 ] 0 -I_L Persistent_GETS_Last_Token [0 ] 0 -I_L Own_Lock_or_Unlock [0 ] 0 - -S_L Load [0 ] 0 -S_L Ifetch [0 ] 0 -S_L Store [0 ] 0 -S_L Atomic [0 ] 0 -S_L L1_Replacement [0 ] 0 -S_L Data_Shared [0 ] 0 -S_L Data_Owner [0 ] 0 -S_L Data_All_Tokens [0 ] 0 -S_L Ack [0 ] 0 -S_L Transient_GETX [0 ] 0 -S_L Transient_Local_GETX [0 ] 0 -S_L Transient_GETS [0 ] 0 -S_L Transient_Local_GETS [0 ] 0 -S_L Transient_GETS_Last_Token [0 ] 0 -S_L Transient_Local_GETS_Last_Token [0 ] 0 -S_L Persistent_GETX [0 ] 0 -S_L Persistent_GETS [0 ] 0 -S_L Persistent_GETS_Last_Token [0 ] 0 -S_L Own_Lock_or_Unlock [0 ] 0 - -IM_L Load [0 ] 0 -IM_L Ifetch [0 ] 0 -IM_L Store [0 ] 0 -IM_L Atomic [0 ] 0 -IM_L L1_Replacement [0 ] 0 -IM_L Data_Shared [0 ] 0 -IM_L Data_Owner [0 ] 0 -IM_L Data_All_Tokens [0 ] 0 -IM_L Ack [0 ] 0 -IM_L Transient_GETX [0 ] 0 -IM_L Transient_Local_GETX [0 ] 0 -IM_L Transient_GETS [0 ] 0 -IM_L Transient_Local_GETS [0 ] 0 -IM_L Transient_GETS_Last_Token [0 ] 0 -IM_L Transient_Local_GETS_Last_Token [0 ] 0 -IM_L Persistent_GETX [0 ] 0 -IM_L Persistent_GETS [0 ] 0 -IM_L Own_Lock_or_Unlock [0 ] 0 -IM_L Request_Timeout [0 ] 0 - -SM_L Load [0 ] 0 -SM_L Ifetch [0 ] 0 -SM_L Store [0 ] 0 -SM_L Atomic [0 ] 0 -SM_L L1_Replacement [0 ] 0 -SM_L Data_Shared [0 ] 0 -SM_L Data_Owner [0 ] 0 -SM_L Data_All_Tokens [0 ] 0 -SM_L Ack [0 ] 0 -SM_L Transient_GETX [0 ] 0 -SM_L Transient_Local_GETX [0 ] 0 -SM_L Transient_GETS [0 ] 0 -SM_L Transient_Local_GETS [0 ] 0 -SM_L Transient_GETS_Last_Token [0 ] 0 -SM_L Transient_Local_GETS_Last_Token [0 ] 0 -SM_L Persistent_GETX [0 ] 0 -SM_L Persistent_GETS [0 ] 0 -SM_L Persistent_GETS_Last_Token [0 ] 0 -SM_L Own_Lock_or_Unlock [0 ] 0 -SM_L Request_Timeout [0 ] 0 - -IS_L Load [0 ] 0 -IS_L Ifetch [0 ] 0 -IS_L Store [0 ] 0 -IS_L Atomic [0 ] 0 -IS_L L1_Replacement [0 ] 0 -IS_L Data_Shared [0 ] 0 -IS_L Data_Owner [0 ] 0 -IS_L Data_All_Tokens [0 ] 0 -IS_L Ack [0 ] 0 -IS_L Transient_GETX [0 ] 0 -IS_L Transient_Local_GETX [0 ] 0 -IS_L Transient_GETS [0 ] 0 -IS_L Transient_Local_GETS [0 ] 0 -IS_L Transient_GETS_Last_Token [0 ] 0 -IS_L Transient_Local_GETS_Last_Token [0 ] 0 -IS_L Persistent_GETX [0 ] 0 -IS_L Persistent_GETS [0 ] 0 -IS_L Own_Lock_or_Unlock [0 ] 0 -IS_L Request_Timeout [0 ] 0 - - --- L2Cache --- - - Event Counts - -L1_GETS [1122 ] 1122 -L1_GETS_Last_Token [49 ] 49 -L1_GETX [211 ] 211 -L1_INV [0 ] 0 -Transient_GETX [0 ] 0 -Transient_GETS [0 ] 0 -Transient_GETS_Last_Token [0 ] 0 -L2_Replacement [1265 ] 1265 -Writeback_Tokens [0 ] 0 -Writeback_Shared_Data [84 ] 84 -Writeback_All_Tokens [1270 ] 1270 -Writeback_Owned [0 ] 0 -Data_Shared [0 ] 0 -Data_Owner [0 ] 0 -Data_All_Tokens [0 ] 0 -Ack [0 ] 0 -Ack_All_Tokens [0 ] 0 -Persistent_GETX [0 ] 0 -Persistent_GETS [0 ] 0 -Persistent_GETS_Last_Token [0 ] 0 -Own_Lock_or_Unlock [0 ] 0 - - - Transitions - -NP L1_GETS [1010 ] 1010 -NP L1_GETX [166 ] 166 -NP L1_INV [0 ] 0 -NP Transient_GETX [0 ] 0 -NP Transient_GETS [0 ] 0 -NP Writeback_Tokens [0 ] 0 -NP Writeback_Shared_Data [81 ] 81 -NP Writeback_All_Tokens [1192 ] 1192 -NP Writeback_Owned [0 ] 0 -NP Data_Shared [0 ] 0 -NP Data_Owner [0 ] 0 -NP Data_All_Tokens [0 ] 0 -NP Ack [0 ] 0 -NP Persistent_GETX [0 ] 0 -NP Persistent_GETS [0 ] 0 -NP Persistent_GETS_Last_Token [0 ] 0 -NP Own_Lock_or_Unlock [0 ] 0 - -I L1_GETS [0 ] 0 -I L1_GETS_Last_Token [0 ] 0 -I L1_GETX [1 ] 1 -I L1_INV [0 ] 0 -I Transient_GETX [0 ] 0 -I Transient_GETS [0 ] 0 -I Transient_GETS_Last_Token [0 ] 0 -I L2_Replacement [69 ] 69 -I Writeback_Tokens [0 ] 0 -I Writeback_Shared_Data [3 ] 3 -I Writeback_All_Tokens [21 ] 21 -I Writeback_Owned [0 ] 0 -I Data_Shared [0 ] 0 -I Data_Owner [0 ] 0 -I Data_All_Tokens [0 ] 0 -I Ack [0 ] 0 -I Persistent_GETX [0 ] 0 -I Persistent_GETS [0 ] 0 -I Persistent_GETS_Last_Token [0 ] 0 -I Own_Lock_or_Unlock [0 ] 0 - -S L1_GETS [0 ] 0 -S L1_GETS_Last_Token [49 ] 49 -S L1_GETX [1 ] 1 -S L1_INV [0 ] 0 -S Transient_GETX [0 ] 0 -S Transient_GETS [0 ] 0 -S Transient_GETS_Last_Token [0 ] 0 -S L2_Replacement [34 ] 34 -S Writeback_Tokens [0 ] 0 -S Writeback_Shared_Data [0 ] 0 -S Writeback_All_Tokens [0 ] 0 -S Writeback_Owned [0 ] 0 -S Data_Shared [0 ] 0 -S Data_Owner [0 ] 0 -S Data_All_Tokens [0 ] 0 -S Ack [0 ] 0 -S Persistent_GETX [0 ] 0 -S Persistent_GETS [0 ] 0 -S Persistent_GETS_Last_Token [0 ] 0 -S Own_Lock_or_Unlock [0 ] 0 - -O L1_GETS [0 ] 0 -O L1_GETS_Last_Token [0 ] 0 -O L1_GETX [17 ] 17 -O L1_INV [0 ] 0 -O Transient_GETX [0 ] 0 -O Transient_GETS [0 ] 0 -O Transient_GETS_Last_Token [0 ] 0 -O L2_Replacement [38 ] 38 -O Writeback_Tokens [0 ] 0 -O Writeback_Shared_Data [0 ] 0 -O Writeback_All_Tokens [57 ] 57 -O Data_Shared [0 ] 0 -O Data_All_Tokens [0 ] 0 -O Ack [0 ] 0 -O Ack_All_Tokens [0 ] 0 -O Persistent_GETX [0 ] 0 -O Persistent_GETS [0 ] 0 -O Persistent_GETS_Last_Token [0 ] 0 -O Own_Lock_or_Unlock [0 ] 0 - -M L1_GETS [112 ] 112 -M L1_GETX [26 ] 26 -M L1_INV [0 ] 0 -M Transient_GETX [0 ] 0 -M Transient_GETS [0 ] 0 -M L2_Replacement [1124 ] 1124 -M Persistent_GETX [0 ] 0 -M Persistent_GETS [0 ] 0 -M Own_Lock_or_Unlock [0 ] 0 - -I_L L1_GETS [0 ] 0 -I_L L1_GETX [0 ] 0 -I_L L1_INV [0 ] 0 -I_L Transient_GETX [0 ] 0 -I_L Transient_GETS [0 ] 0 -I_L Transient_GETS_Last_Token [0 ] 0 -I_L L2_Replacement [0 ] 0 -I_L Writeback_Tokens [0 ] 0 -I_L Writeback_Shared_Data [0 ] 0 -I_L Writeback_All_Tokens [0 ] 0 -I_L Writeback_Owned [0 ] 0 -I_L Data_Shared [0 ] 0 -I_L Data_Owner [0 ] 0 -I_L Data_All_Tokens [0 ] 0 -I_L Ack [0 ] 0 -I_L Persistent_GETX [0 ] 0 -I_L Persistent_GETS [0 ] 0 -I_L Own_Lock_or_Unlock [0 ] 0 - -S_L L1_GETS [0 ] 0 -S_L L1_GETS_Last_Token [0 ] 0 -S_L L1_GETX [0 ] 0 -S_L L1_INV [0 ] 0 -S_L Transient_GETX [0 ] 0 -S_L Transient_GETS [0 ] 0 -S_L Transient_GETS_Last_Token [0 ] 0 -S_L L2_Replacement [0 ] 0 -S_L Writeback_Tokens [0 ] 0 -S_L Writeback_Shared_Data [0 ] 0 -S_L Writeback_All_Tokens [0 ] 0 -S_L Writeback_Owned [0 ] 0 -S_L Data_Shared [0 ] 0 -S_L Data_Owner [0 ] 0 -S_L Data_All_Tokens [0 ] 0 -S_L Ack [0 ] 0 -S_L Persistent_GETX [0 ] 0 -S_L Persistent_GETS [0 ] 0 -S_L Persistent_GETS_Last_Token [0 ] 0 -S_L Own_Lock_or_Unlock [0 ] 0 - -Memory controller: system.ruby.dir_cntrl0.memBuffer: - memory_total_requests: 1407 - memory_reads: 1178 - memory_writes: 229 - memory_refreshes: 789 - memory_total_request_delays: 323 - memory_delays_per_request: 0.229566 - memory_delays_in_input_queue: 0 - memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 323 - memory_stalls_for_bank_busy: 81 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 19 - memory_stalls_for_bus: 213 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 10 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 75 17 45 41 54 102 33 16 20 22 32 34 53 50 40 31 40 21 21 21 28 38 89 22 31 23 32 72 95 141 15 53 - - --- Directory --- - - Event Counts - -GETX [278 ] 278 -GETS [1034 ] 1034 -Lockdown [0 ] 0 -Unlockdown [0 ] 0 -Own_Lock_or_Unlock [0 ] 0 -Own_Lock_or_Unlock_Tokens [0 ] 0 -Data_Owner [9 ] 9 -Data_All_Tokens [220 ] 220 -Ack_Owner [29 ] 29 -Ack_Owner_All_Tokens [904 ] 904 -Tokens [0 ] 0 -Ack_All_Tokens [34 ] 34 -Request_Timeout [0 ] 0 -Memory_Data [1178 ] 1178 -Memory_Ack [229 ] 229 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -DMA_WRITE_All_Tokens [0 ] 0 - - - Transitions - -O GETX [168 ] 168 -O GETS [1010 ] 1010 -O Lockdown [0 ] 0 -O Unlockdown [0 ] 0 -O Own_Lock_or_Unlock [0 ] 0 -O Own_Lock_or_Unlock_Tokens [0 ] 0 -O Data_Owner [0 ] 0 -O Data_All_Tokens [0 ] 0 -O Tokens [0 ] 0 -O Ack_All_Tokens [34 ] 34 -O DMA_READ [0 ] 0 -O DMA_WRITE [0 ] 0 -O DMA_WRITE_All_Tokens [0 ] 0 - -NO GETX [17 ] 17 -NO GETS [0 ] 0 -NO Lockdown [0 ] 0 -NO Unlockdown [0 ] 0 -NO Own_Lock_or_Unlock [0 ] 0 -NO Own_Lock_or_Unlock_Tokens [0 ] 0 -NO Data_Owner [9 ] 9 -NO Data_All_Tokens [220 ] 220 -NO Ack_Owner [29 ] 29 -NO Ack_Owner_All_Tokens [904 ] 904 -NO Tokens [0 ] 0 -NO DMA_READ [0 ] 0 -NO DMA_WRITE [0 ] 0 - -L GETX [0 ] 0 -L GETS [0 ] 0 -L Lockdown [0 ] 0 -L Unlockdown [0 ] 0 -L Own_Lock_or_Unlock [0 ] 0 -L Own_Lock_or_Unlock_Tokens [0 ] 0 -L Data_Owner [0 ] 0 -L Data_All_Tokens [0 ] 0 -L Ack_Owner [0 ] 0 -L Ack_Owner_All_Tokens [0 ] 0 -L Tokens [0 ] 0 -L DMA_READ [0 ] 0 -L DMA_WRITE [0 ] 0 -L DMA_WRITE_All_Tokens [0 ] 0 - -O_W GETX [93 ] 93 -O_W GETS [24 ] 24 -O_W Lockdown [0 ] 0 -O_W Unlockdown [0 ] 0 -O_W Own_Lock_or_Unlock [0 ] 0 -O_W Own_Lock_or_Unlock_Tokens [0 ] 0 -O_W Data_Owner [0 ] 0 -O_W Data_All_Tokens [0 ] 0 -O_W Ack_Owner [0 ] 0 -O_W Tokens [0 ] 0 -O_W Ack_All_Tokens [0 ] 0 -O_W Memory_Data [0 ] 0 -O_W Memory_Ack [229 ] 229 -O_W DMA_READ [0 ] 0 -O_W DMA_WRITE [0 ] 0 -O_W DMA_WRITE_All_Tokens [0 ] 0 - -L_O_W GETX [0 ] 0 -L_O_W GETS [0 ] 0 -L_O_W Lockdown [0 ] 0 -L_O_W Unlockdown [0 ] 0 -L_O_W Own_Lock_or_Unlock [0 ] 0 -L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0 -L_O_W Data_Owner [0 ] 0 -L_O_W Data_All_Tokens [0 ] 0 -L_O_W Ack_Owner [0 ] 0 -L_O_W Tokens [0 ] 0 -L_O_W Ack_All_Tokens [0 ] 0 -L_O_W Memory_Data [0 ] 0 -L_O_W Memory_Ack [0 ] 0 -L_O_W DMA_READ [0 ] 0 -L_O_W DMA_WRITE [0 ] 0 -L_O_W DMA_WRITE_All_Tokens [0 ] 0 - -L_NO_W GETX [0 ] 0 -L_NO_W GETS [0 ] 0 -L_NO_W Lockdown [0 ] 0 -L_NO_W Unlockdown [0 ] 0 -L_NO_W Own_Lock_or_Unlock [0 ] 0 -L_NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 -L_NO_W Data_Owner [0 ] 0 -L_NO_W Data_All_Tokens [0 ] 0 -L_NO_W Ack_Owner [0 ] 0 -L_NO_W Tokens [0 ] 0 -L_NO_W Ack_All_Tokens [0 ] 0 -L_NO_W Memory_Data [0 ] 0 -L_NO_W DMA_READ [0 ] 0 -L_NO_W DMA_WRITE [0 ] 0 -L_NO_W DMA_WRITE_All_Tokens [0 ] 0 - -DR_L_W GETX [0 ] 0 -DR_L_W GETS [0 ] 0 -DR_L_W Lockdown [0 ] 0 -DR_L_W Unlockdown [0 ] 0 -DR_L_W Own_Lock_or_Unlock [0 ] 0 -DR_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 -DR_L_W Data_Owner [0 ] 0 -DR_L_W Data_All_Tokens [0 ] 0 -DR_L_W Ack_Owner [0 ] 0 -DR_L_W Tokens [0 ] 0 -DR_L_W Ack_All_Tokens [0 ] 0 -DR_L_W Request_Timeout [0 ] 0 -DR_L_W Memory_Data [0 ] 0 -DR_L_W DMA_READ [0 ] 0 -DR_L_W DMA_WRITE [0 ] 0 -DR_L_W DMA_WRITE_All_Tokens [0 ] 0 - -DW_L_W GETX [0 ] 0 -DW_L_W GETS [0 ] 0 -DW_L_W Lockdown [0 ] 0 -DW_L_W Unlockdown [0 ] 0 -DW_L_W Own_Lock_or_Unlock [0 ] 0 -DW_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 -DW_L_W Data_Owner [0 ] 0 -DW_L_W Data_All_Tokens [0 ] 0 -DW_L_W Ack_Owner [0 ] 0 -DW_L_W Tokens [0 ] 0 -DW_L_W Ack_All_Tokens [0 ] 0 -DW_L_W Request_Timeout [0 ] 0 -DW_L_W Memory_Ack [0 ] 0 -DW_L_W DMA_READ [0 ] 0 -DW_L_W DMA_WRITE [0 ] 0 -DW_L_W DMA_WRITE_All_Tokens [0 ] 0 - -NO_W GETX [0 ] 0 -NO_W GETS [0 ] 0 -NO_W Lockdown [0 ] 0 -NO_W Unlockdown [0 ] 0 -NO_W Own_Lock_or_Unlock [0 ] 0 -NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 -NO_W Data_Owner [0 ] 0 -NO_W Data_All_Tokens [0 ] 0 -NO_W Ack_Owner [0 ] 0 -NO_W Tokens [0 ] 0 -NO_W Ack_All_Tokens [0 ] 0 -NO_W Memory_Data [1178 ] 1178 -NO_W DMA_READ [0 ] 0 -NO_W DMA_WRITE [0 ] 0 -NO_W DMA_WRITE_All_Tokens [0 ] 0 - -O_DW_W GETX [0 ] 0 -O_DW_W GETS [0 ] 0 -O_DW_W Lockdown [0 ] 0 -O_DW_W Unlockdown [0 ] 0 -O_DW_W Own_Lock_or_Unlock [0 ] 0 -O_DW_W Own_Lock_or_Unlock_Tokens [0 ] 0 -O_DW_W Data_Owner [0 ] 0 -O_DW_W Data_All_Tokens [0 ] 0 -O_DW_W Ack_Owner [0 ] 0 -O_DW_W Tokens [0 ] 0 -O_DW_W Ack_All_Tokens [0 ] 0 -O_DW_W Request_Timeout [0 ] 0 -O_DW_W Memory_Ack [0 ] 0 -O_DW_W DMA_READ [0 ] 0 -O_DW_W DMA_WRITE [0 ] 0 -O_DW_W DMA_WRITE_All_Tokens [0 ] 0 - -O_DR_W GETX [0 ] 0 -O_DR_W GETS [0 ] 0 -O_DR_W Lockdown [0 ] 0 -O_DR_W Unlockdown [0 ] 0 -O_DR_W Own_Lock_or_Unlock [0 ] 0 -O_DR_W Own_Lock_or_Unlock_Tokens [0 ] 0 -O_DR_W Data_Owner [0 ] 0 -O_DR_W Data_All_Tokens [0 ] 0 -O_DR_W Ack_Owner [0 ] 0 -O_DR_W Tokens [0 ] 0 -O_DR_W Ack_All_Tokens [0 ] 0 -O_DR_W Request_Timeout [0 ] 0 -O_DR_W Memory_Data [0 ] 0 -O_DR_W DMA_READ [0 ] 0 -O_DR_W DMA_WRITE [0 ] 0 -O_DR_W DMA_WRITE_All_Tokens [0 ] 0 - -O_DW GETX [0 ] 0 -O_DW GETS [0 ] 0 -O_DW Lockdown [0 ] 0 -O_DW Unlockdown [0 ] 0 -O_DW Own_Lock_or_Unlock [0 ] 0 -O_DW Own_Lock_or_Unlock_Tokens [0 ] 0 -O_DW Data_Owner [0 ] 0 -O_DW Data_All_Tokens [0 ] 0 -O_DW Ack_Owner [0 ] 0 -O_DW Ack_Owner_All_Tokens [0 ] 0 -O_DW Tokens [0 ] 0 -O_DW Ack_All_Tokens [0 ] 0 -O_DW Request_Timeout [0 ] 0 -O_DW DMA_READ [0 ] 0 -O_DW DMA_WRITE [0 ] 0 -O_DW DMA_WRITE_All_Tokens [0 ] 0 - -NO_DW GETX [0 ] 0 -NO_DW GETS [0 ] 0 -NO_DW Lockdown [0 ] 0 -NO_DW Unlockdown [0 ] 0 -NO_DW Own_Lock_or_Unlock [0 ] 0 -NO_DW Own_Lock_or_Unlock_Tokens [0 ] 0 -NO_DW Data_Owner [0 ] 0 -NO_DW Data_All_Tokens [0 ] 0 -NO_DW Tokens [0 ] 0 -NO_DW Request_Timeout [0 ] 0 -NO_DW DMA_READ [0 ] 0 -NO_DW DMA_WRITE [0 ] 0 -NO_DW DMA_WRITE_All_Tokens [0 ] 0 - -NO_DR GETX [0 ] 0 -NO_DR GETS [0 ] 0 -NO_DR Lockdown [0 ] 0 -NO_DR Unlockdown [0 ] 0 -NO_DR Own_Lock_or_Unlock [0 ] 0 -NO_DR Own_Lock_or_Unlock_Tokens [0 ] 0 -NO_DR Data_Owner [0 ] 0 -NO_DR Data_All_Tokens [0 ] 0 -NO_DR Tokens [0 ] 0 -NO_DR Request_Timeout [0 ] 0 -NO_DR DMA_READ [0 ] 0 -NO_DR DMA_WRITE [0 ] 0 -NO_DR DMA_WRITE_All_Tokens [0 ] 0 - -DW_L GETX [0 ] 0 -DW_L GETS [0 ] 0 -DW_L Lockdown [0 ] 0 -DW_L Unlockdown [0 ] 0 -DW_L Own_Lock_or_Unlock [0 ] 0 -DW_L Own_Lock_or_Unlock_Tokens [0 ] 0 -DW_L Data_Owner [0 ] 0 -DW_L Data_All_Tokens [0 ] 0 -DW_L Ack_Owner [0 ] 0 -DW_L Ack_Owner_All_Tokens [0 ] 0 -DW_L Tokens [0 ] 0 -DW_L Request_Timeout [0 ] 0 -DW_L DMA_READ [0 ] 0 -DW_L DMA_WRITE [0 ] 0 -DW_L DMA_WRITE_All_Tokens [0 ] 0 - -DR_L GETX [0 ] 0 -DR_L GETS [0 ] 0 -DR_L Lockdown [0 ] 0 -DR_L Unlockdown [0 ] 0 -DR_L Own_Lock_or_Unlock [0 ] 0 -DR_L Own_Lock_or_Unlock_Tokens [0 ] 0 -DR_L Data_Owner [0 ] 0 -DR_L Data_All_Tokens [0 ] 0 -DR_L Ack_Owner [0 ] 0 -DR_L Ack_Owner_All_Tokens [0 ] 0 -DR_L Tokens [0 ] 0 -DR_L Request_Timeout [0 ] 0 -DR_L DMA_READ [0 ] 0 -DR_L DMA_WRITE [0 ] 0 -DR_L DMA_WRITE_All_Tokens [0 ] 0 - diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index 959a1bade..a5ba013e9 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000114 # Nu sim_ticks 113627 # Number of ticks simulated final_tick 113627 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 26434 # Simulator instruction rate (inst/s) -host_op_rate 26432 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 469977 # Simulator tick rate (ticks/s) -host_mem_usage 153588 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host +host_inst_rate 34924 # Simulator instruction rate (inst/s) +host_op_rate 34920 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 620890 # Simulator tick rate (ticks/s) +host_mem_usage 145676 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.ruby.l2_cntrl0.L2cache.demand_hits 187 # Number of cache demand hits @@ -20,6 +20,20 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses +system.ruby.dir_cntrl0.memBuffer.memReq 1407 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 1178 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 229 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 789 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 323 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 323 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.229566 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 81 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 213 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 10 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 19 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 75 5.33% 5.33% | 17 1.21% 6.54% | 45 3.20% 9.74% | 41 2.91% 12.65% | 54 3.84% 16.49% | 102 7.25% 23.74% | 33 2.35% 26.08% | 16 1.14% 27.22% | 20 1.42% 28.64% | 22 1.56% 30.21% | 32 2.27% 32.48% | 34 2.42% 34.90% | 53 3.77% 38.66% | 50 3.55% 42.22% | 40 2.84% 45.06% | 31 2.20% 47.26% | 40 2.84% 50.11% | 21 1.49% 51.60% | 21 1.49% 53.09% | 21 1.49% 54.58% | 28 1.99% 56.57% | 38 2.70% 59.28% | 89 6.33% 65.60% | 22 1.56% 67.16% | 31 2.20% 69.37% | 23 1.63% 71.00% | 32 2.27% 73.28% | 72 5.12% 78.39% | 95 6.75% 85.15% | 141 10.02% 95.17% | 15 1.07% 96.23% | 53 3.77% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1407 # Number of accesses per bank + system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -75,5 +89,85 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 113627 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles +system.ruby.l2_cntrl0.L1_GETS 1122 0.00% 0.00% +system.ruby.l2_cntrl0.L1_GETS_Last_Token 49 0.00% 0.00% +system.ruby.l2_cntrl0.L1_GETX 211 0.00% 0.00% +system.ruby.l2_cntrl0.L2_Replacement 1265 0.00% 0.00% +system.ruby.l2_cntrl0.Writeback_Shared_Data 84 0.00% 0.00% +system.ruby.l2_cntrl0.Writeback_All_Tokens 1270 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETS 1010 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETX 166 0.00% 0.00% +system.ruby.l2_cntrl0.NP.Writeback_Shared_Data 81 0.00% 0.00% +system.ruby.l2_cntrl0.NP.Writeback_All_Tokens 1192 0.00% 0.00% +system.ruby.l2_cntrl0.I.L1_GETX 1 0.00% 0.00% +system.ruby.l2_cntrl0.I.L2_Replacement 69 0.00% 0.00% +system.ruby.l2_cntrl0.I.Writeback_Shared_Data 3 0.00% 0.00% +system.ruby.l2_cntrl0.I.Writeback_All_Tokens 21 0.00% 0.00% +system.ruby.l2_cntrl0.S.L1_GETS_Last_Token 49 0.00% 0.00% +system.ruby.l2_cntrl0.S.L1_GETX 1 0.00% 0.00% +system.ruby.l2_cntrl0.S.L2_Replacement 34 0.00% 0.00% +system.ruby.l2_cntrl0.O.L1_GETX 17 0.00% 0.00% +system.ruby.l2_cntrl0.O.L2_Replacement 38 0.00% 0.00% +system.ruby.l2_cntrl0.O.Writeback_All_Tokens 57 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETS 112 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETX 26 0.00% 0.00% +system.ruby.l2_cntrl0.M.L2_Replacement 1124 0.00% 0.00% +system.ruby.l1_cntrl0.Load 1183 0.00% 0.00% +system.ruby.l1_cntrl0.Ifetch 6400 0.00% 0.00% +system.ruby.l1_cntrl0.Store 865 0.00% 0.00% +system.ruby.l1_cntrl0.L1_Replacement 1364 0.00% 0.00% +system.ruby.l1_cntrl0.Data_Shared 161 0.00% 0.00% +system.ruby.l1_cntrl0.Data_All_Tokens 1221 0.00% 0.00% +system.ruby.l1_cntrl0.Ack 1 0.00% 0.00% +system.ruby.l1_cntrl0.Use_TimeoutNoStarvers 1220 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Load 525 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Ifetch 646 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Store 191 0.00% 0.00% +system.ruby.l1_cntrl0.S.Load 153 0.00% 0.00% +system.ruby.l1_cntrl0.S.Ifetch 331 0.00% 0.00% +system.ruby.l1_cntrl0.S.Store 20 0.00% 0.00% +system.ruby.l1_cntrl0.S.L1_Replacement 141 0.00% 0.00% +system.ruby.l1_cntrl0.M.Load 184 0.00% 0.00% +system.ruby.l1_cntrl0.M.Ifetch 3308 0.00% 0.00% +system.ruby.l1_cntrl0.M.Store 33 0.00% 0.00% +system.ruby.l1_cntrl0.M.L1_Replacement 945 0.00% 0.00% +system.ruby.l1_cntrl0.MM.Load 220 0.00% 0.00% +system.ruby.l1_cntrl0.MM.Store 330 0.00% 0.00% +system.ruby.l1_cntrl0.MM.L1_Replacement 268 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.Load 80 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.Ifetch 2115 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.Store 25 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.L1_Replacement 6 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.Use_TimeoutNoStarvers 984 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.Load 21 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.Store 266 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.L1_Replacement 4 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.Use_TimeoutNoStarvers 236 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Data_All_Tokens 191 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Ack 1 0.00% 0.00% +system.ruby.l1_cntrl0.SM.Data_All_Tokens 20 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data_Shared 161 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data_All_Tokens 1010 0.00% 0.00% +system.ruby.dir_cntrl0.GETX 278 0.00% 0.00% +system.ruby.dir_cntrl0.GETS 1034 0.00% 0.00% +system.ruby.dir_cntrl0.Data_Owner 9 0.00% 0.00% +system.ruby.dir_cntrl0.Data_All_Tokens 220 0.00% 0.00% +system.ruby.dir_cntrl0.Ack_Owner 29 0.00% 0.00% +system.ruby.dir_cntrl0.Ack_Owner_All_Tokens 904 0.00% 0.00% +system.ruby.dir_cntrl0.Ack_All_Tokens 34 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 1178 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 229 0.00% 0.00% +system.ruby.dir_cntrl0.O.GETX 168 0.00% 0.00% +system.ruby.dir_cntrl0.O.GETS 1010 0.00% 0.00% +system.ruby.dir_cntrl0.O.Ack_All_Tokens 34 0.00% 0.00% +system.ruby.dir_cntrl0.NO.GETX 17 0.00% 0.00% +system.ruby.dir_cntrl0.NO.Data_Owner 9 0.00% 0.00% +system.ruby.dir_cntrl0.NO.Data_All_Tokens 220 0.00% 0.00% +system.ruby.dir_cntrl0.NO.Ack_Owner 29 0.00% 0.00% +system.ruby.dir_cntrl0.NO.Ack_Owner_All_Tokens 904 0.00% 0.00% +system.ruby.dir_cntrl0.O_W.GETX 93 0.00% 0.00% +system.ruby.dir_cntrl0.O_W.GETS 24 0.00% 0.00% +system.ruby.dir_cntrl0.O_W.Memory_Ack 229 0.00% 0.00% +system.ruby.dir_cntrl0.NO_W.Memory_Data 1178 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats index ecbf01672..3467aff26 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats @@ -1,26 +1,24 @@ -Real time: Mar/06/2013 20:34:50 +Real time: Jun/08/2013 13:27:45 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.61 -Virtual_time_in_minutes: 0.0101667 -Virtual_time_in_hours: 0.000169444 -Virtual_time_in_days: 7.06019e-06 +Virtual_time_in_seconds: 0.51 +Virtual_time_in_minutes: 0.0085 +Virtual_time_in_hours: 0.000141667 +Virtual_time_in_days: 5.90278e-06 Ruby_current_time: 93341 Ruby_start_time: 0 Ruby_cycles: 93341 -mbytes_resident: 53.8438 -mbytes_total: 146.117 -resident_ratio: 0.36855 - -ruby_cycles_executed: [ 93342 ] +mbytes_resident: 55.2734 +mbytes_total: 143.172 +resident_ratio: 0.386118 Busy Controller Counts: L1Cache-0:0 @@ -68,7 +66,6 @@ Request vs. RubySystem State Profile -------------------------------- -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- @@ -89,10 +86,10 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11071 -page_faults: 0 +page_reclaims: 15392 +page_faults: 3 swaps: 0 -block_inputs: 24 +block_inputs: 2160 block_outputs: 88 Network Stats @@ -144,749 +141,3 @@ links_utilized_percent_switch_2: 4.80443 outgoing_messages_switch_2_link_1_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1 - --- L1Cache --- - - Event Counts - -Load [1191 ] 1191 -Ifetch [6411 ] 6411 -Store [892 ] 892 -L2_Replacement [1143 ] 1143 -L1_to_L2 [1354 ] 1354 -Trigger_L2_to_L1D [138 ] 138 -Trigger_L2_to_L1I [65 ] 65 -Complete_L2_to_L1 [203 ] 203 -Other_GETX [0 ] 0 -Other_GETS [0 ] 0 -Merged_GETS [0 ] 0 -Other_GETS_No_Mig [0 ] 0 -NC_DMA_GETS [0 ] 0 -Invalidate [0 ] 0 -Ack [0 ] 0 -Shared_Ack [0 ] 0 -Data [0 ] 0 -Shared_Data [0 ] 0 -Exclusive_Data [1159 ] 1159 -Writeback_Ack [1143 ] 1143 -Writeback_Nack [0 ] 0 -All_acks [0 ] 0 -All_acks_no_sharers [1159 ] 1159 -Flush_line [0 ] 0 -Block_Ack [0 ] 0 - - - Transitions - -I Load [420 ] 420 -I Ifetch [581 ] 581 -I Store [158 ] 158 -I L2_Replacement [0 ] 0 -I L1_to_L2 [0 ] 0 -I Trigger_L2_to_L1D [0 ] 0 -I Trigger_L2_to_L1I [0 ] 0 -I Other_GETX [0 ] 0 -I Other_GETS [0 ] 0 -I Other_GETS_No_Mig [0 ] 0 -I NC_DMA_GETS [0 ] 0 -I Invalidate [0 ] 0 -I Flush_line [0 ] 0 - -S Load [0 ] 0 -S Ifetch [0 ] 0 -S Store [0 ] 0 -S L2_Replacement [0 ] 0 -S L1_to_L2 [0 ] 0 -S Trigger_L2_to_L1D [0 ] 0 -S Trigger_L2_to_L1I [0 ] 0 -S Other_GETX [0 ] 0 -S Other_GETS [0 ] 0 -S Other_GETS_No_Mig [0 ] 0 -S NC_DMA_GETS [0 ] 0 -S Invalidate [0 ] 0 -S Flush_line [0 ] 0 - -O Load [0 ] 0 -O Ifetch [0 ] 0 -O Store [0 ] 0 -O L2_Replacement [0 ] 0 -O L1_to_L2 [0 ] 0 -O Trigger_L2_to_L1D [0 ] 0 -O Trigger_L2_to_L1I [0 ] 0 -O Other_GETX [0 ] 0 -O Other_GETS [0 ] 0 -O Merged_GETS [0 ] 0 -O Other_GETS_No_Mig [0 ] 0 -O NC_DMA_GETS [0 ] 0 -O Invalidate [0 ] 0 -O Flush_line [0 ] 0 - -M Load [304 ] 304 -M Ifetch [5754 ] 5754 -M Store [60 ] 60 -M L2_Replacement [923 ] 923 -M L1_to_L2 [1061 ] 1061 -M Trigger_L2_to_L1D [68 ] 68 -M Trigger_L2_to_L1I [65 ] 65 -M Other_GETX [0 ] 0 -M Other_GETS [0 ] 0 -M Merged_GETS [0 ] 0 -M Other_GETS_No_Mig [0 ] 0 -M NC_DMA_GETS [0 ] 0 -M Invalidate [0 ] 0 -M Flush_line [0 ] 0 - -MM Load [354 ] 354 -MM Ifetch [0 ] 0 -MM Store [614 ] 614 -MM L2_Replacement [220 ] 220 -MM L1_to_L2 [293 ] 293 -MM Trigger_L2_to_L1D [70 ] 70 -MM Trigger_L2_to_L1I [0 ] 0 -MM Other_GETX [0 ] 0 -MM Other_GETS [0 ] 0 -MM Merged_GETS [0 ] 0 -MM Other_GETS_No_Mig [0 ] 0 -MM NC_DMA_GETS [0 ] 0 -MM Invalidate [0 ] 0 -MM Flush_line [0 ] 0 - -IR Load [0 ] 0 -IR Ifetch [0 ] 0 -IR Store [0 ] 0 -IR L1_to_L2 [0 ] 0 -IR Flush_line [0 ] 0 - -SR Load [0 ] 0 -SR Ifetch [0 ] 0 -SR Store [0 ] 0 -SR L1_to_L2 [0 ] 0 -SR Flush_line [0 ] 0 - -OR Load [0 ] 0 -OR Ifetch [0 ] 0 -OR Store [0 ] 0 -OR L1_to_L2 [0 ] 0 -OR Flush_line [0 ] 0 - -MR Load [62 ] 62 -MR Ifetch [65 ] 65 -MR Store [6 ] 6 -MR L1_to_L2 [0 ] 0 -MR Flush_line [0 ] 0 - -MMR Load [43 ] 43 -MMR Ifetch [0 ] 0 -MMR Store [27 ] 27 -MMR L1_to_L2 [0 ] 0 -MMR Flush_line [0 ] 0 - -IM Load [0 ] 0 -IM Ifetch [0 ] 0 -IM Store [0 ] 0 -IM L2_Replacement [0 ] 0 -IM L1_to_L2 [0 ] 0 -IM Other_GETX [0 ] 0 -IM Other_GETS [0 ] 0 -IM Other_GETS_No_Mig [0 ] 0 -IM NC_DMA_GETS [0 ] 0 -IM Invalidate [0 ] 0 -IM Ack [0 ] 0 -IM Data [0 ] 0 -IM Exclusive_Data [158 ] 158 -IM Flush_line [0 ] 0 - -SM Load [0 ] 0 -SM Ifetch [0 ] 0 -SM Store [0 ] 0 -SM L2_Replacement [0 ] 0 -SM L1_to_L2 [0 ] 0 -SM Other_GETX [0 ] 0 -SM Other_GETS [0 ] 0 -SM Other_GETS_No_Mig [0 ] 0 -SM NC_DMA_GETS [0 ] 0 -SM Invalidate [0 ] 0 -SM Ack [0 ] 0 -SM Data [0 ] 0 -SM Exclusive_Data [0 ] 0 -SM Flush_line [0 ] 0 - -OM Load [0 ] 0 -OM Ifetch [0 ] 0 -OM Store [0 ] 0 -OM L2_Replacement [0 ] 0 -OM L1_to_L2 [0 ] 0 -OM Other_GETX [0 ] 0 -OM Other_GETS [0 ] 0 -OM Merged_GETS [0 ] 0 -OM Other_GETS_No_Mig [0 ] 0 -OM NC_DMA_GETS [0 ] 0 -OM Invalidate [0 ] 0 -OM Ack [0 ] 0 -OM All_acks [0 ] 0 -OM All_acks_no_sharers [0 ] 0 -OM Flush_line [0 ] 0 - -ISM Load [0 ] 0 -ISM Ifetch [0 ] 0 -ISM Store [0 ] 0 -ISM L2_Replacement [0 ] 0 -ISM L1_to_L2 [0 ] 0 -ISM Ack [0 ] 0 -ISM All_acks_no_sharers [0 ] 0 -ISM Flush_line [0 ] 0 - -M_W Load [0 ] 0 -M_W Ifetch [0 ] 0 -M_W Store [0 ] 0 -M_W L2_Replacement [0 ] 0 -M_W L1_to_L2 [0 ] 0 -M_W Ack [0 ] 0 -M_W All_acks_no_sharers [1001 ] 1001 -M_W Flush_line [0 ] 0 - -MM_W Load [0 ] 0 -MM_W Ifetch [0 ] 0 -MM_W Store [0 ] 0 -MM_W L2_Replacement [0 ] 0 -MM_W L1_to_L2 [0 ] 0 -MM_W Ack [0 ] 0 -MM_W All_acks_no_sharers [158 ] 158 -MM_W Flush_line [0 ] 0 - -IS Load [0 ] 0 -IS Ifetch [0 ] 0 -IS Store [0 ] 0 -IS L2_Replacement [0 ] 0 -IS L1_to_L2 [0 ] 0 -IS Other_GETX [0 ] 0 -IS Other_GETS [0 ] 0 -IS Other_GETS_No_Mig [0 ] 0 -IS NC_DMA_GETS [0 ] 0 -IS Invalidate [0 ] 0 -IS Ack [0 ] 0 -IS Shared_Ack [0 ] 0 -IS Data [0 ] 0 -IS Shared_Data [0 ] 0 -IS Exclusive_Data [1001 ] 1001 -IS Flush_line [0 ] 0 - -SS Load [0 ] 0 -SS Ifetch [0 ] 0 -SS Store [0 ] 0 -SS L2_Replacement [0 ] 0 -SS L1_to_L2 [0 ] 0 -SS Ack [0 ] 0 -SS Shared_Ack [0 ] 0 -SS All_acks [0 ] 0 -SS All_acks_no_sharers [0 ] 0 -SS Flush_line [0 ] 0 - -OI Load [0 ] 0 -OI Ifetch [0 ] 0 -OI Store [0 ] 0 -OI L2_Replacement [0 ] 0 -OI L1_to_L2 [0 ] 0 -OI Other_GETX [0 ] 0 -OI Other_GETS [0 ] 0 -OI Merged_GETS [0 ] 0 -OI Other_GETS_No_Mig [0 ] 0 -OI NC_DMA_GETS [0 ] 0 -OI Invalidate [0 ] 0 -OI Writeback_Ack [0 ] 0 -OI Flush_line [0 ] 0 - -MI Load [8 ] 8 -MI Ifetch [11 ] 11 -MI Store [27 ] 27 -MI L2_Replacement [0 ] 0 -MI L1_to_L2 [0 ] 0 -MI Other_GETX [0 ] 0 -MI Other_GETS [0 ] 0 -MI Merged_GETS [0 ] 0 -MI Other_GETS_No_Mig [0 ] 0 -MI NC_DMA_GETS [0 ] 0 -MI Invalidate [0 ] 0 -MI Writeback_Ack [1143 ] 1143 -MI Flush_line [0 ] 0 - -II Load [0 ] 0 -II Ifetch [0 ] 0 -II Store [0 ] 0 -II L2_Replacement [0 ] 0 -II L1_to_L2 [0 ] 0 -II Other_GETX [0 ] 0 -II Other_GETS [0 ] 0 -II Other_GETS_No_Mig [0 ] 0 -II NC_DMA_GETS [0 ] 0 -II Invalidate [0 ] 0 -II Writeback_Ack [0 ] 0 -II Writeback_Nack [0 ] 0 -II Flush_line [0 ] 0 - -IT Load [0 ] 0 -IT Ifetch [0 ] 0 -IT Store [0 ] 0 -IT L2_Replacement [0 ] 0 -IT L1_to_L2 [0 ] 0 -IT Complete_L2_to_L1 [0 ] 0 - -ST Load [0 ] 0 -ST Ifetch [0 ] 0 -ST Store [0 ] 0 -ST L2_Replacement [0 ] 0 -ST L1_to_L2 [0 ] 0 -ST Complete_L2_to_L1 [0 ] 0 - -OT Load [0 ] 0 -OT Ifetch [0 ] 0 -OT Store [0 ] 0 -OT L2_Replacement [0 ] 0 -OT L1_to_L2 [0 ] 0 -OT Complete_L2_to_L1 [0 ] 0 - -MT Load [0 ] 0 -MT Ifetch [0 ] 0 -MT Store [0 ] 0 -MT L2_Replacement [0 ] 0 -MT L1_to_L2 [0 ] 0 -MT Complete_L2_to_L1 [133 ] 133 - -MMT Load [0 ] 0 -MMT Ifetch [0 ] 0 -MMT Store [0 ] 0 -MMT L2_Replacement [0 ] 0 -MMT L1_to_L2 [0 ] 0 -MMT Complete_L2_to_L1 [70 ] 70 - -MI_F Load [0 ] 0 -MI_F Ifetch [0 ] 0 -MI_F Store [0 ] 0 -MI_F L1_to_L2 [0 ] 0 -MI_F Writeback_Ack [0 ] 0 -MI_F Flush_line [0 ] 0 - -MM_F Load [0 ] 0 -MM_F Ifetch [0 ] 0 -MM_F Store [0 ] 0 -MM_F L1_to_L2 [0 ] 0 -MM_F Other_GETX [0 ] 0 -MM_F Other_GETS [0 ] 0 -MM_F Merged_GETS [0 ] 0 -MM_F Other_GETS_No_Mig [0 ] 0 -MM_F NC_DMA_GETS [0 ] 0 -MM_F Invalidate [0 ] 0 -MM_F Ack [0 ] 0 -MM_F All_acks [0 ] 0 -MM_F All_acks_no_sharers [0 ] 0 -MM_F Flush_line [0 ] 0 -MM_F Block_Ack [0 ] 0 - -IM_F Load [0 ] 0 -IM_F Ifetch [0 ] 0 -IM_F Store [0 ] 0 -IM_F L2_Replacement [0 ] 0 -IM_F L1_to_L2 [0 ] 0 -IM_F Other_GETX [0 ] 0 -IM_F Other_GETS [0 ] 0 -IM_F Other_GETS_No_Mig [0 ] 0 -IM_F NC_DMA_GETS [0 ] 0 -IM_F Invalidate [0 ] 0 -IM_F Ack [0 ] 0 -IM_F Data [0 ] 0 -IM_F Exclusive_Data [0 ] 0 -IM_F Flush_line [0 ] 0 - -ISM_F Load [0 ] 0 -ISM_F Ifetch [0 ] 0 -ISM_F Store [0 ] 0 -ISM_F L2_Replacement [0 ] 0 -ISM_F L1_to_L2 [0 ] 0 -ISM_F Ack [0 ] 0 -ISM_F All_acks_no_sharers [0 ] 0 -ISM_F Flush_line [0 ] 0 - -SM_F Load [0 ] 0 -SM_F Ifetch [0 ] 0 -SM_F Store [0 ] 0 -SM_F L2_Replacement [0 ] 0 -SM_F L1_to_L2 [0 ] 0 -SM_F Other_GETX [0 ] 0 -SM_F Other_GETS [0 ] 0 -SM_F Other_GETS_No_Mig [0 ] 0 -SM_F NC_DMA_GETS [0 ] 0 -SM_F Invalidate [0 ] 0 -SM_F Ack [0 ] 0 -SM_F Data [0 ] 0 -SM_F Exclusive_Data [0 ] 0 -SM_F Flush_line [0 ] 0 - -OM_F Load [0 ] 0 -OM_F Ifetch [0 ] 0 -OM_F Store [0 ] 0 -OM_F L2_Replacement [0 ] 0 -OM_F L1_to_L2 [0 ] 0 -OM_F Other_GETX [0 ] 0 -OM_F Other_GETS [0 ] 0 -OM_F Merged_GETS [0 ] 0 -OM_F Other_GETS_No_Mig [0 ] 0 -OM_F NC_DMA_GETS [0 ] 0 -OM_F Invalidate [0 ] 0 -OM_F Ack [0 ] 0 -OM_F All_acks [0 ] 0 -OM_F All_acks_no_sharers [0 ] 0 -OM_F Flush_line [0 ] 0 - -MM_WF Load [0 ] 0 -MM_WF Ifetch [0 ] 0 -MM_WF Store [0 ] 0 -MM_WF L2_Replacement [0 ] 0 -MM_WF L1_to_L2 [0 ] 0 -MM_WF Ack [0 ] 0 -MM_WF All_acks_no_sharers [0 ] 0 -MM_WF Flush_line [0 ] 0 - -Memory controller: system.ruby.dir_cntrl0.memBuffer: - memory_total_requests: 1379 - memory_reads: 1159 - memory_writes: 220 - memory_refreshes: 649 - memory_total_request_delays: 167 - memory_delays_per_request: 0.121102 - memory_delays_in_input_queue: 1 - memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 166 - memory_stalls_for_bank_busy: 114 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 11 - memory_stalls_for_bus: 33 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 8 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 75 17 45 40 54 101 33 16 20 22 32 34 53 50 39 31 39 22 21 27 28 38 81 22 31 23 32 72 89 126 14 52 - - --- Directory --- - - Event Counts - -GETX [186 ] 186 -GETS [1022 ] 1022 -PUT [1143 ] 1143 -Unblock [0 ] 0 -UnblockS [0 ] 0 -UnblockM [1159 ] 1159 -Writeback_Clean [0 ] 0 -Writeback_Dirty [0 ] 0 -Writeback_Exclusive_Clean [923 ] 923 -Writeback_Exclusive_Dirty [220 ] 220 -Pf_Replacement [0 ] 0 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -Memory_Data [1159 ] 1159 -Memory_Ack [220 ] 220 -Ack [0 ] 0 -Shared_Ack [0 ] 0 -Shared_Data [0 ] 0 -Data [0 ] 0 -Exclusive_Data [0 ] 0 -All_acks_and_shared_data [0 ] 0 -All_acks_and_owner_data [0 ] 0 -All_acks_and_data_no_sharers [0 ] 0 -All_Unblocks [0 ] 0 -GETF [0 ] 0 -PUTF [0 ] 0 - - - Transitions - -NX GETX [0 ] 0 -NX GETS [0 ] 0 -NX PUT [0 ] 0 -NX Pf_Replacement [0 ] 0 -NX DMA_READ [0 ] 0 -NX DMA_WRITE [0 ] 0 -NX GETF [0 ] 0 - -NO GETX [0 ] 0 -NO GETS [0 ] 0 -NO PUT [1143 ] 1143 -NO Pf_Replacement [0 ] 0 -NO DMA_READ [0 ] 0 -NO DMA_WRITE [0 ] 0 -NO GETF [0 ] 0 - -S GETX [0 ] 0 -S GETS [0 ] 0 -S PUT [0 ] 0 -S Pf_Replacement [0 ] 0 -S DMA_READ [0 ] 0 -S DMA_WRITE [0 ] 0 -S GETF [0 ] 0 - -O GETX [0 ] 0 -O GETS [0 ] 0 -O PUT [0 ] 0 -O Pf_Replacement [0 ] 0 -O DMA_READ [0 ] 0 -O DMA_WRITE [0 ] 0 -O GETF [0 ] 0 - -E GETX [158 ] 158 -E GETS [1001 ] 1001 -E PUT [0 ] 0 -E DMA_READ [0 ] 0 -E DMA_WRITE [0 ] 0 -E GETF [0 ] 0 - -O_R GETX [0 ] 0 -O_R GETS [0 ] 0 -O_R PUT [0 ] 0 -O_R Pf_Replacement [0 ] 0 -O_R DMA_READ [0 ] 0 -O_R DMA_WRITE [0 ] 0 -O_R Ack [0 ] 0 -O_R All_acks_and_data_no_sharers [0 ] 0 -O_R GETF [0 ] 0 - -S_R GETX [0 ] 0 -S_R GETS [0 ] 0 -S_R PUT [0 ] 0 -S_R Pf_Replacement [0 ] 0 -S_R DMA_READ [0 ] 0 -S_R DMA_WRITE [0 ] 0 -S_R Ack [0 ] 0 -S_R Data [0 ] 0 -S_R All_acks_and_data_no_sharers [0 ] 0 -S_R GETF [0 ] 0 - -NO_R GETX [0 ] 0 -NO_R GETS [0 ] 0 -NO_R PUT [0 ] 0 -NO_R Pf_Replacement [0 ] 0 -NO_R DMA_READ [0 ] 0 -NO_R DMA_WRITE [0 ] 0 -NO_R Ack [0 ] 0 -NO_R Data [0 ] 0 -NO_R Exclusive_Data [0 ] 0 -NO_R All_acks_and_data_no_sharers [0 ] 0 -NO_R GETF [0 ] 0 - -NO_B GETX [0 ] 0 -NO_B GETS [0 ] 0 -NO_B PUT [0 ] 0 -NO_B UnblockS [0 ] 0 -NO_B UnblockM [1159 ] 1159 -NO_B Pf_Replacement [0 ] 0 -NO_B DMA_READ [0 ] 0 -NO_B DMA_WRITE [0 ] 0 -NO_B GETF [0 ] 0 - -NO_B_X GETX [0 ] 0 -NO_B_X GETS [0 ] 0 -NO_B_X PUT [0 ] 0 -NO_B_X UnblockS [0 ] 0 -NO_B_X UnblockM [0 ] 0 -NO_B_X Pf_Replacement [0 ] 0 -NO_B_X DMA_READ [0 ] 0 -NO_B_X DMA_WRITE [0 ] 0 -NO_B_X GETF [0 ] 0 - -NO_B_S GETX [0 ] 0 -NO_B_S GETS [0 ] 0 -NO_B_S PUT [0 ] 0 -NO_B_S UnblockS [0 ] 0 -NO_B_S UnblockM [0 ] 0 -NO_B_S Pf_Replacement [0 ] 0 -NO_B_S DMA_READ [0 ] 0 -NO_B_S DMA_WRITE [0 ] 0 -NO_B_S GETF [0 ] 0 - -NO_B_S_W GETX [0 ] 0 -NO_B_S_W GETS [0 ] 0 -NO_B_S_W PUT [0 ] 0 -NO_B_S_W UnblockS [0 ] 0 -NO_B_S_W Pf_Replacement [0 ] 0 -NO_B_S_W DMA_READ [0 ] 0 -NO_B_S_W DMA_WRITE [0 ] 0 -NO_B_S_W All_Unblocks [0 ] 0 -NO_B_S_W GETF [0 ] 0 - -O_B GETX [0 ] 0 -O_B GETS [0 ] 0 -O_B PUT [0 ] 0 -O_B UnblockS [0 ] 0 -O_B UnblockM [0 ] 0 -O_B Pf_Replacement [0 ] 0 -O_B DMA_READ [0 ] 0 -O_B DMA_WRITE [0 ] 0 -O_B GETF [0 ] 0 - -NO_B_W GETX [0 ] 0 -NO_B_W GETS [0 ] 0 -NO_B_W PUT [0 ] 0 -NO_B_W UnblockS [0 ] 0 -NO_B_W UnblockM [0 ] 0 -NO_B_W Pf_Replacement [0 ] 0 -NO_B_W DMA_READ [0 ] 0 -NO_B_W DMA_WRITE [0 ] 0 -NO_B_W Memory_Data [1159 ] 1159 -NO_B_W GETF [0 ] 0 - -O_B_W GETX [0 ] 0 -O_B_W GETS [0 ] 0 -O_B_W PUT [0 ] 0 -O_B_W UnblockS [0 ] 0 -O_B_W Pf_Replacement [0 ] 0 -O_B_W DMA_READ [0 ] 0 -O_B_W DMA_WRITE [0 ] 0 -O_B_W Memory_Data [0 ] 0 -O_B_W GETF [0 ] 0 - -NO_W GETX [0 ] 0 -NO_W GETS [0 ] 0 -NO_W PUT [0 ] 0 -NO_W Pf_Replacement [0 ] 0 -NO_W DMA_READ [0 ] 0 -NO_W DMA_WRITE [0 ] 0 -NO_W Memory_Data [0 ] 0 -NO_W GETF [0 ] 0 - -O_W GETX [0 ] 0 -O_W GETS [0 ] 0 -O_W PUT [0 ] 0 -O_W Pf_Replacement [0 ] 0 -O_W DMA_READ [0 ] 0 -O_W DMA_WRITE [0 ] 0 -O_W Memory_Data [0 ] 0 -O_W GETF [0 ] 0 - -NO_DW_B_W GETX [0 ] 0 -NO_DW_B_W GETS [0 ] 0 -NO_DW_B_W PUT [0 ] 0 -NO_DW_B_W Pf_Replacement [0 ] 0 -NO_DW_B_W DMA_READ [0 ] 0 -NO_DW_B_W DMA_WRITE [0 ] 0 -NO_DW_B_W Ack [0 ] 0 -NO_DW_B_W Data [0 ] 0 -NO_DW_B_W Exclusive_Data [0 ] 0 -NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0 -NO_DW_B_W GETF [0 ] 0 - -NO_DR_B_W GETX [0 ] 0 -NO_DR_B_W GETS [0 ] 0 -NO_DR_B_W PUT [0 ] 0 -NO_DR_B_W Pf_Replacement [0 ] 0 -NO_DR_B_W DMA_READ [0 ] 0 -NO_DR_B_W DMA_WRITE [0 ] 0 -NO_DR_B_W Memory_Data [0 ] 0 -NO_DR_B_W Ack [0 ] 0 -NO_DR_B_W Shared_Ack [0 ] 0 -NO_DR_B_W Shared_Data [0 ] 0 -NO_DR_B_W Data [0 ] 0 -NO_DR_B_W Exclusive_Data [0 ] 0 -NO_DR_B_W GETF [0 ] 0 - -NO_DR_B_D GETX [0 ] 0 -NO_DR_B_D GETS [0 ] 0 -NO_DR_B_D PUT [0 ] 0 -NO_DR_B_D Pf_Replacement [0 ] 0 -NO_DR_B_D DMA_READ [0 ] 0 -NO_DR_B_D DMA_WRITE [0 ] 0 -NO_DR_B_D Ack [0 ] 0 -NO_DR_B_D Shared_Ack [0 ] 0 -NO_DR_B_D Shared_Data [0 ] 0 -NO_DR_B_D Data [0 ] 0 -NO_DR_B_D Exclusive_Data [0 ] 0 -NO_DR_B_D All_acks_and_shared_data [0 ] 0 -NO_DR_B_D All_acks_and_owner_data [0 ] 0 -NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0 -NO_DR_B_D GETF [0 ] 0 - -NO_DR_B GETX [0 ] 0 -NO_DR_B GETS [0 ] 0 -NO_DR_B PUT [0 ] 0 -NO_DR_B Pf_Replacement [0 ] 0 -NO_DR_B DMA_READ [0 ] 0 -NO_DR_B DMA_WRITE [0 ] 0 -NO_DR_B Ack [0 ] 0 -NO_DR_B Shared_Ack [0 ] 0 -NO_DR_B Shared_Data [0 ] 0 -NO_DR_B Data [0 ] 0 -NO_DR_B Exclusive_Data [0 ] 0 -NO_DR_B All_acks_and_shared_data [0 ] 0 -NO_DR_B All_acks_and_owner_data [0 ] 0 -NO_DR_B All_acks_and_data_no_sharers [0 ] 0 -NO_DR_B GETF [0 ] 0 - -NO_DW_W GETX [0 ] 0 -NO_DW_W GETS [0 ] 0 -NO_DW_W PUT [0 ] 0 -NO_DW_W Pf_Replacement [0 ] 0 -NO_DW_W DMA_READ [0 ] 0 -NO_DW_W DMA_WRITE [0 ] 0 -NO_DW_W Memory_Ack [0 ] 0 -NO_DW_W GETF [0 ] 0 - -O_DR_B_W GETX [0 ] 0 -O_DR_B_W GETS [0 ] 0 -O_DR_B_W PUT [0 ] 0 -O_DR_B_W Pf_Replacement [0 ] 0 -O_DR_B_W DMA_READ [0 ] 0 -O_DR_B_W DMA_WRITE [0 ] 0 -O_DR_B_W Memory_Data [0 ] 0 -O_DR_B_W Ack [0 ] 0 -O_DR_B_W Shared_Ack [0 ] 0 -O_DR_B_W GETF [0 ] 0 - -O_DR_B GETX [0 ] 0 -O_DR_B GETS [0 ] 0 -O_DR_B PUT [0 ] 0 -O_DR_B Pf_Replacement [0 ] 0 -O_DR_B DMA_READ [0 ] 0 -O_DR_B DMA_WRITE [0 ] 0 -O_DR_B Ack [0 ] 0 -O_DR_B Shared_Ack [0 ] 0 -O_DR_B All_acks_and_owner_data [0 ] 0 -O_DR_B All_acks_and_data_no_sharers [0 ] 0 -O_DR_B GETF [0 ] 0 - -WB GETX [27 ] 27 -WB GETS [19 ] 19 -WB PUT [0 ] 0 -WB Unblock [0 ] 0 -WB Writeback_Clean [0 ] 0 -WB Writeback_Dirty [0 ] 0 -WB Writeback_Exclusive_Clean [923 ] 923 -WB Writeback_Exclusive_Dirty [220 ] 220 -WB Pf_Replacement [0 ] 0 -WB DMA_READ [0 ] 0 -WB DMA_WRITE [0 ] 0 -WB GETF [0 ] 0 - -WB_O_W GETX [0 ] 0 -WB_O_W GETS [0 ] 0 -WB_O_W PUT [0 ] 0 -WB_O_W Pf_Replacement [0 ] 0 -WB_O_W DMA_READ [0 ] 0 -WB_O_W DMA_WRITE [0 ] 0 -WB_O_W Memory_Ack [0 ] 0 -WB_O_W GETF [0 ] 0 - -WB_E_W GETX [1 ] 1 -WB_E_W GETS [2 ] 2 -WB_E_W PUT [0 ] 0 -WB_E_W Pf_Replacement [0 ] 0 -WB_E_W DMA_READ [0 ] 0 -WB_E_W DMA_WRITE [0 ] 0 -WB_E_W Memory_Ack [220 ] 220 -WB_E_W GETF [0 ] 0 - -NO_F GETX [0 ] 0 -NO_F GETS [0 ] 0 -NO_F PUT [0 ] 0 -NO_F UnblockM [0 ] 0 -NO_F Pf_Replacement [0 ] 0 -NO_F GETF [0 ] 0 -NO_F PUTF [0 ] 0 - -NO_F_W GETX [0 ] 0 -NO_F_W GETS [0 ] 0 -NO_F_W PUT [0 ] 0 -NO_F_W Pf_Replacement [0 ] 0 -NO_F_W DMA_READ [0 ] 0 -NO_F_W DMA_WRITE [0 ] 0 -NO_F_W Memory_Data [0 ] 0 -NO_F_W GETF [0 ] 0 - diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index aace843a9..0583b2632 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000093 # Nu sim_ticks 93341 # Number of ticks simulated final_tick 93341 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 22966 # Simulator instruction rate (inst/s) -host_op_rate 22964 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 335419 # Simulator tick rate (ticks/s) -host_mem_usage 152500 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host +host_inst_rate 15100 # Simulator instruction rate (inst/s) +host_op_rate 15100 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 220554 # Simulator tick rate (ticks/s) +host_mem_usage 146612 # Number of bytes of host memory used +host_seconds 0.42 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.ruby.l1_cntrl0.L1Dcache.demand_hits 1332 # Number of cache demand hits @@ -20,6 +20,21 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 system.ruby.l1_cntrl0.L2cache.demand_hits 203 # Number of cache demand hits system.ruby.l1_cntrl0.L2cache.demand_misses 1159 # Number of cache demand misses system.ruby.l1_cntrl0.L2cache.demand_accesses 1362 # Number of cache demand accesses +system.ruby.dir_cntrl0.memBuffer.memReq 1379 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 1159 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 220 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 649 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 166 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memInputQ 1 # Delay in the input queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 167 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.121102 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 114 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 33 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 8 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 11 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 75 5.44% 5.44% | 17 1.23% 6.67% | 45 3.26% 9.93% | 40 2.90% 12.84% | 54 3.92% 16.75% | 101 7.32% 24.08% | 33 2.39% 26.47% | 16 1.16% 27.63% | 20 1.45% 29.08% | 22 1.60% 30.67% | 32 2.32% 32.99% | 34 2.47% 35.46% | 53 3.84% 39.30% | 50 3.63% 42.93% | 39 2.83% 45.76% | 31 2.25% 48.01% | 39 2.83% 50.83% | 22 1.60% 52.43% | 21 1.52% 53.95% | 27 1.96% 55.91% | 28 2.03% 57.94% | 38 2.76% 60.70% | 81 5.87% 66.57% | 22 1.60% 68.17% | 31 2.25% 70.41% | 23 1.67% 72.08% | 32 2.32% 74.40% | 72 5.22% 79.62% | 89 6.45% 86.08% | 126 9.14% 95.21% | 14 1.02% 96.23% | 52 3.77% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1379 # Number of accesses per bank + system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses @@ -78,5 +93,66 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 93341 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles +system.ruby.l1_cntrl0.Load 1191 0.00% 0.00% +system.ruby.l1_cntrl0.Ifetch 6411 0.00% 0.00% +system.ruby.l1_cntrl0.Store 892 0.00% 0.00% +system.ruby.l1_cntrl0.L2_Replacement 1143 0.00% 0.00% +system.ruby.l1_cntrl0.L1_to_L2 1354 0.00% 0.00% +system.ruby.l1_cntrl0.Trigger_L2_to_L1D 138 0.00% 0.00% +system.ruby.l1_cntrl0.Trigger_L2_to_L1I 65 0.00% 0.00% +system.ruby.l1_cntrl0.Complete_L2_to_L1 203 0.00% 0.00% +system.ruby.l1_cntrl0.Exclusive_Data 1159 0.00% 0.00% +system.ruby.l1_cntrl0.Writeback_Ack 1143 0.00% 0.00% +system.ruby.l1_cntrl0.All_acks_no_sharers 1159 0.00% 0.00% +system.ruby.l1_cntrl0.I.Load 420 0.00% 0.00% +system.ruby.l1_cntrl0.I.Ifetch 581 0.00% 0.00% +system.ruby.l1_cntrl0.I.Store 158 0.00% 0.00% +system.ruby.l1_cntrl0.M.Load 304 0.00% 0.00% +system.ruby.l1_cntrl0.M.Ifetch 5754 0.00% 0.00% +system.ruby.l1_cntrl0.M.Store 60 0.00% 0.00% +system.ruby.l1_cntrl0.M.L2_Replacement 923 0.00% 0.00% +system.ruby.l1_cntrl0.M.L1_to_L2 1061 0.00% 0.00% +system.ruby.l1_cntrl0.M.Trigger_L2_to_L1D 68 0.00% 0.00% +system.ruby.l1_cntrl0.M.Trigger_L2_to_L1I 65 0.00% 0.00% +system.ruby.l1_cntrl0.MM.Load 354 0.00% 0.00% +system.ruby.l1_cntrl0.MM.Store 614 0.00% 0.00% +system.ruby.l1_cntrl0.MM.L2_Replacement 220 0.00% 0.00% +system.ruby.l1_cntrl0.MM.L1_to_L2 293 0.00% 0.00% +system.ruby.l1_cntrl0.MM.Trigger_L2_to_L1D 70 0.00% 0.00% +system.ruby.l1_cntrl0.MR.Load 62 0.00% 0.00% +system.ruby.l1_cntrl0.MR.Ifetch 65 0.00% 0.00% +system.ruby.l1_cntrl0.MR.Store 6 0.00% 0.00% +system.ruby.l1_cntrl0.MMR.Load 43 0.00% 0.00% +system.ruby.l1_cntrl0.MMR.Store 27 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Exclusive_Data 158 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.All_acks_no_sharers 1001 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.All_acks_no_sharers 158 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Exclusive_Data 1001 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Load 8 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Ifetch 11 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Store 27 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Writeback_Ack 1143 0.00% 0.00% +system.ruby.l1_cntrl0.MT.Complete_L2_to_L1 133 0.00% 0.00% +system.ruby.l1_cntrl0.MMT.Complete_L2_to_L1 70 0.00% 0.00% +system.ruby.dir_cntrl0.GETX 186 0.00% 0.00% +system.ruby.dir_cntrl0.GETS 1022 0.00% 0.00% +system.ruby.dir_cntrl0.PUT 1143 0.00% 0.00% +system.ruby.dir_cntrl0.UnblockM 1159 0.00% 0.00% +system.ruby.dir_cntrl0.Writeback_Exclusive_Clean 923 0.00% 0.00% +system.ruby.dir_cntrl0.Writeback_Exclusive_Dirty 220 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 1159 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 220 0.00% 0.00% +system.ruby.dir_cntrl0.NO.PUT 1143 0.00% 0.00% +system.ruby.dir_cntrl0.E.GETX 158 0.00% 0.00% +system.ruby.dir_cntrl0.E.GETS 1001 0.00% 0.00% +system.ruby.dir_cntrl0.NO_B.UnblockM 1159 0.00% 0.00% +system.ruby.dir_cntrl0.NO_B_W.Memory_Data 1159 0.00% 0.00% +system.ruby.dir_cntrl0.WB.GETX 27 0.00% 0.00% +system.ruby.dir_cntrl0.WB.GETS 19 0.00% 0.00% +system.ruby.dir_cntrl0.WB.Writeback_Exclusive_Clean 923 0.00% 0.00% +system.ruby.dir_cntrl0.WB.Writeback_Exclusive_Dirty 220 0.00% 0.00% +system.ruby.dir_cntrl0.WB_E_W.GETX 1 0.00% 0.00% +system.ruby.dir_cntrl0.WB_E_W.GETS 2 0.00% 0.00% +system.ruby.dir_cntrl0.WB_E_W.Memory_Ack 220 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats index b561f1129..005ede722 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats @@ -1,4 +1,4 @@ -Real time: Mar/06/2013 20:31:07 +Real time: Jun/08/2013 13:51:49 Profiler Stats -------------- @@ -7,20 +7,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.63 -Virtual_time_in_minutes: 0.0105 -Virtual_time_in_hours: 0.000175 -Virtual_time_in_days: 7.29167e-06 +Virtual_time_in_seconds: 0.5 +Virtual_time_in_minutes: 0.00833333 +Virtual_time_in_hours: 0.000138889 +Virtual_time_in_days: 5.78704e-06 Ruby_current_time: 143853 Ruby_start_time: 0 Ruby_cycles: 143853 -mbytes_resident: 55.1172 -mbytes_total: 146.695 -resident_ratio: 0.375806 - -ruby_cycles_executed: [ 143854 ] +mbytes_resident: 55.0938 +mbytes_total: 142.211 +resident_ratio: 0.387464 Busy Controller Counts: L1Cache-0:0 @@ -64,7 +62,6 @@ Request vs. RubySystem State Profile -------------------------------- -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- @@ -85,10 +82,10 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10897 +page_reclaims: 11329 page_faults: 0 swaps: 0 -block_inputs: 336 +block_inputs: 0 block_outputs: 88 Network Stats @@ -133,129 +130,3 @@ links_utilized_percent_switch_2: 6.00613 outgoing_messages_switch_2_link_1_Control: 1730 13840 [ 0 0 1730 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Data: 1726 124272 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1 - --- L1Cache --- - - Event Counts - -Load [1183 ] 1183 -Ifetch [6400 ] 6400 -Store [865 ] 865 -Data [1730 ] 1730 -Fwd_GETX [0 ] 0 -Inv [0 ] 0 -Replacement [1726 ] 1726 -Writeback_Ack [1726 ] 1726 -Writeback_Nack [0 ] 0 - - - Transitions - -I Load [727 ] 727 -I Ifetch [730 ] 730 -I Store [273 ] 273 -I Inv [0 ] 0 -I Replacement [0 ] 0 - -II Writeback_Nack [0 ] 0 - -M Load [456 ] 456 -M Ifetch [5670 ] 5670 -M Store [592 ] 592 -M Fwd_GETX [0 ] 0 -M Inv [0 ] 0 -M Replacement [1726 ] 1726 - -MI Fwd_GETX [0 ] 0 -MI Inv [0 ] 0 -MI Writeback_Ack [1726 ] 1726 -MI Writeback_Nack [0 ] 0 - -MII Fwd_GETX [0 ] 0 - -IS Data [1457 ] 1457 - -IM Data [273 ] 273 - -Memory controller: system.ruby.dir_cntrl0.memBuffer: - memory_total_requests: 3456 - memory_reads: 1730 - memory_writes: 1726 - memory_refreshes: 999 - memory_total_request_delays: 3048 - memory_delays_per_request: 0.881944 - memory_delays_in_input_queue: 0 - memory_delays_behind_head_of_bank_queue: 11 - memory_delays_stalled_at_head_of_bank_queue: 3037 - memory_stalls_for_bank_busy: 1500 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 107 - memory_stalls_for_bus: 1375 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 55 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 162 36 92 110 106 362 98 36 32 34 83 92 110 104 84 86 83 53 50 58 64 124 212 72 66 50 122 190 220 325 42 98 - - --- Directory --- - - Event Counts - -GETX [1730 ] 1730 -GETS [0 ] 0 -PUTX [1726 ] 1726 -PUTX_NotOwner [0 ] 0 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -Memory_Data [1730 ] 1730 -Memory_Ack [1726 ] 1726 - - - Transitions - -I GETX [1730 ] 1730 -I PUTX_NotOwner [0 ] 0 -I DMA_READ [0 ] 0 -I DMA_WRITE [0 ] 0 - -M GETX [0 ] 0 -M PUTX [1726 ] 1726 -M PUTX_NotOwner [0 ] 0 -M DMA_READ [0 ] 0 -M DMA_WRITE [0 ] 0 - -M_DRD GETX [0 ] 0 -M_DRD PUTX [0 ] 0 - -M_DWR GETX [0 ] 0 -M_DWR PUTX [0 ] 0 - -M_DWRI GETX [0 ] 0 -M_DWRI Memory_Ack [0 ] 0 - -M_DRDI GETX [0 ] 0 -M_DRDI Memory_Ack [0 ] 0 - -IM GETX [0 ] 0 -IM GETS [0 ] 0 -IM PUTX [0 ] 0 -IM PUTX_NotOwner [0 ] 0 -IM DMA_READ [0 ] 0 -IM DMA_WRITE [0 ] 0 -IM Memory_Data [1730 ] 1730 - -MI GETX [0 ] 0 -MI GETS [0 ] 0 -MI PUTX [0 ] 0 -MI PUTX_NotOwner [0 ] 0 -MI DMA_READ [0 ] 0 -MI DMA_WRITE [0 ] 0 -MI Memory_Ack [1726 ] 1726 - -ID GETX [0 ] 0 -ID GETS [0 ] 0 -ID PUTX [0 ] 0 -ID PUTX_NotOwner [0 ] 0 -ID DMA_READ [0 ] 0 -ID DMA_WRITE [0 ] 0 -ID Memory_Data [0 ] 0 - -ID_W GETX [0 ] 0 -ID_W GETS [0 ] 0 -ID_W PUTX [0 ] 0 -ID_W PUTX_NotOwner [0 ] 0 -ID_W DMA_READ [0 ] 0 -ID_W DMA_WRITE [0 ] 0 -ID_W Memory_Ack [0 ] 0 - diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index e942e8340..b55a5b3d1 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -4,16 +4,31 @@ sim_seconds 0.000144 # Nu sim_ticks 143853 # Number of ticks simulated final_tick 143853 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 31570 # Simulator instruction rate (inst/s) -host_op_rate 31567 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 710572 # Simulator tick rate (ticks/s) -host_mem_usage 153096 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 39172 # Simulator instruction rate (inst/s) +host_op_rate 39167 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 881633 # Simulator tick rate (ticks/s) +host_mem_usage 145628 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses +system.ruby.dir_cntrl0.memBuffer.memReq 3456 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 1730 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 1726 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 999 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 3037 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memBankQ 11 # Delay behind the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 3048 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.881944 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 1500 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 1375 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 55 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 107 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 162 4.69% 4.69% | 36 1.04% 5.73% | 92 2.66% 8.39% | 110 3.18% 11.57% | 106 3.07% 14.64% | 362 10.47% 25.12% | 98 2.84% 27.95% | 36 1.04% 28.99% | 32 0.93% 29.92% | 34 0.98% 30.90% | 83 2.40% 33.30% | 92 2.66% 35.97% | 110 3.18% 39.15% | 104 3.01% 42.16% | 84 2.43% 44.59% | 86 2.49% 47.08% | 83 2.40% 49.48% | 53 1.53% 51.01% | 50 1.45% 52.46% | 58 1.68% 54.14% | 64 1.85% 55.99% | 124 3.59% 59.58% | 212 6.13% 65.71% | 72 2.08% 67.80% | 66 1.91% 69.70% | 50 1.45% 71.15% | 122 3.53% 74.68% | 190 5.50% 80.18% | 220 6.37% 86.55% | 325 9.40% 95.95% | 42 1.22% 97.16% | 98 2.84% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 3456 # Number of accesses per bank + system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -69,5 +84,29 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 143853 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles +system.ruby.l1_cntrl0.Load 1183 0.00% 0.00% +system.ruby.l1_cntrl0.Ifetch 6400 0.00% 0.00% +system.ruby.l1_cntrl0.Store 865 0.00% 0.00% +system.ruby.l1_cntrl0.Data 1730 0.00% 0.00% +system.ruby.l1_cntrl0.Replacement 1726 0.00% 0.00% +system.ruby.l1_cntrl0.Writeback_Ack 1726 0.00% 0.00% +system.ruby.l1_cntrl0.I.Load 727 0.00% 0.00% +system.ruby.l1_cntrl0.I.Ifetch 730 0.00% 0.00% +system.ruby.l1_cntrl0.I.Store 273 0.00% 0.00% +system.ruby.l1_cntrl0.M.Load 456 0.00% 0.00% +system.ruby.l1_cntrl0.M.Ifetch 5670 0.00% 0.00% +system.ruby.l1_cntrl0.M.Store 592 0.00% 0.00% +system.ruby.l1_cntrl0.M.Replacement 1726 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Writeback_Ack 1726 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data 1457 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Data 273 0.00% 0.00% +system.ruby.dir_cntrl0.GETX 1730 0.00% 0.00% +system.ruby.dir_cntrl0.PUTX 1726 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 1730 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 1726 0.00% 0.00% +system.ruby.dir_cntrl0.I.GETX 1730 0.00% 0.00% +system.ruby.dir_cntrl0.M.PUTX 1726 0.00% 0.00% +system.ruby.dir_cntrl0.IM.Memory_Data 1730 0.00% 0.00% +system.ruby.dir_cntrl0.MI.Memory_Ack 1726 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats index e4af41b60..ff366244b 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -1,4 +1,4 @@ -Real time: Mar/06/2013 20:38:34 +Real time: Jun/08/2013 14:12:43 Profiler Stats -------------- @@ -7,20 +7,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.54 -Virtual_time_in_minutes: 0.009 -Virtual_time_in_hours: 0.00015 -Virtual_time_in_days: 6.25e-06 +Virtual_time_in_seconds: 0.48 +Virtual_time_in_minutes: 0.008 +Virtual_time_in_hours: 0.000133333 +Virtual_time_in_days: 5.55556e-06 Ruby_current_time: 52575 Ruby_start_time: 0 Ruby_cycles: 52575 -mbytes_resident: 53.8125 -mbytes_total: 145.805 -resident_ratio: 0.369126 - -ruby_cycles_executed: [ 52576 ] +mbytes_resident: 54.0742 +mbytes_total: 141.93 +resident_ratio: 0.381048 Busy Controller Counts: L1Cache-0:0 @@ -61,7 +59,6 @@ Request vs. RubySystem State Profile -------------------------------- -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- @@ -82,7 +79,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11068 +page_reclaims: 11040 page_faults: 0 swaps: 0 block_inputs: 0 @@ -160,458 +157,3 @@ links_utilized_percent_switch_3: 4.8648 outgoing_messages_switch_3_link_2_Response_Data: 103 7416 [ 0 103 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1 - --- L1Cache --- - - Event Counts - -Load [415 ] 415 -Ifetch [2585 ] 2585 -Store [294 ] 294 -Inv [431 ] 431 -L1_Replacement [502 ] 502 -Fwd_GETX [0 ] 0 -Fwd_GETS [0 ] 0 -Fwd_GET_INSTR [0 ] 0 -Data [0 ] 0 -Data_Exclusive [204 ] 204 -DataS_fromL1 [0 ] 0 -Data_all_Acks [368 ] 368 -Ack [0 ] 0 -Ack_all [0 ] 0 -WB_Ack [124 ] 124 -PF_Load [0 ] 0 -PF_Ifetch [0 ] 0 -PF_Store [0 ] 0 - - - Transitions - -NP Load [182 ] 182 -NP Ifetch [270 ] 270 -NP Store [58 ] 58 -NP Inv [162 ] 162 -NP L1_Replacement [0 ] 0 -NP PF_Load [0 ] 0 -NP PF_Ifetch [0 ] 0 -NP PF_Store [0 ] 0 - -I Load [22 ] 22 -I Ifetch [30 ] 30 -I Store [10 ] 10 -I Inv [0 ] 0 -I L1_Replacement [206 ] 206 -I PF_Load [0 ] 0 -I PF_Ifetch [0 ] 0 -I PF_Store [0 ] 0 - -S Load [0 ] 0 -S Ifetch [2285 ] 2285 -S Store [0 ] 0 -S Inv [124 ] 124 -S L1_Replacement [172 ] 172 -S PF_Load [0 ] 0 -S PF_Store [0 ] 0 - -E Load [140 ] 140 -E Ifetch [0 ] 0 -E Store [41 ] 41 -E Inv [83 ] 83 -E L1_Replacement [79 ] 79 -E Fwd_GETX [0 ] 0 -E Fwd_GETS [0 ] 0 -E Fwd_GET_INSTR [0 ] 0 -E PF_Load [0 ] 0 -E PF_Store [0 ] 0 - -M Load [71 ] 71 -M Ifetch [0 ] 0 -M Store [185 ] 185 -M Inv [62 ] 62 -M L1_Replacement [45 ] 45 -M Fwd_GETX [0 ] 0 -M Fwd_GETS [0 ] 0 -M Fwd_GET_INSTR [0 ] 0 -M PF_Load [0 ] 0 -M PF_Store [0 ] 0 - -IS Load [0 ] 0 -IS Ifetch [0 ] 0 -IS Store [0 ] 0 -IS Inv [0 ] 0 -IS L1_Replacement [0 ] 0 -IS Data_Exclusive [204 ] 204 -IS DataS_fromL1 [0 ] 0 -IS Data_all_Acks [300 ] 300 -IS PF_Load [0 ] 0 -IS PF_Store [0 ] 0 - -IM Load [0 ] 0 -IM Ifetch [0 ] 0 -IM Store [0 ] 0 -IM Inv [0 ] 0 -IM L1_Replacement [0 ] 0 -IM Data [0 ] 0 -IM Data_all_Acks [68 ] 68 -IM Ack [0 ] 0 -IM PF_Load [0 ] 0 -IM PF_Store [0 ] 0 - -SM Load [0 ] 0 -SM Ifetch [0 ] 0 -SM Store [0 ] 0 -SM Inv [0 ] 0 -SM L1_Replacement [0 ] 0 -SM Ack [0 ] 0 -SM Ack_all [0 ] 0 -SM PF_Load [0 ] 0 -SM PF_Store [0 ] 0 - -IS_I Load [0 ] 0 -IS_I Ifetch [0 ] 0 -IS_I Store [0 ] 0 -IS_I Inv [0 ] 0 -IS_I L1_Replacement [0 ] 0 -IS_I Data_Exclusive [0 ] 0 -IS_I DataS_fromL1 [0 ] 0 -IS_I Data_all_Acks [0 ] 0 -IS_I PF_Load [0 ] 0 -IS_I PF_Store [0 ] 0 - -M_I Load [0 ] 0 -M_I Ifetch [0 ] 0 -M_I Store [0 ] 0 -M_I Inv [0 ] 0 -M_I L1_Replacement [0 ] 0 -M_I Fwd_GETX [0 ] 0 -M_I Fwd_GETS [0 ] 0 -M_I Fwd_GET_INSTR [0 ] 0 -M_I WB_Ack [124 ] 124 -M_I PF_Load [0 ] 0 -M_I PF_Store [0 ] 0 - -SINK_WB_ACK Load [0 ] 0 -SINK_WB_ACK Ifetch [0 ] 0 -SINK_WB_ACK Store [0 ] 0 -SINK_WB_ACK Inv [0 ] 0 -SINK_WB_ACK L1_Replacement [0 ] 0 -SINK_WB_ACK WB_Ack [0 ] 0 -SINK_WB_ACK PF_Load [0 ] 0 -SINK_WB_ACK PF_Store [0 ] 0 - -PF_IS Load [0 ] 0 -PF_IS Ifetch [0 ] 0 -PF_IS Store [0 ] 0 -PF_IS Inv [0 ] 0 -PF_IS L1_Replacement [0 ] 0 -PF_IS Data_Exclusive [0 ] 0 -PF_IS DataS_fromL1 [0 ] 0 -PF_IS Data_all_Acks [0 ] 0 -PF_IS PF_Load [0 ] 0 -PF_IS PF_Store [0 ] 0 - -PF_IM Load [0 ] 0 -PF_IM Ifetch [0 ] 0 -PF_IM Store [0 ] 0 -PF_IM Inv [0 ] 0 -PF_IM L1_Replacement [0 ] 0 -PF_IM Data [0 ] 0 -PF_IM Data_all_Acks [0 ] 0 -PF_IM Ack [0 ] 0 -PF_IM PF_Load [0 ] 0 -PF_IM PF_Store [0 ] 0 - -PF_SM Load [0 ] 0 -PF_SM Ifetch [0 ] 0 -PF_SM Store [0 ] 0 -PF_SM Inv [0 ] 0 -PF_SM L1_Replacement [0 ] 0 -PF_SM Ack [0 ] 0 -PF_SM Ack_all [0 ] 0 - -PF_IS_I Load [0 ] 0 -PF_IS_I Store [0 ] 0 -PF_IS_I Inv [0 ] 0 -PF_IS_I L1_Replacement [0 ] 0 -PF_IS_I Data_Exclusive [0 ] 0 -PF_IS_I DataS_fromL1 [0 ] 0 -PF_IS_I Data_all_Acks [0 ] 0 - - --- L2Cache --- - - Event Counts - -L1_GET_INSTR [300 ] 300 -L1_GETS [204 ] 204 -L1_GETX [68 ] 68 -L1_UPGRADE [0 ] 0 -L1_PUTX [124 ] 124 -L1_PUTX_old [0 ] 0 -Fwd_L1_GETX [0 ] 0 -Fwd_L1_GETS [0 ] 0 -Fwd_L1_GET_INSTR [0 ] 0 -L2_Replacement [43 ] 43 -L2_Replacement_clean [496 ] 496 -Mem_Data [547 ] 547 -Mem_Ack [539 ] 539 -WB_Data [62 ] 62 -WB_Data_clean [0 ] 0 -Ack [0 ] 0 -Ack_all [369 ] 369 -Unblock [0 ] 0 -Unblock_Cancel [0 ] 0 -Exclusive_Unblock [272 ] 272 -MEM_Inv [0 ] 0 - - - Transitions - -NP L1_GET_INSTR [291 ] 291 -NP L1_GETS [192 ] 192 -NP L1_GETX [64 ] 64 -NP L1_PUTX [0 ] 0 -NP L1_PUTX_old [0 ] 0 - -SS L1_GET_INSTR [9 ] 9 -SS L1_GETS [0 ] 0 -SS L1_GETX [0 ] 0 -SS L1_UPGRADE [0 ] 0 -SS L1_PUTX [0 ] 0 -SS L1_PUTX_old [0 ] 0 -SS L2_Replacement [0 ] 0 -SS L2_Replacement_clean [286 ] 286 -SS MEM_Inv [0 ] 0 - -M L1_GET_INSTR [0 ] 0 -M L1_GETS [12 ] 12 -M L1_GETX [4 ] 4 -M L1_PUTX [0 ] 0 -M L1_PUTX_old [0 ] 0 -M L2_Replacement [39 ] 39 -M L2_Replacement_clean [69 ] 69 -M MEM_Inv [0 ] 0 - -MT L1_GET_INSTR [0 ] 0 -MT L1_GETS [0 ] 0 -MT L1_GETX [0 ] 0 -MT L1_PUTX [124 ] 124 -MT L1_PUTX_old [0 ] 0 -MT L2_Replacement [4 ] 4 -MT L2_Replacement_clean [141 ] 141 -MT MEM_Inv [0 ] 0 - -M_I L1_GET_INSTR [0 ] 0 -M_I L1_GETS [0 ] 0 -M_I L1_GETX [0 ] 0 -M_I L1_UPGRADE [0 ] 0 -M_I L1_PUTX [0 ] 0 -M_I L1_PUTX_old [0 ] 0 -M_I Mem_Ack [539 ] 539 -M_I MEM_Inv [0 ] 0 - -MT_I L1_GET_INSTR [0 ] 0 -MT_I L1_GETS [0 ] 0 -MT_I L1_GETX [0 ] 0 -MT_I L1_UPGRADE [0 ] 0 -MT_I L1_PUTX [0 ] 0 -MT_I L1_PUTX_old [0 ] 0 -MT_I WB_Data [2 ] 2 -MT_I WB_Data_clean [0 ] 0 -MT_I Ack_all [2 ] 2 -MT_I MEM_Inv [0 ] 0 - -MCT_I L1_GET_INSTR [0 ] 0 -MCT_I L1_GETS [0 ] 0 -MCT_I L1_GETX [0 ] 0 -MCT_I L1_UPGRADE [0 ] 0 -MCT_I L1_PUTX [0 ] 0 -MCT_I L1_PUTX_old [0 ] 0 -MCT_I WB_Data [60 ] 60 -MCT_I WB_Data_clean [0 ] 0 -MCT_I Ack_all [81 ] 81 - -I_I L1_GET_INSTR [0 ] 0 -I_I L1_GETS [0 ] 0 -I_I L1_GETX [0 ] 0 -I_I L1_UPGRADE [0 ] 0 -I_I L1_PUTX [0 ] 0 -I_I L1_PUTX_old [0 ] 0 -I_I Ack [0 ] 0 -I_I Ack_all [286 ] 286 - -S_I L1_GET_INSTR [0 ] 0 -S_I L1_GETS [0 ] 0 -S_I L1_GETX [0 ] 0 -S_I L1_UPGRADE [0 ] 0 -S_I L1_PUTX [0 ] 0 -S_I L1_PUTX_old [0 ] 0 -S_I Ack [0 ] 0 -S_I Ack_all [0 ] 0 -S_I MEM_Inv [0 ] 0 - -ISS L1_GET_INSTR [0 ] 0 -ISS L1_GETS [0 ] 0 -ISS L1_GETX [0 ] 0 -ISS L1_PUTX [0 ] 0 -ISS L1_PUTX_old [0 ] 0 -ISS L2_Replacement [0 ] 0 -ISS L2_Replacement_clean [0 ] 0 -ISS Mem_Data [192 ] 192 -ISS MEM_Inv [0 ] 0 - -IS L1_GET_INSTR [0 ] 0 -IS L1_GETS [0 ] 0 -IS L1_GETX [0 ] 0 -IS L1_PUTX [0 ] 0 -IS L1_PUTX_old [0 ] 0 -IS L2_Replacement [0 ] 0 -IS L2_Replacement_clean [0 ] 0 -IS Mem_Data [291 ] 291 -IS MEM_Inv [0 ] 0 - -IM L1_GET_INSTR [0 ] 0 -IM L1_GETS [0 ] 0 -IM L1_GETX [0 ] 0 -IM L1_PUTX [0 ] 0 -IM L1_PUTX_old [0 ] 0 -IM L2_Replacement [0 ] 0 -IM L2_Replacement_clean [0 ] 0 -IM Mem_Data [64 ] 64 -IM MEM_Inv [0 ] 0 - -SS_MB L1_GET_INSTR [0 ] 0 -SS_MB L1_GETS [0 ] 0 -SS_MB L1_GETX [0 ] 0 -SS_MB L1_UPGRADE [0 ] 0 -SS_MB L1_PUTX [0 ] 0 -SS_MB L1_PUTX_old [0 ] 0 -SS_MB L2_Replacement [0 ] 0 -SS_MB L2_Replacement_clean [0 ] 0 -SS_MB Unblock_Cancel [0 ] 0 -SS_MB Exclusive_Unblock [0 ] 0 -SS_MB MEM_Inv [0 ] 0 - -MT_MB L1_GET_INSTR [0 ] 0 -MT_MB L1_GETS [0 ] 0 -MT_MB L1_GETX [0 ] 0 -MT_MB L1_UPGRADE [0 ] 0 -MT_MB L1_PUTX [0 ] 0 -MT_MB L1_PUTX_old [0 ] 0 -MT_MB L2_Replacement [0 ] 0 -MT_MB L2_Replacement_clean [0 ] 0 -MT_MB Unblock_Cancel [0 ] 0 -MT_MB Exclusive_Unblock [272 ] 272 -MT_MB MEM_Inv [0 ] 0 - -MT_IIB L1_GET_INSTR [0 ] 0 -MT_IIB L1_GETS [0 ] 0 -MT_IIB L1_GETX [0 ] 0 -MT_IIB L1_UPGRADE [0 ] 0 -MT_IIB L1_PUTX [0 ] 0 -MT_IIB L1_PUTX_old [0 ] 0 -MT_IIB L2_Replacement [0 ] 0 -MT_IIB L2_Replacement_clean [0 ] 0 -MT_IIB WB_Data [0 ] 0 -MT_IIB WB_Data_clean [0 ] 0 -MT_IIB Unblock [0 ] 0 -MT_IIB MEM_Inv [0 ] 0 - -MT_IB L1_GET_INSTR [0 ] 0 -MT_IB L1_GETS [0 ] 0 -MT_IB L1_GETX [0 ] 0 -MT_IB L1_UPGRADE [0 ] 0 -MT_IB L1_PUTX [0 ] 0 -MT_IB L1_PUTX_old [0 ] 0 -MT_IB L2_Replacement [0 ] 0 -MT_IB L2_Replacement_clean [0 ] 0 -MT_IB WB_Data [0 ] 0 -MT_IB WB_Data_clean [0 ] 0 -MT_IB Unblock_Cancel [0 ] 0 -MT_IB MEM_Inv [0 ] 0 - -MT_SB L1_GET_INSTR [0 ] 0 -MT_SB L1_GETS [0 ] 0 -MT_SB L1_GETX [0 ] 0 -MT_SB L1_UPGRADE [0 ] 0 -MT_SB L1_PUTX [0 ] 0 -MT_SB L1_PUTX_old [0 ] 0 -MT_SB L2_Replacement [0 ] 0 -MT_SB L2_Replacement_clean [0 ] 0 -MT_SB Unblock [0 ] 0 -MT_SB MEM_Inv [0 ] 0 - -Memory controller: system.ruby.dir_cntrl0.memBuffer: - memory_total_requests: 650 - memory_reads: 547 - memory_writes: 103 - memory_refreshes: 365 - memory_total_request_delays: 117 - memory_delays_per_request: 0.18 - memory_delays_in_input_queue: 0 - memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 117 - memory_stalls_for_bank_busy: 63 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 8 - memory_stalls_for_bus: 46 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 0 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 26 14 0 49 21 21 42 25 6 4 7 4 24 42 26 3 5 7 7 18 10 29 15 50 19 5 6 16 14 24 19 92 - - --- Directory --- - - Event Counts - -Fetch [547 ] 547 -Data [103 ] 103 -Memory_Data [547 ] 547 -Memory_Ack [103 ] 103 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -CleanReplacement [436 ] 436 - - - Transitions - -I Fetch [547 ] 547 -I DMA_READ [0 ] 0 -I DMA_WRITE [0 ] 0 - -ID Fetch [0 ] 0 -ID Data [0 ] 0 -ID Memory_Data [0 ] 0 -ID DMA_READ [0 ] 0 -ID DMA_WRITE [0 ] 0 - -ID_W Fetch [0 ] 0 -ID_W Data [0 ] 0 -ID_W Memory_Ack [0 ] 0 -ID_W DMA_READ [0 ] 0 -ID_W DMA_WRITE [0 ] 0 - -M Data [103 ] 103 -M DMA_READ [0 ] 0 -M DMA_WRITE [0 ] 0 -M CleanReplacement [436 ] 436 - -IM Fetch [0 ] 0 -IM Data [0 ] 0 -IM Memory_Data [547 ] 547 -IM DMA_READ [0 ] 0 -IM DMA_WRITE [0 ] 0 - -MI Fetch [0 ] 0 -MI Data [0 ] 0 -MI Memory_Ack [103 ] 103 -MI DMA_READ [0 ] 0 -MI DMA_WRITE [0 ] 0 - -M_DRD Data [0 ] 0 -M_DRD DMA_READ [0 ] 0 -M_DRD DMA_WRITE [0 ] 0 - -M_DRDI Fetch [0 ] 0 -M_DRDI Data [0 ] 0 -M_DRDI Memory_Ack [0 ] 0 -M_DRDI DMA_READ [0 ] 0 -M_DRDI DMA_WRITE [0 ] 0 - -M_DWR Data [0 ] 0 -M_DWR DMA_READ [0 ] 0 -M_DWR DMA_WRITE [0 ] 0 - -M_DWRI Fetch [0 ] 0 -M_DWRI Data [0 ] 0 -M_DWRI Memory_Ack [0 ] 0 -M_DWRI DMA_READ [0 ] 0 -M_DWRI DMA_WRITE [0 ] 0 - diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt index e400893c2..6569b99b5 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000053 # Nu sim_ticks 52575 # Number of ticks simulated final_tick 52575 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 12497 # Simulator instruction rate (inst/s) -host_op_rate 12496 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 254920 # Simulator tick rate (ticks/s) -host_mem_usage 152164 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 18867 # Simulator instruction rate (inst/s) +host_op_rate 18864 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 384805 # Simulator tick rate (ticks/s) +host_mem_usage 145340 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.ruby.l2_cntrl0.L2cache.demand_hits 25 # Number of cache demand hits @@ -29,6 +29,19 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.dir_cntrl0.memBuffer.memReq 650 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 547 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 103 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 365 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 117 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 117 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.180000 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 63 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 46 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memArbWait 8 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 26 4.00% 4.00% | 14 2.15% 6.15% | 0 0.00% 6.15% | 49 7.54% 13.69% | 21 3.23% 16.92% | 21 3.23% 20.15% | 42 6.46% 26.62% | 25 3.85% 30.46% | 6 0.92% 31.38% | 4 0.62% 32.00% | 7 1.08% 33.08% | 4 0.62% 33.69% | 24 3.69% 37.38% | 42 6.46% 43.85% | 26 4.00% 47.85% | 3 0.46% 48.31% | 5 0.77% 49.08% | 7 1.08% 50.15% | 7 1.08% 51.23% | 18 2.77% 54.00% | 10 1.54% 55.54% | 29 4.46% 60.00% | 15 2.31% 62.31% | 50 7.69% 70.00% | 19 2.92% 72.92% | 5 0.77% 73.69% | 6 0.92% 74.62% | 16 2.46% 77.08% | 14 2.15% 79.23% | 24 3.69% 82.92% | 19 2.92% 85.85% | 92 14.15% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 650 # Number of accesses per bank + system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -84,5 +97,79 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 52575 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles +system.ruby.l2_cntrl0.L1_GET_INSTR 300 0.00% 0.00% +system.ruby.l2_cntrl0.L1_GETS 204 0.00% 0.00% +system.ruby.l2_cntrl0.L1_GETX 68 0.00% 0.00% +system.ruby.l2_cntrl0.L1_PUTX 124 0.00% 0.00% +system.ruby.l2_cntrl0.L2_Replacement 43 0.00% 0.00% +system.ruby.l2_cntrl0.L2_Replacement_clean 496 0.00% 0.00% +system.ruby.l2_cntrl0.Mem_Data 547 0.00% 0.00% +system.ruby.l2_cntrl0.Mem_Ack 539 0.00% 0.00% +system.ruby.l2_cntrl0.WB_Data 62 0.00% 0.00% +system.ruby.l2_cntrl0.Ack_all 369 0.00% 0.00% +system.ruby.l2_cntrl0.Exclusive_Unblock 272 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GET_INSTR 291 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETS 192 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETX 64 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_GET_INSTR 9 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L2_Replacement_clean 286 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETS 12 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETX 4 0.00% 0.00% +system.ruby.l2_cntrl0.M.L2_Replacement 39 0.00% 0.00% +system.ruby.l2_cntrl0.M.L2_Replacement_clean 69 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L1_PUTX 124 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L2_Replacement 4 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L2_Replacement_clean 141 0.00% 0.00% +system.ruby.l2_cntrl0.M_I.Mem_Ack 539 0.00% 0.00% +system.ruby.l2_cntrl0.MT_I.WB_Data 2 0.00% 0.00% +system.ruby.l2_cntrl0.MT_I.Ack_all 2 0.00% 0.00% +system.ruby.l2_cntrl0.MCT_I.WB_Data 60 0.00% 0.00% +system.ruby.l2_cntrl0.MCT_I.Ack_all 81 0.00% 0.00% +system.ruby.l2_cntrl0.I_I.Ack_all 286 0.00% 0.00% +system.ruby.l2_cntrl0.ISS.Mem_Data 192 0.00% 0.00% +system.ruby.l2_cntrl0.IS.Mem_Data 291 0.00% 0.00% +system.ruby.l2_cntrl0.IM.Mem_Data 64 0.00% 0.00% +system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 272 0.00% 0.00% +system.ruby.l1_cntrl0.Load 415 0.00% 0.00% +system.ruby.l1_cntrl0.Ifetch 2585 0.00% 0.00% +system.ruby.l1_cntrl0.Store 294 0.00% 0.00% +system.ruby.l1_cntrl0.Inv 431 0.00% 0.00% +system.ruby.l1_cntrl0.L1_Replacement 502 0.00% 0.00% +system.ruby.l1_cntrl0.Data_Exclusive 204 0.00% 0.00% +system.ruby.l1_cntrl0.Data_all_Acks 368 0.00% 0.00% +system.ruby.l1_cntrl0.WB_Ack 124 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Load 182 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Ifetch 270 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Store 58 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Inv 162 0.00% 0.00% +system.ruby.l1_cntrl0.I.Load 22 0.00% 0.00% +system.ruby.l1_cntrl0.I.Ifetch 30 0.00% 0.00% +system.ruby.l1_cntrl0.I.Store 10 0.00% 0.00% +system.ruby.l1_cntrl0.I.L1_Replacement 206 0.00% 0.00% +system.ruby.l1_cntrl0.S.Ifetch 2285 0.00% 0.00% +system.ruby.l1_cntrl0.S.Inv 124 0.00% 0.00% +system.ruby.l1_cntrl0.S.L1_Replacement 172 0.00% 0.00% +system.ruby.l1_cntrl0.E.Load 140 0.00% 0.00% +system.ruby.l1_cntrl0.E.Store 41 0.00% 0.00% +system.ruby.l1_cntrl0.E.Inv 83 0.00% 0.00% +system.ruby.l1_cntrl0.E.L1_Replacement 79 0.00% 0.00% +system.ruby.l1_cntrl0.M.Load 71 0.00% 0.00% +system.ruby.l1_cntrl0.M.Store 185 0.00% 0.00% +system.ruby.l1_cntrl0.M.Inv 62 0.00% 0.00% +system.ruby.l1_cntrl0.M.L1_Replacement 45 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data_Exclusive 204 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data_all_Acks 300 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Data_all_Acks 68 0.00% 0.00% +system.ruby.l1_cntrl0.M_I.WB_Ack 124 0.00% 0.00% +system.ruby.dir_cntrl0.Fetch 547 0.00% 0.00% +system.ruby.dir_cntrl0.Data 103 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 547 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 103 0.00% 0.00% +system.ruby.dir_cntrl0.CleanReplacement 436 0.00% 0.00% +system.ruby.dir_cntrl0.I.Fetch 547 0.00% 0.00% +system.ruby.dir_cntrl0.M.Data 103 0.00% 0.00% +system.ruby.dir_cntrl0.M.CleanReplacement 436 0.00% 0.00% +system.ruby.dir_cntrl0.IM.Memory_Data 547 0.00% 0.00% +system.ruby.dir_cntrl0.MI.Memory_Ack 103 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats index 1cbdf7fce..619a67ae6 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats @@ -1,4 +1,4 @@ -Real time: Mar/06/2013 20:42:20 +Real time: Jun/08/2013 14:13:05 Profiler Stats -------------- @@ -7,20 +7,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.58 -Virtual_time_in_minutes: 0.00966667 -Virtual_time_in_hours: 0.000161111 -Virtual_time_in_days: 6.71296e-06 +Virtual_time_in_seconds: 0.51 +Virtual_time_in_minutes: 0.0085 +Virtual_time_in_hours: 0.000141667 +Virtual_time_in_days: 5.90278e-06 Ruby_current_time: 44968 Ruby_start_time: 0 Ruby_cycles: 44968 -mbytes_resident: 53.8398 -mbytes_total: 145.961 -resident_ratio: 0.368918 - -ruby_cycles_executed: [ 44969 ] +mbytes_resident: 55.6133 +mbytes_total: 143.102 +resident_ratio: 0.388683 Busy Controller Counts: L1Cache-0:0 @@ -61,7 +59,6 @@ Request vs. RubySystem State Profile -------------------------------- -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- @@ -82,11 +79,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11071 +page_reclaims: 11425 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 96 +block_outputs: 88 Network Stats ------------- @@ -164,1246 +161,3 @@ links_utilized_percent_switch_3: 6.52835 outgoing_messages_switch_3_link_2_Writeback_Control: 738 5904 [ 0 407 331 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Unblock_Control: 423 3384 [ 0 0 423 0 0 0 0 0 0 0 ] base_latency: 1 - --- L1Cache --- - - Event Counts - -Load [415 ] 415 -Ifetch [2585 ] 2585 -Store [294 ] 294 -L1_Replacement [506 ] 506 -Own_GETX [0 ] 0 -Fwd_GETX [0 ] 0 -Fwd_GETS [0 ] 0 -Fwd_DMA [0 ] 0 -Inv [0 ] 0 -Ack [0 ] 0 -Data [0 ] 0 -Exclusive_Data [510 ] 510 -Writeback_Ack [0 ] 0 -Writeback_Ack_Data [502 ] 502 -Writeback_Nack [0 ] 0 -All_acks [58 ] 58 -Use_Timeout [509 ] 509 - - - Transitions - -I Load [182 ] 182 -I Ifetch [270 ] 270 -I Store [58 ] 58 -I L1_Replacement [0 ] 0 -I Inv [0 ] 0 - -S Load [0 ] 0 -S Ifetch [0 ] 0 -S Store [0 ] 0 -S L1_Replacement [0 ] 0 -S Fwd_GETS [0 ] 0 -S Fwd_DMA [0 ] 0 -S Inv [0 ] 0 - -O Load [0 ] 0 -O Ifetch [0 ] 0 -O Store [0 ] 0 -O L1_Replacement [0 ] 0 -O Fwd_GETX [0 ] 0 -O Fwd_GETS [0 ] 0 -O Fwd_DMA [0 ] 0 - -M Load [82 ] 82 -M Ifetch [1220 ] 1220 -M Store [33 ] 33 -M L1_Replacement [406 ] 406 -M Fwd_GETX [0 ] 0 -M Fwd_GETS [0 ] 0 -M Fwd_DMA [0 ] 0 - -M_W Load [49 ] 49 -M_W Ifetch [1095 ] 1095 -M_W Store [7 ] 7 -M_W L1_Replacement [4 ] 4 -M_W Own_GETX [0 ] 0 -M_W Fwd_GETX [0 ] 0 -M_W Fwd_GETS [0 ] 0 -M_W Fwd_DMA [0 ] 0 -M_W Inv [0 ] 0 -M_W Use_Timeout [444 ] 444 - -MM Load [99 ] 99 -MM Ifetch [0 ] 0 -MM Store [114 ] 114 -MM L1_Replacement [96 ] 96 -MM Fwd_GETX [0 ] 0 -MM Fwd_GETS [0 ] 0 -MM Fwd_DMA [0 ] 0 - -MM_W Load [3 ] 3 -MM_W Ifetch [0 ] 0 -MM_W Store [82 ] 82 -MM_W L1_Replacement [0 ] 0 -MM_W Own_GETX [0 ] 0 -MM_W Fwd_GETX [0 ] 0 -MM_W Fwd_GETS [0 ] 0 -MM_W Fwd_DMA [0 ] 0 -MM_W Inv [0 ] 0 -MM_W Use_Timeout [65 ] 65 - -IM Load [0 ] 0 -IM Ifetch [0 ] 0 -IM Store [0 ] 0 -IM L1_Replacement [0 ] 0 -IM Inv [0 ] 0 -IM Ack [0 ] 0 -IM Data [0 ] 0 -IM Exclusive_Data [58 ] 58 - -SM Load [0 ] 0 -SM Ifetch [0 ] 0 -SM Store [0 ] 0 -SM L1_Replacement [0 ] 0 -SM Fwd_GETS [0 ] 0 -SM Fwd_DMA [0 ] 0 -SM Inv [0 ] 0 -SM Ack [0 ] 0 -SM Data [0 ] 0 -SM Exclusive_Data [0 ] 0 - -OM Load [0 ] 0 -OM Ifetch [0 ] 0 -OM Store [0 ] 0 -OM L1_Replacement [0 ] 0 -OM Own_GETX [0 ] 0 -OM Fwd_GETX [0 ] 0 -OM Fwd_GETS [0 ] 0 -OM Fwd_DMA [0 ] 0 -OM Ack [0 ] 0 -OM All_acks [58 ] 58 - -IS Load [0 ] 0 -IS Ifetch [0 ] 0 -IS Store [0 ] 0 -IS L1_Replacement [0 ] 0 -IS Inv [0 ] 0 -IS Data [0 ] 0 -IS Exclusive_Data [452 ] 452 - -SI Load [0 ] 0 -SI Ifetch [0 ] 0 -SI Store [0 ] 0 -SI L1_Replacement [0 ] 0 -SI Fwd_GETS [0 ] 0 -SI Fwd_DMA [0 ] 0 -SI Inv [0 ] 0 -SI Writeback_Ack [0 ] 0 -SI Writeback_Ack_Data [0 ] 0 -SI Writeback_Nack [0 ] 0 - -OI Load [0 ] 0 -OI Ifetch [0 ] 0 -OI Store [0 ] 0 -OI L1_Replacement [0 ] 0 -OI Fwd_GETX [0 ] 0 -OI Fwd_GETS [0 ] 0 -OI Fwd_DMA [0 ] 0 -OI Writeback_Ack [0 ] 0 -OI Writeback_Ack_Data [0 ] 0 -OI Writeback_Nack [0 ] 0 - -MI Load [0 ] 0 -MI Ifetch [0 ] 0 -MI Store [0 ] 0 -MI L1_Replacement [0 ] 0 -MI Fwd_GETX [0 ] 0 -MI Fwd_GETS [0 ] 0 -MI Fwd_DMA [0 ] 0 -MI Writeback_Ack [0 ] 0 -MI Writeback_Ack_Data [502 ] 502 -MI Writeback_Nack [0 ] 0 - -II Load [0 ] 0 -II Ifetch [0 ] 0 -II Store [0 ] 0 -II L1_Replacement [0 ] 0 -II Inv [0 ] 0 -II Writeback_Ack [0 ] 0 -II Writeback_Ack_Data [0 ] 0 -II Writeback_Nack [0 ] 0 - - --- L2Cache --- - - Event Counts - -L1_GETS [454 ] 454 -L1_GETX [58 ] 58 -L1_PUTO [0 ] 0 -L1_PUTX [502 ] 502 -L1_PUTS_only [0 ] 0 -L1_PUTS [0 ] 0 -Fwd_GETX [0 ] 0 -Fwd_GETS [0 ] 0 -Fwd_DMA [0 ] 0 -Own_GETX [0 ] 0 -Inv [0 ] 0 -IntAck [0 ] 0 -ExtAck [0 ] 0 -All_Acks [43 ] 43 -Data [43 ] 43 -Data_Exclusive [380 ] 380 -L1_WBCLEANDATA [396 ] 396 -L1_WBDIRTYDATA [106 ] 106 -Writeback_Ack [407 ] 407 -Writeback_Nack [0 ] 0 -Unblock [0 ] 0 -Exclusive_Unblock [510 ] 510 -DmaAck [0 ] 0 -L2_Replacement [407 ] 407 - - - Transitions - -NP L1_GETS [380 ] 380 -NP L1_GETX [43 ] 43 -NP L1_PUTO [0 ] 0 -NP L1_PUTX [0 ] 0 -NP L1_PUTS [0 ] 0 -NP Inv [0 ] 0 - -I L1_GETS [0 ] 0 -I L1_GETX [0 ] 0 -I L1_PUTO [0 ] 0 -I L1_PUTX [0 ] 0 -I L1_PUTS [0 ] 0 -I Inv [0 ] 0 -I L2_Replacement [0 ] 0 - -ILS L1_GETS [0 ] 0 -ILS L1_GETX [0 ] 0 -ILS L1_PUTO [0 ] 0 -ILS L1_PUTX [0 ] 0 -ILS L1_PUTS_only [0 ] 0 -ILS L1_PUTS [0 ] 0 -ILS Inv [0 ] 0 -ILS L2_Replacement [0 ] 0 - -ILX L1_GETS [0 ] 0 -ILX L1_GETX [0 ] 0 -ILX L1_PUTO [0 ] 0 -ILX L1_PUTX [502 ] 502 -ILX L1_PUTS_only [0 ] 0 -ILX L1_PUTS [0 ] 0 -ILX Fwd_GETX [0 ] 0 -ILX Fwd_GETS [0 ] 0 -ILX Fwd_DMA [0 ] 0 -ILX Inv [0 ] 0 -ILX Data [0 ] 0 -ILX L2_Replacement [0 ] 0 - -ILO L1_GETS [0 ] 0 -ILO L1_GETX [0 ] 0 -ILO L1_PUTO [0 ] 0 -ILO L1_PUTX [0 ] 0 -ILO L1_PUTS [0 ] 0 -ILO Fwd_GETX [0 ] 0 -ILO Fwd_GETS [0 ] 0 -ILO Fwd_DMA [0 ] 0 -ILO Inv [0 ] 0 -ILO Data [0 ] 0 -ILO L2_Replacement [0 ] 0 - -ILOX L1_GETS [0 ] 0 -ILOX L1_GETX [0 ] 0 -ILOX L1_PUTO [0 ] 0 -ILOX L1_PUTX [0 ] 0 -ILOX L1_PUTS [0 ] 0 -ILOX Fwd_GETX [0 ] 0 -ILOX Fwd_GETS [0 ] 0 -ILOX Fwd_DMA [0 ] 0 -ILOX Data [0 ] 0 - -ILOS L1_GETS [0 ] 0 -ILOS L1_GETX [0 ] 0 -ILOS L1_PUTO [0 ] 0 -ILOS L1_PUTX [0 ] 0 -ILOS L1_PUTS_only [0 ] 0 -ILOS L1_PUTS [0 ] 0 -ILOS Fwd_GETX [0 ] 0 -ILOS Fwd_GETS [0 ] 0 -ILOS Fwd_DMA [0 ] 0 -ILOS Data [0 ] 0 -ILOS L2_Replacement [0 ] 0 - -ILOSX L1_GETS [0 ] 0 -ILOSX L1_GETX [0 ] 0 -ILOSX L1_PUTO [0 ] 0 -ILOSX L1_PUTX [0 ] 0 -ILOSX L1_PUTS_only [0 ] 0 -ILOSX L1_PUTS [0 ] 0 -ILOSX Fwd_GETX [0 ] 0 -ILOSX Fwd_GETS [0 ] 0 -ILOSX Fwd_DMA [0 ] 0 -ILOSX Data [0 ] 0 - -S L1_GETS [0 ] 0 -S L1_GETX [0 ] 0 -S L1_PUTX [0 ] 0 -S L1_PUTS [0 ] 0 -S Inv [0 ] 0 -S L2_Replacement [0 ] 0 - -O L1_GETS [0 ] 0 -O L1_GETX [0 ] 0 -O L1_PUTX [0 ] 0 -O Fwd_GETX [0 ] 0 -O Fwd_GETS [0 ] 0 -O Fwd_DMA [0 ] 0 -O L2_Replacement [0 ] 0 - -OLS L1_GETS [0 ] 0 -OLS L1_GETX [0 ] 0 -OLS L1_PUTX [0 ] 0 -OLS L1_PUTS_only [0 ] 0 -OLS L1_PUTS [0 ] 0 -OLS Fwd_GETX [0 ] 0 -OLS Fwd_GETS [0 ] 0 -OLS Fwd_DMA [0 ] 0 -OLS L2_Replacement [0 ] 0 - -OLSX L1_GETS [0 ] 0 -OLSX L1_GETX [0 ] 0 -OLSX L1_PUTO [0 ] 0 -OLSX L1_PUTX [0 ] 0 -OLSX L1_PUTS_only [0 ] 0 -OLSX L1_PUTS [0 ] 0 -OLSX Fwd_GETX [0 ] 0 -OLSX Fwd_GETS [0 ] 0 -OLSX Fwd_DMA [0 ] 0 -OLSX L2_Replacement [0 ] 0 - -SLS L1_GETS [0 ] 0 -SLS L1_GETX [0 ] 0 -SLS L1_PUTX [0 ] 0 -SLS L1_PUTS_only [0 ] 0 -SLS L1_PUTS [0 ] 0 -SLS Inv [0 ] 0 -SLS L2_Replacement [0 ] 0 - -M L1_GETS [72 ] 72 -M L1_GETX [15 ] 15 -M L1_PUTO [0 ] 0 -M L1_PUTX [0 ] 0 -M L1_PUTS [0 ] 0 -M Fwd_GETX [0 ] 0 -M Fwd_GETS [0 ] 0 -M Fwd_DMA [0 ] 0 -M L2_Replacement [407 ] 407 - -IFGX L1_GETS [0 ] 0 -IFGX L1_GETX [0 ] 0 -IFGX L1_PUTO [0 ] 0 -IFGX L1_PUTX [0 ] 0 -IFGX L1_PUTS_only [0 ] 0 -IFGX L1_PUTS [0 ] 0 -IFGX Fwd_GETX [0 ] 0 -IFGX Fwd_GETS [0 ] 0 -IFGX Fwd_DMA [0 ] 0 -IFGX Inv [0 ] 0 -IFGX Data [0 ] 0 -IFGX Data_Exclusive [0 ] 0 -IFGX L2_Replacement [0 ] 0 - -IFGS L1_GETS [0 ] 0 -IFGS L1_GETX [0 ] 0 -IFGS L1_PUTO [0 ] 0 -IFGS L1_PUTX [0 ] 0 -IFGS L1_PUTS_only [0 ] 0 -IFGS L1_PUTS [0 ] 0 -IFGS Fwd_GETX [0 ] 0 -IFGS Fwd_GETS [0 ] 0 -IFGS Fwd_DMA [0 ] 0 -IFGS Inv [0 ] 0 -IFGS Data [0 ] 0 -IFGS Data_Exclusive [0 ] 0 -IFGS L2_Replacement [0 ] 0 - -ISFGS L1_GETS [0 ] 0 -ISFGS L1_GETX [0 ] 0 -ISFGS L1_PUTO [0 ] 0 -ISFGS L1_PUTX [0 ] 0 -ISFGS L1_PUTS_only [0 ] 0 -ISFGS L1_PUTS [0 ] 0 -ISFGS Fwd_GETX [0 ] 0 -ISFGS Fwd_GETS [0 ] 0 -ISFGS Fwd_DMA [0 ] 0 -ISFGS Inv [0 ] 0 -ISFGS Data [0 ] 0 -ISFGS L2_Replacement [0 ] 0 - -IFGXX L1_GETS [0 ] 0 -IFGXX L1_GETX [0 ] 0 -IFGXX L1_PUTO [0 ] 0 -IFGXX L1_PUTX [0 ] 0 -IFGXX L1_PUTS_only [0 ] 0 -IFGXX L1_PUTS [0 ] 0 -IFGXX Fwd_GETX [0 ] 0 -IFGXX Fwd_GETS [0 ] 0 -IFGXX Fwd_DMA [0 ] 0 -IFGXX Inv [0 ] 0 -IFGXX IntAck [0 ] 0 -IFGXX All_Acks [0 ] 0 -IFGXX Data_Exclusive [0 ] 0 -IFGXX L2_Replacement [0 ] 0 - -OFGX L1_GETS [0 ] 0 -OFGX L1_GETX [0 ] 0 -OFGX L1_PUTO [0 ] 0 -OFGX L1_PUTX [0 ] 0 -OFGX L1_PUTS_only [0 ] 0 -OFGX L1_PUTS [0 ] 0 -OFGX Fwd_GETX [0 ] 0 -OFGX Fwd_GETS [0 ] 0 -OFGX Fwd_DMA [0 ] 0 -OFGX Inv [0 ] 0 -OFGX L2_Replacement [0 ] 0 - -OLSF L1_GETS [0 ] 0 -OLSF L1_GETX [0 ] 0 -OLSF L1_PUTO [0 ] 0 -OLSF L1_PUTX [0 ] 0 -OLSF L1_PUTS_only [0 ] 0 -OLSF L1_PUTS [0 ] 0 -OLSF Fwd_GETX [0 ] 0 -OLSF Fwd_GETS [0 ] 0 -OLSF Fwd_DMA [0 ] 0 -OLSF Inv [0 ] 0 -OLSF IntAck [0 ] 0 -OLSF All_Acks [0 ] 0 -OLSF L2_Replacement [0 ] 0 - -ILOW L1_GETS [0 ] 0 -ILOW L1_GETX [0 ] 0 -ILOW L1_PUTO [0 ] 0 -ILOW L1_PUTX [0 ] 0 -ILOW L1_PUTS_only [0 ] 0 -ILOW L1_PUTS [0 ] 0 -ILOW Fwd_GETX [0 ] 0 -ILOW Fwd_GETS [0 ] 0 -ILOW Fwd_DMA [0 ] 0 -ILOW Inv [0 ] 0 -ILOW L1_WBCLEANDATA [0 ] 0 -ILOW L1_WBDIRTYDATA [0 ] 0 -ILOW Unblock [0 ] 0 -ILOW L2_Replacement [0 ] 0 - -ILOXW L1_GETS [0 ] 0 -ILOXW L1_GETX [0 ] 0 -ILOXW L1_PUTO [0 ] 0 -ILOXW L1_PUTX [0 ] 0 -ILOXW L1_PUTS_only [0 ] 0 -ILOXW L1_PUTS [0 ] 0 -ILOXW Fwd_GETX [0 ] 0 -ILOXW Fwd_GETS [0 ] 0 -ILOXW Fwd_DMA [0 ] 0 -ILOXW Inv [0 ] 0 -ILOXW L1_WBCLEANDATA [0 ] 0 -ILOXW L1_WBDIRTYDATA [0 ] 0 -ILOXW Unblock [0 ] 0 -ILOXW L2_Replacement [0 ] 0 - -ILOSW L1_GETS [0 ] 0 -ILOSW L1_GETX [0 ] 0 -ILOSW L1_PUTO [0 ] 0 -ILOSW L1_PUTX [0 ] 0 -ILOSW L1_PUTS_only [0 ] 0 -ILOSW L1_PUTS [0 ] 0 -ILOSW Fwd_GETX [0 ] 0 -ILOSW Fwd_GETS [0 ] 0 -ILOSW Fwd_DMA [0 ] 0 -ILOSW Inv [0 ] 0 -ILOSW L1_WBCLEANDATA [0 ] 0 -ILOSW L1_WBDIRTYDATA [0 ] 0 -ILOSW Unblock [0 ] 0 -ILOSW L2_Replacement [0 ] 0 - -ILOSXW L1_GETS [0 ] 0 -ILOSXW L1_GETX [0 ] 0 -ILOSXW L1_PUTO [0 ] 0 -ILOSXW L1_PUTX [0 ] 0 -ILOSXW L1_PUTS_only [0 ] 0 -ILOSXW L1_PUTS [0 ] 0 -ILOSXW Fwd_GETX [0 ] 0 -ILOSXW Fwd_GETS [0 ] 0 -ILOSXW Fwd_DMA [0 ] 0 -ILOSXW Inv [0 ] 0 -ILOSXW L1_WBCLEANDATA [0 ] 0 -ILOSXW L1_WBDIRTYDATA [0 ] 0 -ILOSXW Unblock [0 ] 0 -ILOSXW L2_Replacement [0 ] 0 - -SLSW L1_GETS [0 ] 0 -SLSW L1_GETX [0 ] 0 -SLSW L1_PUTO [0 ] 0 -SLSW L1_PUTX [0 ] 0 -SLSW L1_PUTS_only [0 ] 0 -SLSW L1_PUTS [0 ] 0 -SLSW Fwd_GETX [0 ] 0 -SLSW Fwd_GETS [0 ] 0 -SLSW Fwd_DMA [0 ] 0 -SLSW Inv [0 ] 0 -SLSW Unblock [0 ] 0 -SLSW L2_Replacement [0 ] 0 - -OLSW L1_GETS [0 ] 0 -OLSW L1_GETX [0 ] 0 -OLSW L1_PUTO [0 ] 0 -OLSW L1_PUTX [0 ] 0 -OLSW L1_PUTS_only [0 ] 0 -OLSW L1_PUTS [0 ] 0 -OLSW Fwd_GETX [0 ] 0 -OLSW Fwd_GETS [0 ] 0 -OLSW Fwd_DMA [0 ] 0 -OLSW Inv [0 ] 0 -OLSW Unblock [0 ] 0 -OLSW L2_Replacement [0 ] 0 - -ILSW L1_GETS [0 ] 0 -ILSW L1_GETX [0 ] 0 -ILSW L1_PUTO [0 ] 0 -ILSW L1_PUTX [0 ] 0 -ILSW L1_PUTS_only [0 ] 0 -ILSW L1_PUTS [0 ] 0 -ILSW Fwd_GETX [0 ] 0 -ILSW Fwd_GETS [0 ] 0 -ILSW Fwd_DMA [0 ] 0 -ILSW Inv [0 ] 0 -ILSW L1_WBCLEANDATA [0 ] 0 -ILSW Unblock [0 ] 0 -ILSW L2_Replacement [0 ] 0 - -IW L1_GETS [0 ] 0 -IW L1_GETX [0 ] 0 -IW L1_PUTO [0 ] 0 -IW L1_PUTX [0 ] 0 -IW L1_PUTS_only [0 ] 0 -IW L1_PUTS [0 ] 0 -IW Fwd_GETX [0 ] 0 -IW Fwd_GETS [0 ] 0 -IW Fwd_DMA [0 ] 0 -IW Inv [0 ] 0 -IW L1_WBCLEANDATA [0 ] 0 -IW L2_Replacement [0 ] 0 - -OW L1_GETS [0 ] 0 -OW L1_GETX [0 ] 0 -OW L1_PUTO [0 ] 0 -OW L1_PUTX [0 ] 0 -OW L1_PUTS_only [0 ] 0 -OW L1_PUTS [0 ] 0 -OW Fwd_GETX [0 ] 0 -OW Fwd_GETS [0 ] 0 -OW Fwd_DMA [0 ] 0 -OW Inv [0 ] 0 -OW Unblock [0 ] 0 -OW L2_Replacement [0 ] 0 - -SW L1_GETS [0 ] 0 -SW L1_GETX [0 ] 0 -SW L1_PUTO [0 ] 0 -SW L1_PUTX [0 ] 0 -SW L1_PUTS_only [0 ] 0 -SW L1_PUTS [0 ] 0 -SW Fwd_GETX [0 ] 0 -SW Fwd_GETS [0 ] 0 -SW Fwd_DMA [0 ] 0 -SW Inv [0 ] 0 -SW Unblock [0 ] 0 -SW L2_Replacement [0 ] 0 - -OXW L1_GETS [0 ] 0 -OXW L1_GETX [0 ] 0 -OXW L1_PUTO [0 ] 0 -OXW L1_PUTX [0 ] 0 -OXW L1_PUTS_only [0 ] 0 -OXW L1_PUTS [0 ] 0 -OXW Fwd_GETX [0 ] 0 -OXW Fwd_GETS [0 ] 0 -OXW Fwd_DMA [0 ] 0 -OXW Inv [0 ] 0 -OXW Unblock [0 ] 0 -OXW L2_Replacement [0 ] 0 - -OLSXW L1_GETS [0 ] 0 -OLSXW L1_GETX [0 ] 0 -OLSXW L1_PUTO [0 ] 0 -OLSXW L1_PUTX [0 ] 0 -OLSXW L1_PUTS_only [0 ] 0 -OLSXW L1_PUTS [0 ] 0 -OLSXW Fwd_GETX [0 ] 0 -OLSXW Fwd_GETS [0 ] 0 -OLSXW Fwd_DMA [0 ] 0 -OLSXW Inv [0 ] 0 -OLSXW Unblock [0 ] 0 -OLSXW L2_Replacement [0 ] 0 - -ILXW L1_GETS [0 ] 0 -ILXW L1_GETX [0 ] 0 -ILXW L1_PUTO [0 ] 0 -ILXW L1_PUTX [0 ] 0 -ILXW L1_PUTS_only [0 ] 0 -ILXW L1_PUTS [0 ] 0 -ILXW Fwd_GETX [0 ] 0 -ILXW Fwd_GETS [0 ] 0 -ILXW Fwd_DMA [0 ] 0 -ILXW Inv [0 ] 0 -ILXW Data [0 ] 0 -ILXW L1_WBCLEANDATA [396 ] 396 -ILXW L1_WBDIRTYDATA [106 ] 106 -ILXW Unblock [0 ] 0 -ILXW L2_Replacement [0 ] 0 - -IFLS L1_GETS [0 ] 0 -IFLS L1_GETX [0 ] 0 -IFLS L1_PUTO [0 ] 0 -IFLS L1_PUTX [0 ] 0 -IFLS L1_PUTS_only [0 ] 0 -IFLS L1_PUTS [0 ] 0 -IFLS Fwd_GETX [0 ] 0 -IFLS Fwd_GETS [0 ] 0 -IFLS Fwd_DMA [0 ] 0 -IFLS Inv [0 ] 0 -IFLS Unblock [0 ] 0 -IFLS L2_Replacement [0 ] 0 - -IFLO L1_GETS [0 ] 0 -IFLO L1_GETX [0 ] 0 -IFLO L1_PUTO [0 ] 0 -IFLO L1_PUTX [0 ] 0 -IFLO L1_PUTS_only [0 ] 0 -IFLO L1_PUTS [0 ] 0 -IFLO Fwd_GETX [0 ] 0 -IFLO Fwd_GETS [0 ] 0 -IFLO Fwd_DMA [0 ] 0 -IFLO Inv [0 ] 0 -IFLO Unblock [0 ] 0 -IFLO L2_Replacement [0 ] 0 - -IFLOX L1_GETS [0 ] 0 -IFLOX L1_GETX [0 ] 0 -IFLOX L1_PUTO [0 ] 0 -IFLOX L1_PUTX [0 ] 0 -IFLOX L1_PUTS_only [0 ] 0 -IFLOX L1_PUTS [0 ] 0 -IFLOX Fwd_GETX [0 ] 0 -IFLOX Fwd_GETS [0 ] 0 -IFLOX Fwd_DMA [0 ] 0 -IFLOX Inv [0 ] 0 -IFLOX Unblock [0 ] 0 -IFLOX Exclusive_Unblock [0 ] 0 -IFLOX L2_Replacement [0 ] 0 - -IFLOXX L1_GETS [0 ] 0 -IFLOXX L1_GETX [0 ] 0 -IFLOXX L1_PUTO [0 ] 0 -IFLOXX L1_PUTX [0 ] 0 -IFLOXX L1_PUTS_only [0 ] 0 -IFLOXX L1_PUTS [0 ] 0 -IFLOXX Fwd_GETX [0 ] 0 -IFLOXX Fwd_GETS [0 ] 0 -IFLOXX Fwd_DMA [0 ] 0 -IFLOXX Inv [0 ] 0 -IFLOXX Unblock [0 ] 0 -IFLOXX Exclusive_Unblock [0 ] 0 -IFLOXX L2_Replacement [0 ] 0 - -IFLOSX L1_GETS [0 ] 0 -IFLOSX L1_GETX [0 ] 0 -IFLOSX L1_PUTO [0 ] 0 -IFLOSX L1_PUTX [0 ] 0 -IFLOSX L1_PUTS_only [0 ] 0 -IFLOSX L1_PUTS [0 ] 0 -IFLOSX Fwd_GETX [0 ] 0 -IFLOSX Fwd_GETS [0 ] 0 -IFLOSX Fwd_DMA [0 ] 0 -IFLOSX Inv [0 ] 0 -IFLOSX Unblock [0 ] 0 -IFLOSX Exclusive_Unblock [0 ] 0 -IFLOSX L2_Replacement [0 ] 0 - -IFLXO L1_GETS [0 ] 0 -IFLXO L1_GETX [0 ] 0 -IFLXO L1_PUTO [0 ] 0 -IFLXO L1_PUTX [0 ] 0 -IFLXO L1_PUTS_only [0 ] 0 -IFLXO L1_PUTS [0 ] 0 -IFLXO Fwd_GETX [0 ] 0 -IFLXO Fwd_GETS [0 ] 0 -IFLXO Fwd_DMA [0 ] 0 -IFLXO Inv [0 ] 0 -IFLXO Exclusive_Unblock [0 ] 0 -IFLXO L2_Replacement [0 ] 0 - -IGS L1_GETS [0 ] 0 -IGS L1_GETX [0 ] 0 -IGS L1_PUTO [0 ] 0 -IGS L1_PUTX [0 ] 0 -IGS L1_PUTS_only [0 ] 0 -IGS L1_PUTS [0 ] 0 -IGS Fwd_GETX [0 ] 0 -IGS Fwd_GETS [0 ] 0 -IGS Fwd_DMA [0 ] 0 -IGS Own_GETX [0 ] 0 -IGS Inv [0 ] 0 -IGS Data [0 ] 0 -IGS Data_Exclusive [380 ] 380 -IGS Unblock [0 ] 0 -IGS Exclusive_Unblock [380 ] 380 -IGS L2_Replacement [0 ] 0 - -IGM L1_GETS [0 ] 0 -IGM L1_GETX [0 ] 0 -IGM L1_PUTO [0 ] 0 -IGM L1_PUTX [0 ] 0 -IGM L1_PUTS_only [0 ] 0 -IGM L1_PUTS [0 ] 0 -IGM Fwd_GETX [0 ] 0 -IGM Fwd_GETS [0 ] 0 -IGM Fwd_DMA [0 ] 0 -IGM Own_GETX [0 ] 0 -IGM Inv [0 ] 0 -IGM ExtAck [0 ] 0 -IGM Data [43 ] 43 -IGM Data_Exclusive [0 ] 0 -IGM L2_Replacement [0 ] 0 - -IGMLS L1_GETS [0 ] 0 -IGMLS L1_GETX [0 ] 0 -IGMLS L1_PUTO [0 ] 0 -IGMLS L1_PUTX [0 ] 0 -IGMLS L1_PUTS_only [0 ] 0 -IGMLS L1_PUTS [0 ] 0 -IGMLS Inv [0 ] 0 -IGMLS IntAck [0 ] 0 -IGMLS ExtAck [0 ] 0 -IGMLS All_Acks [0 ] 0 -IGMLS Data [0 ] 0 -IGMLS Data_Exclusive [0 ] 0 -IGMLS L2_Replacement [0 ] 0 - -IGMO L1_GETS [0 ] 0 -IGMO L1_GETX [0 ] 0 -IGMO L1_PUTO [0 ] 0 -IGMO L1_PUTX [0 ] 0 -IGMO L1_PUTS_only [0 ] 0 -IGMO L1_PUTS [0 ] 0 -IGMO Fwd_GETX [0 ] 0 -IGMO Fwd_GETS [0 ] 0 -IGMO Fwd_DMA [0 ] 0 -IGMO Own_GETX [0 ] 0 -IGMO ExtAck [0 ] 0 -IGMO All_Acks [43 ] 43 -IGMO Exclusive_Unblock [43 ] 43 -IGMO L2_Replacement [0 ] 0 - -IGMIO L1_GETS [0 ] 0 -IGMIO L1_GETX [0 ] 0 -IGMIO L1_PUTO [0 ] 0 -IGMIO L1_PUTX [0 ] 0 -IGMIO L1_PUTS_only [0 ] 0 -IGMIO L1_PUTS [0 ] 0 -IGMIO Fwd_GETX [0 ] 0 -IGMIO Fwd_GETS [0 ] 0 -IGMIO Fwd_DMA [0 ] 0 -IGMIO Own_GETX [0 ] 0 -IGMIO ExtAck [0 ] 0 -IGMIO All_Acks [0 ] 0 - -OGMIO L1_GETS [0 ] 0 -OGMIO L1_GETX [0 ] 0 -OGMIO L1_PUTO [0 ] 0 -OGMIO L1_PUTX [0 ] 0 -OGMIO L1_PUTS_only [0 ] 0 -OGMIO L1_PUTS [0 ] 0 -OGMIO Fwd_GETX [0 ] 0 -OGMIO Fwd_GETS [0 ] 0 -OGMIO Fwd_DMA [0 ] 0 -OGMIO Own_GETX [0 ] 0 -OGMIO ExtAck [0 ] 0 -OGMIO All_Acks [0 ] 0 - -IGMIOF L1_GETS [0 ] 0 -IGMIOF L1_GETX [0 ] 0 -IGMIOF L1_PUTO [0 ] 0 -IGMIOF L1_PUTX [0 ] 0 -IGMIOF L1_PUTS_only [0 ] 0 -IGMIOF L1_PUTS [0 ] 0 -IGMIOF IntAck [0 ] 0 -IGMIOF All_Acks [0 ] 0 -IGMIOF Data_Exclusive [0 ] 0 - -IGMIOFS L1_GETS [0 ] 0 -IGMIOFS L1_GETX [0 ] 0 -IGMIOFS L1_PUTO [0 ] 0 -IGMIOFS L1_PUTX [0 ] 0 -IGMIOFS L1_PUTS_only [0 ] 0 -IGMIOFS L1_PUTS [0 ] 0 -IGMIOFS Fwd_GETX [0 ] 0 -IGMIOFS Fwd_GETS [0 ] 0 -IGMIOFS Fwd_DMA [0 ] 0 -IGMIOFS Inv [0 ] 0 -IGMIOFS Data [0 ] 0 -IGMIOFS L2_Replacement [0 ] 0 - -OGMIOF L1_GETS [0 ] 0 -OGMIOF L1_GETX [0 ] 0 -OGMIOF L1_PUTO [0 ] 0 -OGMIOF L1_PUTX [0 ] 0 -OGMIOF L1_PUTS_only [0 ] 0 -OGMIOF L1_PUTS [0 ] 0 -OGMIOF IntAck [0 ] 0 -OGMIOF All_Acks [0 ] 0 - -II L1_GETS [0 ] 0 -II L1_GETX [0 ] 0 -II L1_PUTO [0 ] 0 -II L1_PUTX [0 ] 0 -II L1_PUTS_only [0 ] 0 -II L1_PUTS [0 ] 0 -II IntAck [0 ] 0 -II All_Acks [0 ] 0 - -MM L1_GETS [0 ] 0 -MM L1_GETX [0 ] 0 -MM L1_PUTO [0 ] 0 -MM L1_PUTX [0 ] 0 -MM L1_PUTS_only [0 ] 0 -MM L1_PUTS [0 ] 0 -MM Fwd_GETX [0 ] 0 -MM Fwd_GETS [0 ] 0 -MM Fwd_DMA [0 ] 0 -MM Inv [0 ] 0 -MM Exclusive_Unblock [15 ] 15 -MM L2_Replacement [0 ] 0 - -SS L1_GETS [0 ] 0 -SS L1_GETX [0 ] 0 -SS L1_PUTO [0 ] 0 -SS L1_PUTX [0 ] 0 -SS L1_PUTS_only [0 ] 0 -SS L1_PUTS [0 ] 0 -SS Fwd_GETX [0 ] 0 -SS Fwd_GETS [0 ] 0 -SS Fwd_DMA [0 ] 0 -SS Inv [0 ] 0 -SS Unblock [0 ] 0 -SS L2_Replacement [0 ] 0 - -OO L1_GETS [0 ] 0 -OO L1_GETX [0 ] 0 -OO L1_PUTO [0 ] 0 -OO L1_PUTX [0 ] 0 -OO L1_PUTS_only [0 ] 0 -OO L1_PUTS [0 ] 0 -OO Fwd_GETX [0 ] 0 -OO Fwd_GETS [0 ] 0 -OO Fwd_DMA [0 ] 0 -OO Inv [0 ] 0 -OO Unblock [0 ] 0 -OO Exclusive_Unblock [72 ] 72 -OO L2_Replacement [0 ] 0 - -OLSS L1_GETS [0 ] 0 -OLSS L1_GETX [0 ] 0 -OLSS L1_PUTO [0 ] 0 -OLSS L1_PUTX [0 ] 0 -OLSS L1_PUTS_only [0 ] 0 -OLSS L1_PUTS [0 ] 0 -OLSS Fwd_GETX [0 ] 0 -OLSS Fwd_GETS [0 ] 0 -OLSS Fwd_DMA [0 ] 0 -OLSS Inv [0 ] 0 -OLSS Unblock [0 ] 0 -OLSS L2_Replacement [0 ] 0 - -OLSXS L1_GETS [0 ] 0 -OLSXS L1_GETX [0 ] 0 -OLSXS L1_PUTO [0 ] 0 -OLSXS L1_PUTX [0 ] 0 -OLSXS L1_PUTS_only [0 ] 0 -OLSXS L1_PUTS [0 ] 0 -OLSXS Fwd_GETX [0 ] 0 -OLSXS Fwd_GETS [0 ] 0 -OLSXS Fwd_DMA [0 ] 0 -OLSXS Inv [0 ] 0 -OLSXS Unblock [0 ] 0 -OLSXS L2_Replacement [0 ] 0 - -SLSS L1_GETS [0 ] 0 -SLSS L1_GETX [0 ] 0 -SLSS L1_PUTO [0 ] 0 -SLSS L1_PUTX [0 ] 0 -SLSS L1_PUTS_only [0 ] 0 -SLSS L1_PUTS [0 ] 0 -SLSS Fwd_GETX [0 ] 0 -SLSS Fwd_GETS [0 ] 0 -SLSS Fwd_DMA [0 ] 0 -SLSS Inv [0 ] 0 -SLSS Unblock [0 ] 0 -SLSS L2_Replacement [0 ] 0 - -OI L1_GETS [0 ] 0 -OI L1_GETX [0 ] 0 -OI L1_PUTO [0 ] 0 -OI L1_PUTX [0 ] 0 -OI L1_PUTS_only [0 ] 0 -OI L1_PUTS [0 ] 0 -OI Fwd_GETX [0 ] 0 -OI Fwd_GETS [0 ] 0 -OI Fwd_DMA [0 ] 0 -OI Writeback_Ack [0 ] 0 -OI Writeback_Nack [0 ] 0 -OI L2_Replacement [0 ] 0 - -MI L1_GETS [2 ] 2 -MI L1_GETX [0 ] 0 -MI L1_PUTO [0 ] 0 -MI L1_PUTX [0 ] 0 -MI L1_PUTS_only [0 ] 0 -MI L1_PUTS [0 ] 0 -MI Fwd_GETX [0 ] 0 -MI Fwd_GETS [0 ] 0 -MI Fwd_DMA [0 ] 0 -MI Writeback_Ack [407 ] 407 -MI L2_Replacement [0 ] 0 - -MII L1_GETS [0 ] 0 -MII L1_GETX [0 ] 0 -MII L1_PUTO [0 ] 0 -MII L1_PUTX [0 ] 0 -MII L1_PUTS_only [0 ] 0 -MII L1_PUTS [0 ] 0 -MII Writeback_Ack [0 ] 0 -MII Writeback_Nack [0 ] 0 -MII L2_Replacement [0 ] 0 - -OLSI L1_GETS [0 ] 0 -OLSI L1_GETX [0 ] 0 -OLSI L1_PUTO [0 ] 0 -OLSI L1_PUTX [0 ] 0 -OLSI L1_PUTS_only [0 ] 0 -OLSI L1_PUTS [0 ] 0 -OLSI Fwd_GETX [0 ] 0 -OLSI Fwd_GETS [0 ] 0 -OLSI Fwd_DMA [0 ] 0 -OLSI Writeback_Ack [0 ] 0 -OLSI L2_Replacement [0 ] 0 - -ILSI L1_GETS [0 ] 0 -ILSI L1_GETX [0 ] 0 -ILSI L1_PUTO [0 ] 0 -ILSI L1_PUTX [0 ] 0 -ILSI L1_PUTS_only [0 ] 0 -ILSI L1_PUTS [0 ] 0 -ILSI IntAck [0 ] 0 -ILSI All_Acks [0 ] 0 -ILSI Writeback_Ack [0 ] 0 -ILSI L2_Replacement [0 ] 0 - -ILOSD L1_GETS [0 ] 0 -ILOSD L1_GETX [0 ] 0 -ILOSD L1_PUTO [0 ] 0 -ILOSD L1_PUTX [0 ] 0 -ILOSD L1_PUTS_only [0 ] 0 -ILOSD L1_PUTS [0 ] 0 -ILOSD Fwd_GETX [0 ] 0 -ILOSD Fwd_GETS [0 ] 0 -ILOSD Fwd_DMA [0 ] 0 -ILOSD Own_GETX [0 ] 0 -ILOSD Inv [0 ] 0 -ILOSD DmaAck [0 ] 0 -ILOSD L2_Replacement [0 ] 0 - -ILOSXD L1_GETS [0 ] 0 -ILOSXD L1_GETX [0 ] 0 -ILOSXD L1_PUTO [0 ] 0 -ILOSXD L1_PUTX [0 ] 0 -ILOSXD L1_PUTS_only [0 ] 0 -ILOSXD L1_PUTS [0 ] 0 -ILOSXD Fwd_GETX [0 ] 0 -ILOSXD Fwd_GETS [0 ] 0 -ILOSXD Fwd_DMA [0 ] 0 -ILOSXD Own_GETX [0 ] 0 -ILOSXD Inv [0 ] 0 -ILOSXD DmaAck [0 ] 0 -ILOSXD L2_Replacement [0 ] 0 - -ILOD L1_GETS [0 ] 0 -ILOD L1_GETX [0 ] 0 -ILOD L1_PUTO [0 ] 0 -ILOD L1_PUTX [0 ] 0 -ILOD L1_PUTS_only [0 ] 0 -ILOD L1_PUTS [0 ] 0 -ILOD Fwd_GETX [0 ] 0 -ILOD Fwd_GETS [0 ] 0 -ILOD Fwd_DMA [0 ] 0 -ILOD Own_GETX [0 ] 0 -ILOD Inv [0 ] 0 -ILOD DmaAck [0 ] 0 -ILOD L2_Replacement [0 ] 0 - -ILXD L1_GETS [0 ] 0 -ILXD L1_GETX [0 ] 0 -ILXD L1_PUTO [0 ] 0 -ILXD L1_PUTX [0 ] 0 -ILXD L1_PUTS_only [0 ] 0 -ILXD L1_PUTS [0 ] 0 -ILXD Fwd_GETX [0 ] 0 -ILXD Fwd_GETS [0 ] 0 -ILXD Fwd_DMA [0 ] 0 -ILXD Own_GETX [0 ] 0 -ILXD Inv [0 ] 0 -ILXD DmaAck [0 ] 0 -ILXD L2_Replacement [0 ] 0 - -ILOXD L1_GETS [0 ] 0 -ILOXD L1_GETX [0 ] 0 -ILOXD L1_PUTO [0 ] 0 -ILOXD L1_PUTX [0 ] 0 -ILOXD L1_PUTS_only [0 ] 0 -ILOXD L1_PUTS [0 ] 0 -ILOXD Fwd_GETX [0 ] 0 -ILOXD Fwd_GETS [0 ] 0 -ILOXD Fwd_DMA [0 ] 0 -ILOXD Own_GETX [0 ] 0 -ILOXD Inv [0 ] 0 -ILOXD DmaAck [0 ] 0 -ILOXD L2_Replacement [0 ] 0 - -Memory controller: system.ruby.dir_cntrl0.memBuffer: - memory_total_requests: 499 - memory_reads: 423 - memory_writes: 76 - memory_refreshes: 313 - memory_total_request_delays: 77 - memory_delays_per_request: 0.154309 - memory_delays_in_input_queue: 0 - memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 77 - memory_stalls_for_bank_busy: 41 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 9 - memory_stalls_for_bus: 25 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 2 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 18 10 0 34 20 19 28 21 5 3 6 4 21 40 20 3 4 5 7 13 10 16 14 41 15 5 5 12 12 18 14 56 - - --- Directory --- - - Event Counts - -GETX [43 ] 43 -GETS [380 ] 380 -PUTX [407 ] 407 -PUTO [0 ] 0 -PUTO_SHARERS [0 ] 0 -Unblock [0 ] 0 -Last_Unblock [0 ] 0 -Exclusive_Unblock [422 ] 422 -Clean_Writeback [331 ] 331 -Dirty_Writeback [76 ] 76 -Memory_Data [423 ] 423 -Memory_Ack [76 ] 76 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -DMA_ACK [0 ] 0 -Data [0 ] 0 - - - Transitions - -I GETX [43 ] 43 -I GETS [380 ] 380 -I PUTX [0 ] 0 -I PUTO [0 ] 0 -I Memory_Data [0 ] 0 -I Memory_Ack [74 ] 74 -I DMA_READ [0 ] 0 -I DMA_WRITE [0 ] 0 - -S GETX [0 ] 0 -S GETS [0 ] 0 -S PUTX [0 ] 0 -S PUTO [0 ] 0 -S Memory_Data [0 ] 0 -S Memory_Ack [0 ] 0 -S DMA_READ [0 ] 0 -S DMA_WRITE [0 ] 0 - -O GETX [0 ] 0 -O GETS [0 ] 0 -O PUTX [0 ] 0 -O PUTO [0 ] 0 -O PUTO_SHARERS [0 ] 0 -O Memory_Data [0 ] 0 -O Memory_Ack [0 ] 0 -O DMA_READ [0 ] 0 -O DMA_WRITE [0 ] 0 - -M GETX [0 ] 0 -M GETS [0 ] 0 -M PUTX [407 ] 407 -M PUTO [0 ] 0 -M PUTO_SHARERS [0 ] 0 -M Memory_Data [0 ] 0 -M Memory_Ack [0 ] 0 -M DMA_READ [0 ] 0 -M DMA_WRITE [0 ] 0 - -IS GETX [0 ] 0 -IS GETS [0 ] 0 -IS PUTX [0 ] 0 -IS PUTO [0 ] 0 -IS PUTO_SHARERS [0 ] 0 -IS Unblock [0 ] 0 -IS Exclusive_Unblock [379 ] 379 -IS Memory_Data [380 ] 380 -IS Memory_Ack [2 ] 2 -IS DMA_READ [0 ] 0 -IS DMA_WRITE [0 ] 0 - -SS GETX [0 ] 0 -SS GETS [0 ] 0 -SS PUTX [0 ] 0 -SS PUTO [0 ] 0 -SS PUTO_SHARERS [0 ] 0 -SS Unblock [0 ] 0 -SS Last_Unblock [0 ] 0 -SS Memory_Data [0 ] 0 -SS Memory_Ack [0 ] 0 -SS DMA_READ [0 ] 0 -SS DMA_WRITE [0 ] 0 - -OO GETX [0 ] 0 -OO GETS [0 ] 0 -OO PUTX [0 ] 0 -OO PUTO [0 ] 0 -OO PUTO_SHARERS [0 ] 0 -OO Unblock [0 ] 0 -OO Last_Unblock [0 ] 0 -OO Memory_Data [0 ] 0 -OO Memory_Ack [0 ] 0 -OO DMA_READ [0 ] 0 -OO DMA_WRITE [0 ] 0 - -MO GETX [0 ] 0 -MO GETS [0 ] 0 -MO PUTX [0 ] 0 -MO PUTO [0 ] 0 -MO PUTO_SHARERS [0 ] 0 -MO Unblock [0 ] 0 -MO Exclusive_Unblock [0 ] 0 -MO Memory_Data [0 ] 0 -MO Memory_Ack [0 ] 0 -MO DMA_READ [0 ] 0 -MO DMA_WRITE [0 ] 0 - -MM GETX [0 ] 0 -MM GETS [0 ] 0 -MM PUTX [0 ] 0 -MM PUTO [0 ] 0 -MM PUTO_SHARERS [0 ] 0 -MM Exclusive_Unblock [43 ] 43 -MM Memory_Data [43 ] 43 -MM Memory_Ack [0 ] 0 -MM DMA_READ [0 ] 0 -MM DMA_WRITE [0 ] 0 - - -MI GETX [0 ] 0 -MI GETS [0 ] 0 -MI PUTX [0 ] 0 -MI PUTO [0 ] 0 -MI PUTO_SHARERS [0 ] 0 -MI Unblock [0 ] 0 -MI Clean_Writeback [331 ] 331 -MI Dirty_Writeback [76 ] 76 -MI Memory_Data [0 ] 0 -MI Memory_Ack [0 ] 0 -MI DMA_READ [0 ] 0 -MI DMA_WRITE [0 ] 0 - -MIS GETX [0 ] 0 -MIS GETS [0 ] 0 -MIS PUTX [0 ] 0 -MIS PUTO [0 ] 0 -MIS PUTO_SHARERS [0 ] 0 -MIS Unblock [0 ] 0 -MIS Clean_Writeback [0 ] 0 -MIS Dirty_Writeback [0 ] 0 -MIS Memory_Data [0 ] 0 -MIS Memory_Ack [0 ] 0 -MIS DMA_READ [0 ] 0 -MIS DMA_WRITE [0 ] 0 - -OS GETX [0 ] 0 -OS GETS [0 ] 0 -OS PUTX [0 ] 0 -OS PUTO [0 ] 0 -OS PUTO_SHARERS [0 ] 0 -OS Unblock [0 ] 0 -OS Clean_Writeback [0 ] 0 -OS Dirty_Writeback [0 ] 0 -OS Memory_Data [0 ] 0 -OS Memory_Ack [0 ] 0 -OS DMA_READ [0 ] 0 -OS DMA_WRITE [0 ] 0 - -OSS GETX [0 ] 0 -OSS GETS [0 ] 0 -OSS PUTX [0 ] 0 -OSS PUTO [0 ] 0 -OSS PUTO_SHARERS [0 ] 0 -OSS Unblock [0 ] 0 -OSS Clean_Writeback [0 ] 0 -OSS Dirty_Writeback [0 ] 0 -OSS Memory_Data [0 ] 0 -OSS Memory_Ack [0 ] 0 -OSS DMA_READ [0 ] 0 -OSS DMA_WRITE [0 ] 0 - -XI_M GETX [0 ] 0 -XI_M GETS [0 ] 0 -XI_M PUTX [0 ] 0 -XI_M PUTO [0 ] 0 -XI_M PUTO_SHARERS [0 ] 0 -XI_M Memory_Data [0 ] 0 -XI_M Memory_Ack [0 ] 0 -XI_M DMA_READ [0 ] 0 -XI_M DMA_WRITE [0 ] 0 - -XI_U GETX [0 ] 0 -XI_U GETS [0 ] 0 -XI_U PUTX [0 ] 0 -XI_U PUTO [0 ] 0 -XI_U PUTO_SHARERS [0 ] 0 -XI_U Exclusive_Unblock [0 ] 0 -XI_U Memory_Ack [0 ] 0 -XI_U DMA_READ [0 ] 0 -XI_U DMA_WRITE [0 ] 0 - -OI_D GETX [0 ] 0 -OI_D GETS [0 ] 0 -OI_D PUTX [0 ] 0 -OI_D PUTO [0 ] 0 -OI_D PUTO_SHARERS [0 ] 0 -OI_D DMA_READ [0 ] 0 -OI_D DMA_WRITE [0 ] 0 -OI_D Data [0 ] 0 - -OD GETX [0 ] 0 -OD GETS [0 ] 0 -OD PUTX [0 ] 0 -OD PUTO [0 ] 0 -OD PUTO_SHARERS [0 ] 0 -OD DMA_READ [0 ] 0 -OD DMA_WRITE [0 ] 0 -OD DMA_ACK [0 ] 0 - -MD GETX [0 ] 0 -MD GETS [0 ] 0 -MD PUTX [0 ] 0 -MD PUTO [0 ] 0 -MD PUTO_SHARERS [0 ] 0 -MD DMA_READ [0 ] 0 -MD DMA_WRITE [0 ] 0 -MD DMA_ACK [0 ] 0 - diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 8f2c45ec9..fd5d57f08 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000045 # Nu sim_ticks 44968 # Number of ticks simulated final_tick 44968 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 13243 # Simulator instruction rate (inst/s) -host_op_rate 13241 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 231036 # Simulator tick rate (ticks/s) -host_mem_usage 152316 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 16391 # Simulator instruction rate (inst/s) +host_op_rate 16389 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 285944 # Simulator tick rate (ticks/s) +host_mem_usage 146540 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.ruby.l2_cntrl0.L2cache.demand_hits 87 # Number of cache demand hits @@ -20,6 +20,20 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses +system.ruby.dir_cntrl0.memBuffer.memReq 499 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 423 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 76 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 313 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 77 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 77 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.154309 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 41 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 25 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 2 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 9 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 18 3.61% 3.61% | 10 2.00% 5.61% | 0 0.00% 5.61% | 34 6.81% 12.42% | 20 4.01% 16.43% | 19 3.81% 20.24% | 28 5.61% 25.85% | 21 4.21% 30.06% | 5 1.00% 31.06% | 3 0.60% 31.66% | 6 1.20% 32.87% | 4 0.80% 33.67% | 21 4.21% 37.88% | 40 8.02% 45.89% | 20 4.01% 49.90% | 3 0.60% 50.50% | 4 0.80% 51.30% | 5 1.00% 52.30% | 7 1.40% 53.71% | 13 2.61% 56.31% | 10 2.00% 58.32% | 16 3.21% 61.52% | 14 2.81% 64.33% | 41 8.22% 72.55% | 15 3.01% 75.55% | 5 1.00% 76.55% | 5 1.00% 77.56% | 12 2.40% 79.96% | 12 2.40% 82.36% | 18 3.61% 85.97% | 14 2.81% 88.78% | 56 11.22% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 499 # Number of accesses per bank + system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -75,5 +89,82 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 44968 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles +system.ruby.l2_cntrl0.L1_GETS 454 0.00% 0.00% +system.ruby.l2_cntrl0.L1_GETX 58 0.00% 0.00% +system.ruby.l2_cntrl0.L1_PUTX 502 0.00% 0.00% +system.ruby.l2_cntrl0.All_Acks 43 0.00% 0.00% +system.ruby.l2_cntrl0.Data 43 0.00% 0.00% +system.ruby.l2_cntrl0.Data_Exclusive 380 0.00% 0.00% +system.ruby.l2_cntrl0.L1_WBCLEANDATA 396 0.00% 0.00% +system.ruby.l2_cntrl0.L1_WBDIRTYDATA 106 0.00% 0.00% +system.ruby.l2_cntrl0.Writeback_Ack 407 0.00% 0.00% +system.ruby.l2_cntrl0.Exclusive_Unblock 510 0.00% 0.00% +system.ruby.l2_cntrl0.L2_Replacement 407 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETS 380 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETX 43 0.00% 0.00% +system.ruby.l2_cntrl0.ILX.L1_PUTX 502 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETS 72 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETX 15 0.00% 0.00% +system.ruby.l2_cntrl0.M.L2_Replacement 407 0.00% 0.00% +system.ruby.l2_cntrl0.ILXW.L1_WBCLEANDATA 396 0.00% 0.00% +system.ruby.l2_cntrl0.ILXW.L1_WBDIRTYDATA 106 0.00% 0.00% +system.ruby.l2_cntrl0.IGS.Data_Exclusive 380 0.00% 0.00% +system.ruby.l2_cntrl0.IGS.Exclusive_Unblock 380 0.00% 0.00% +system.ruby.l2_cntrl0.IGM.Data 43 0.00% 0.00% +system.ruby.l2_cntrl0.IGMO.All_Acks 43 0.00% 0.00% +system.ruby.l2_cntrl0.IGMO.Exclusive_Unblock 43 0.00% 0.00% +system.ruby.l2_cntrl0.MM.Exclusive_Unblock 15 0.00% 0.00% +system.ruby.l2_cntrl0.OO.Exclusive_Unblock 72 0.00% 0.00% +system.ruby.l2_cntrl0.MI.L1_GETS 2 0.00% 0.00% +system.ruby.l2_cntrl0.MI.Writeback_Ack 407 0.00% 0.00% +system.ruby.l1_cntrl0.Load 415 0.00% 0.00% +system.ruby.l1_cntrl0.Ifetch 2585 0.00% 0.00% +system.ruby.l1_cntrl0.Store 294 0.00% 0.00% +system.ruby.l1_cntrl0.L1_Replacement 506 0.00% 0.00% +system.ruby.l1_cntrl0.Exclusive_Data 510 0.00% 0.00% +system.ruby.l1_cntrl0.Writeback_Ack_Data 502 0.00% 0.00% +system.ruby.l1_cntrl0.All_acks 58 0.00% 0.00% +system.ruby.l1_cntrl0.Use_Timeout 509 0.00% 0.00% +system.ruby.l1_cntrl0.I.Load 182 0.00% 0.00% +system.ruby.l1_cntrl0.I.Ifetch 270 0.00% 0.00% +system.ruby.l1_cntrl0.I.Store 58 0.00% 0.00% +system.ruby.l1_cntrl0.M.Load 82 0.00% 0.00% +system.ruby.l1_cntrl0.M.Ifetch 1220 0.00% 0.00% +system.ruby.l1_cntrl0.M.Store 33 0.00% 0.00% +system.ruby.l1_cntrl0.M.L1_Replacement 406 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.Load 49 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.Ifetch 1095 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.Store 7 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.L1_Replacement 4 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.Use_Timeout 444 0.00% 0.00% +system.ruby.l1_cntrl0.MM.Load 99 0.00% 0.00% +system.ruby.l1_cntrl0.MM.Store 114 0.00% 0.00% +system.ruby.l1_cntrl0.MM.L1_Replacement 96 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.Load 3 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.Store 82 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.Use_Timeout 65 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Exclusive_Data 58 0.00% 0.00% +system.ruby.l1_cntrl0.OM.All_acks 58 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Exclusive_Data 452 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Writeback_Ack_Data 502 0.00% 0.00% +system.ruby.dir_cntrl0.GETX 43 0.00% 0.00% +system.ruby.dir_cntrl0.GETS 380 0.00% 0.00% +system.ruby.dir_cntrl0.PUTX 407 0.00% 0.00% +system.ruby.dir_cntrl0.Exclusive_Unblock 422 0.00% 0.00% +system.ruby.dir_cntrl0.Clean_Writeback 331 0.00% 0.00% +system.ruby.dir_cntrl0.Dirty_Writeback 76 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 423 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 76 0.00% 0.00% +system.ruby.dir_cntrl0.I.GETX 43 0.00% 0.00% +system.ruby.dir_cntrl0.I.GETS 380 0.00% 0.00% +system.ruby.dir_cntrl0.I.Memory_Ack 74 0.00% 0.00% +system.ruby.dir_cntrl0.M.PUTX 407 0.00% 0.00% +system.ruby.dir_cntrl0.IS.Exclusive_Unblock 379 0.00% 0.00% +system.ruby.dir_cntrl0.IS.Memory_Data 380 0.00% 0.00% +system.ruby.dir_cntrl0.IS.Memory_Ack 2 0.00% 0.00% +system.ruby.dir_cntrl0.MM.Exclusive_Unblock 43 0.00% 0.00% +system.ruby.dir_cntrl0.MM.Memory_Data 43 0.00% 0.00% +system.ruby.dir_cntrl0.MI.Clean_Writeback 331 0.00% 0.00% +system.ruby.dir_cntrl0.MI.Dirty_Writeback 76 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats index 8d7b50556..ac8013811 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats @@ -1,4 +1,4 @@ -Real time: Mar/06/2013 20:46:06 +Real time: Jun/08/2013 14:14:46 Profiler Stats -------------- @@ -7,20 +7,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.55 -Virtual_time_in_minutes: 0.00916667 -Virtual_time_in_hours: 0.000152778 -Virtual_time_in_days: 6.36574e-06 +Virtual_time_in_seconds: 0.47 +Virtual_time_in_minutes: 0.00783333 +Virtual_time_in_hours: 0.000130556 +Virtual_time_in_days: 5.43981e-06 Ruby_current_time: 43073 Ruby_start_time: 0 Ruby_cycles: 43073 -mbytes_resident: 53.1133 -mbytes_total: 144.906 -resident_ratio: 0.366562 - -ruby_cycles_executed: [ 43074 ] +mbytes_resident: 53.543 +mbytes_total: 140.984 +resident_ratio: 0.379835 Busy Controller Counts: L1Cache-0:0 @@ -69,7 +67,6 @@ Request vs. RubySystem State Profile -------------------------------- -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- @@ -90,7 +87,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11916 +page_reclaims: 10919 page_faults: 0 swaps: 0 block_inputs: 0 @@ -160,805 +157,3 @@ links_utilized_percent_switch_3: 4.36236 outgoing_messages_switch_3_link_2_Writeback_Data: 84 6048 [ 0 0 0 0 84 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Writeback_Control: 365 2920 [ 0 0 0 0 365 0 0 0 0 0 ] base_latency: 1 - --- L1Cache --- - - Event Counts - -Load [415 ] 415 -Ifetch [2585 ] 2585 -Store [294 ] 294 -Atomic [0 ] 0 -L1_Replacement [504 ] 504 -Data_Shared [56 ] 56 -Data_Owner [0 ] 0 -Data_All_Tokens [462 ] 462 -Ack [1 ] 1 -Ack_All_Tokens [0 ] 0 -Transient_GETX [0 ] 0 -Transient_Local_GETX [0 ] 0 -Transient_GETS [0 ] 0 -Transient_Local_GETS [0 ] 0 -Transient_GETS_Last_Token [0 ] 0 -Transient_Local_GETS_Last_Token [0 ] 0 -Persistent_GETX [0 ] 0 -Persistent_GETS [0 ] 0 -Persistent_GETS_Last_Token [0 ] 0 -Own_Lock_or_Unlock [0 ] 0 -Request_Timeout [0 ] 0 -Use_TimeoutStarverX [0 ] 0 -Use_TimeoutStarverS [0 ] 0 -Use_TimeoutNoStarvers [461 ] 461 -Use_TimeoutNoStarvers_NoMig [0 ] 0 - - - Transitions - -NP Load [182 ] 182 -NP Ifetch [270 ] 270 -NP Store [58 ] 58 -NP Atomic [0 ] 0 -NP Data_Shared [0 ] 0 -NP Data_Owner [0 ] 0 -NP Data_All_Tokens [0 ] 0 -NP Ack [0 ] 0 -NP Transient_GETX [0 ] 0 -NP Transient_Local_GETX [0 ] 0 -NP Transient_GETS [0 ] 0 -NP Transient_Local_GETS [0 ] 0 -NP Persistent_GETX [0 ] 0 -NP Persistent_GETS [0 ] 0 -NP Persistent_GETS_Last_Token [0 ] 0 -NP Own_Lock_or_Unlock [0 ] 0 - -I Load [0 ] 0 -I Ifetch [0 ] 0 -I Store [0 ] 0 -I Atomic [0 ] 0 -I L1_Replacement [0 ] 0 -I Data_Shared [0 ] 0 -I Data_Owner [0 ] 0 -I Data_All_Tokens [0 ] 0 -I Ack [0 ] 0 -I Transient_GETX [0 ] 0 -I Transient_Local_GETX [0 ] 0 -I Transient_GETS [0 ] 0 -I Transient_Local_GETS [0 ] 0 -I Transient_GETS_Last_Token [0 ] 0 -I Transient_Local_GETS_Last_Token [0 ] 0 -I Persistent_GETX [0 ] 0 -I Persistent_GETS [0 ] 0 -I Persistent_GETS_Last_Token [0 ] 0 -I Own_Lock_or_Unlock [0 ] 0 - -S Load [29 ] 29 -S Ifetch [158 ] 158 -S Store [8 ] 8 -S Atomic [0 ] 0 -S L1_Replacement [48 ] 48 -S Data_Shared [0 ] 0 -S Data_Owner [0 ] 0 -S Data_All_Tokens [0 ] 0 -S Ack [0 ] 0 -S Transient_GETX [0 ] 0 -S Transient_Local_GETX [0 ] 0 -S Transient_GETS [0 ] 0 -S Transient_Local_GETS [0 ] 0 -S Transient_GETS_Last_Token [0 ] 0 -S Transient_Local_GETS_Last_Token [0 ] 0 -S Persistent_GETX [0 ] 0 -S Persistent_GETS [0 ] 0 -S Persistent_GETS_Last_Token [0 ] 0 -S Own_Lock_or_Unlock [0 ] 0 - -O Load [0 ] 0 -O Ifetch [0 ] 0 -O Store [0 ] 0 -O Atomic [0 ] 0 -O L1_Replacement [0 ] 0 -O Data_Shared [0 ] 0 -O Data_All_Tokens [0 ] 0 -O Ack [0 ] 0 -O Ack_All_Tokens [0 ] 0 -O Transient_GETX [0 ] 0 -O Transient_Local_GETX [0 ] 0 -O Transient_GETS [0 ] 0 -O Transient_Local_GETS [0 ] 0 -O Transient_GETS_Last_Token [0 ] 0 -O Transient_Local_GETS_Last_Token [0 ] 0 -O Persistent_GETX [0 ] 0 -O Persistent_GETS [0 ] 0 -O Persistent_GETS_Last_Token [0 ] 0 -O Own_Lock_or_Unlock [0 ] 0 - -M Load [66 ] 66 -M Ifetch [1161 ] 1161 -M Store [29 ] 29 -M Atomic [0 ] 0 -M L1_Replacement [358 ] 358 -M Transient_GETX [0 ] 0 -M Transient_Local_GETX [0 ] 0 -M Transient_GETS [0 ] 0 -M Transient_Local_GETS [0 ] 0 -M Persistent_GETX [0 ] 0 -M Persistent_GETS [0 ] 0 -M Own_Lock_or_Unlock [0 ] 0 - -MM Load [96 ] 96 -MM Ifetch [0 ] 0 -MM Store [104 ] 104 -MM Atomic [0 ] 0 -MM L1_Replacement [96 ] 96 -MM Transient_GETX [0 ] 0 -MM Transient_Local_GETX [0 ] 0 -MM Transient_GETS [0 ] 0 -MM Transient_Local_GETS [0 ] 0 -MM Persistent_GETX [0 ] 0 -MM Persistent_GETS [0 ] 0 -MM Own_Lock_or_Unlock [0 ] 0 - -M_W Load [36 ] 36 -M_W Ifetch [996 ] 996 -M_W Store [3 ] 3 -M_W Atomic [0 ] 0 -M_W L1_Replacement [1 ] 1 -M_W Transient_GETX [0 ] 0 -M_W Transient_Local_GETX [0 ] 0 -M_W Transient_GETS [0 ] 0 -M_W Transient_Local_GETS [0 ] 0 -M_W Persistent_GETX [0 ] 0 -M_W Persistent_GETS [0 ] 0 -M_W Own_Lock_or_Unlock [0 ] 0 -M_W Use_TimeoutStarverX [0 ] 0 -M_W Use_TimeoutStarverS [0 ] 0 -M_W Use_TimeoutNoStarvers [392 ] 392 -M_W Use_TimeoutNoStarvers_NoMig [0 ] 0 - -MM_W Load [6 ] 6 -MM_W Ifetch [0 ] 0 -MM_W Store [92 ] 92 -MM_W Atomic [0 ] 0 -MM_W L1_Replacement [1 ] 1 -MM_W Transient_GETX [0 ] 0 -MM_W Transient_Local_GETX [0 ] 0 -MM_W Transient_GETS [0 ] 0 -MM_W Transient_Local_GETS [0 ] 0 -MM_W Persistent_GETX [0 ] 0 -MM_W Persistent_GETS [0 ] 0 -MM_W Own_Lock_or_Unlock [0 ] 0 -MM_W Use_TimeoutStarverX [0 ] 0 -MM_W Use_TimeoutStarverS [0 ] 0 -MM_W Use_TimeoutNoStarvers [69 ] 69 -MM_W Use_TimeoutNoStarvers_NoMig [0 ] 0 - -IM Load [0 ] 0 -IM Ifetch [0 ] 0 -IM Store [0 ] 0 -IM Atomic [0 ] 0 -IM L1_Replacement [0 ] 0 -IM Data_Shared [0 ] 0 -IM Data_Owner [0 ] 0 -IM Data_All_Tokens [58 ] 58 -IM Ack [1 ] 1 -IM Transient_GETX [0 ] 0 -IM Transient_Local_GETX [0 ] 0 -IM Transient_GETS [0 ] 0 -IM Transient_Local_GETS [0 ] 0 -IM Transient_GETS_Last_Token [0 ] 0 -IM Transient_Local_GETS_Last_Token [0 ] 0 -IM Persistent_GETX [0 ] 0 -IM Persistent_GETS [0 ] 0 -IM Persistent_GETS_Last_Token [0 ] 0 -IM Own_Lock_or_Unlock [0 ] 0 -IM Request_Timeout [0 ] 0 - -SM Load [0 ] 0 -SM Ifetch [0 ] 0 -SM Store [0 ] 0 -SM Atomic [0 ] 0 -SM L1_Replacement [0 ] 0 -SM Data_Shared [0 ] 0 -SM Data_Owner [0 ] 0 -SM Data_All_Tokens [8 ] 8 -SM Ack [0 ] 0 -SM Transient_GETX [0 ] 0 -SM Transient_Local_GETX [0 ] 0 -SM Transient_GETS [0 ] 0 -SM Transient_Local_GETS [0 ] 0 -SM Transient_GETS_Last_Token [0 ] 0 -SM Transient_Local_GETS_Last_Token [0 ] 0 -SM Persistent_GETX [0 ] 0 -SM Persistent_GETS [0 ] 0 -SM Persistent_GETS_Last_Token [0 ] 0 -SM Own_Lock_or_Unlock [0 ] 0 -SM Request_Timeout [0 ] 0 - -OM Load [0 ] 0 -OM Ifetch [0 ] 0 -OM Store [0 ] 0 -OM Atomic [0 ] 0 -OM L1_Replacement [0 ] 0 -OM Data_Shared [0 ] 0 -OM Data_All_Tokens [0 ] 0 -OM Ack [0 ] 0 -OM Ack_All_Tokens [0 ] 0 -OM Transient_GETX [0 ] 0 -OM Transient_Local_GETX [0 ] 0 -OM Transient_GETS [0 ] 0 -OM Transient_Local_GETS [0 ] 0 -OM Transient_GETS_Last_Token [0 ] 0 -OM Transient_Local_GETS_Last_Token [0 ] 0 -OM Persistent_GETX [0 ] 0 -OM Persistent_GETS [0 ] 0 -OM Persistent_GETS_Last_Token [0 ] 0 -OM Own_Lock_or_Unlock [0 ] 0 -OM Request_Timeout [0 ] 0 - -IS Load [0 ] 0 -IS Ifetch [0 ] 0 -IS Store [0 ] 0 -IS Atomic [0 ] 0 -IS L1_Replacement [0 ] 0 -IS Data_Shared [56 ] 56 -IS Data_Owner [0 ] 0 -IS Data_All_Tokens [396 ] 396 -IS Ack [0 ] 0 -IS Transient_GETX [0 ] 0 -IS Transient_Local_GETX [0 ] 0 -IS Transient_GETS [0 ] 0 -IS Transient_Local_GETS [0 ] 0 -IS Transient_GETS_Last_Token [0 ] 0 -IS Transient_Local_GETS_Last_Token [0 ] 0 -IS Persistent_GETX [0 ] 0 -IS Persistent_GETS [0 ] 0 -IS Persistent_GETS_Last_Token [0 ] 0 -IS Own_Lock_or_Unlock [0 ] 0 -IS Request_Timeout [0 ] 0 - -I_L Load [0 ] 0 -I_L Ifetch [0 ] 0 -I_L Store [0 ] 0 -I_L Atomic [0 ] 0 -I_L L1_Replacement [0 ] 0 -I_L Data_Shared [0 ] 0 -I_L Data_Owner [0 ] 0 -I_L Data_All_Tokens [0 ] 0 -I_L Ack [0 ] 0 -I_L Transient_GETX [0 ] 0 -I_L Transient_Local_GETX [0 ] 0 -I_L Transient_GETS [0 ] 0 -I_L Transient_Local_GETS [0 ] 0 -I_L Transient_GETS_Last_Token [0 ] 0 -I_L Transient_Local_GETS_Last_Token [0 ] 0 -I_L Persistent_GETX [0 ] 0 -I_L Persistent_GETS [0 ] 0 -I_L Persistent_GETS_Last_Token [0 ] 0 -I_L Own_Lock_or_Unlock [0 ] 0 - -S_L Load [0 ] 0 -S_L Ifetch [0 ] 0 -S_L Store [0 ] 0 -S_L Atomic [0 ] 0 -S_L L1_Replacement [0 ] 0 -S_L Data_Shared [0 ] 0 -S_L Data_Owner [0 ] 0 -S_L Data_All_Tokens [0 ] 0 -S_L Ack [0 ] 0 -S_L Transient_GETX [0 ] 0 -S_L Transient_Local_GETX [0 ] 0 -S_L Transient_GETS [0 ] 0 -S_L Transient_Local_GETS [0 ] 0 -S_L Transient_GETS_Last_Token [0 ] 0 -S_L Transient_Local_GETS_Last_Token [0 ] 0 -S_L Persistent_GETX [0 ] 0 -S_L Persistent_GETS [0 ] 0 -S_L Persistent_GETS_Last_Token [0 ] 0 -S_L Own_Lock_or_Unlock [0 ] 0 - -IM_L Load [0 ] 0 -IM_L Ifetch [0 ] 0 -IM_L Store [0 ] 0 -IM_L Atomic [0 ] 0 -IM_L L1_Replacement [0 ] 0 -IM_L Data_Shared [0 ] 0 -IM_L Data_Owner [0 ] 0 -IM_L Data_All_Tokens [0 ] 0 -IM_L Ack [0 ] 0 -IM_L Transient_GETX [0 ] 0 -IM_L Transient_Local_GETX [0 ] 0 -IM_L Transient_GETS [0 ] 0 -IM_L Transient_Local_GETS [0 ] 0 -IM_L Transient_GETS_Last_Token [0 ] 0 -IM_L Transient_Local_GETS_Last_Token [0 ] 0 -IM_L Persistent_GETX [0 ] 0 -IM_L Persistent_GETS [0 ] 0 -IM_L Own_Lock_or_Unlock [0 ] 0 -IM_L Request_Timeout [0 ] 0 - -SM_L Load [0 ] 0 -SM_L Ifetch [0 ] 0 -SM_L Store [0 ] 0 -SM_L Atomic [0 ] 0 -SM_L L1_Replacement [0 ] 0 -SM_L Data_Shared [0 ] 0 -SM_L Data_Owner [0 ] 0 -SM_L Data_All_Tokens [0 ] 0 -SM_L Ack [0 ] 0 -SM_L Transient_GETX [0 ] 0 -SM_L Transient_Local_GETX [0 ] 0 -SM_L Transient_GETS [0 ] 0 -SM_L Transient_Local_GETS [0 ] 0 -SM_L Transient_GETS_Last_Token [0 ] 0 -SM_L Transient_Local_GETS_Last_Token [0 ] 0 -SM_L Persistent_GETX [0 ] 0 -SM_L Persistent_GETS [0 ] 0 -SM_L Persistent_GETS_Last_Token [0 ] 0 -SM_L Own_Lock_or_Unlock [0 ] 0 -SM_L Request_Timeout [0 ] 0 - -IS_L Load [0 ] 0 -IS_L Ifetch [0 ] 0 -IS_L Store [0 ] 0 -IS_L Atomic [0 ] 0 -IS_L L1_Replacement [0 ] 0 -IS_L Data_Shared [0 ] 0 -IS_L Data_Owner [0 ] 0 -IS_L Data_All_Tokens [0 ] 0 -IS_L Ack [0 ] 0 -IS_L Transient_GETX [0 ] 0 -IS_L Transient_Local_GETX [0 ] 0 -IS_L Transient_GETS [0 ] 0 -IS_L Transient_Local_GETS [0 ] 0 -IS_L Transient_GETS_Last_Token [0 ] 0 -IS_L Transient_Local_GETS_Last_Token [0 ] 0 -IS_L Persistent_GETX [0 ] 0 -IS_L Persistent_GETS [0 ] 0 -IS_L Own_Lock_or_Unlock [0 ] 0 -IS_L Request_Timeout [0 ] 0 - - --- L2Cache --- - - Event Counts - -L1_GETS [448 ] 448 -L1_GETS_Last_Token [4 ] 4 -L1_GETX [66 ] 66 -L1_INV [0 ] 0 -Transient_GETX [0 ] 0 -Transient_GETS [0 ] 0 -Transient_GETS_Last_Token [0 ] 0 -L2_Replacement [458 ] 458 -Writeback_Tokens [0 ] 0 -Writeback_Shared_Data [21 ] 21 -Writeback_All_Tokens [481 ] 481 -Writeback_Owned [0 ] 0 -Data_Shared [0 ] 0 -Data_Owner [0 ] 0 -Data_All_Tokens [0 ] 0 -Ack [0 ] 0 -Ack_All_Tokens [0 ] 0 -Persistent_GETX [0 ] 0 -Persistent_GETS [0 ] 0 -Persistent_GETS_Last_Token [0 ] 0 -Own_Lock_or_Unlock [0 ] 0 - - - Transitions - -NP L1_GETS [396 ] 396 -NP L1_GETX [50 ] 50 -NP L1_INV [0 ] 0 -NP Transient_GETX [0 ] 0 -NP Transient_GETS [0 ] 0 -NP Writeback_Tokens [0 ] 0 -NP Writeback_Shared_Data [18 ] 18 -NP Writeback_All_Tokens [448 ] 448 -NP Writeback_Owned [0 ] 0 -NP Data_Shared [0 ] 0 -NP Data_Owner [0 ] 0 -NP Data_All_Tokens [0 ] 0 -NP Ack [0 ] 0 -NP Persistent_GETX [0 ] 0 -NP Persistent_GETS [0 ] 0 -NP Persistent_GETS_Last_Token [0 ] 0 -NP Own_Lock_or_Unlock [0 ] 0 - -I L1_GETS [0 ] 0 -I L1_GETS_Last_Token [0 ] 0 -I L1_GETX [1 ] 1 -I L1_INV [0 ] 0 -I Transient_GETX [0 ] 0 -I Transient_GETS [0 ] 0 -I Transient_GETS_Last_Token [0 ] 0 -I L2_Replacement [9 ] 9 -I Writeback_Tokens [0 ] 0 -I Writeback_Shared_Data [3 ] 3 -I Writeback_All_Tokens [6 ] 6 -I Writeback_Owned [0 ] 0 -I Data_Shared [0 ] 0 -I Data_Owner [0 ] 0 -I Data_All_Tokens [0 ] 0 -I Ack [0 ] 0 -I Persistent_GETX [0 ] 0 -I Persistent_GETS [0 ] 0 -I Persistent_GETS_Last_Token [0 ] 0 -I Own_Lock_or_Unlock [0 ] 0 - -S L1_GETS [0 ] 0 -S L1_GETS_Last_Token [4 ] 4 -S L1_GETX [1 ] 1 -S L1_INV [0 ] 0 -S Transient_GETX [0 ] 0 -S Transient_GETS [0 ] 0 -S Transient_GETS_Last_Token [0 ] 0 -S L2_Replacement [15 ] 15 -S Writeback_Tokens [0 ] 0 -S Writeback_Shared_Data [0 ] 0 -S Writeback_All_Tokens [0 ] 0 -S Writeback_Owned [0 ] 0 -S Data_Shared [0 ] 0 -S Data_Owner [0 ] 0 -S Data_All_Tokens [0 ] 0 -S Ack [0 ] 0 -S Persistent_GETX [0 ] 0 -S Persistent_GETS [0 ] 0 -S Persistent_GETS_Last_Token [0 ] 0 -S Own_Lock_or_Unlock [0 ] 0 - -O L1_GETS [0 ] 0 -O L1_GETS_Last_Token [0 ] 0 -O L1_GETX [6 ] 6 -O L1_INV [0 ] 0 -O Transient_GETX [0 ] 0 -O Transient_GETS [0 ] 0 -O Transient_GETS_Last_Token [0 ] 0 -O L2_Replacement [19 ] 19 -O Writeback_Tokens [0 ] 0 -O Writeback_Shared_Data [0 ] 0 -O Writeback_All_Tokens [27 ] 27 -O Data_Shared [0 ] 0 -O Data_All_Tokens [0 ] 0 -O Ack [0 ] 0 -O Ack_All_Tokens [0 ] 0 -O Persistent_GETX [0 ] 0 -O Persistent_GETS [0 ] 0 -O Persistent_GETS_Last_Token [0 ] 0 -O Own_Lock_or_Unlock [0 ] 0 - -M L1_GETS [52 ] 52 -M L1_GETX [8 ] 8 -M L1_INV [0 ] 0 -M Transient_GETX [0 ] 0 -M Transient_GETS [0 ] 0 -M L2_Replacement [415 ] 415 -M Persistent_GETX [0 ] 0 -M Persistent_GETS [0 ] 0 -M Own_Lock_or_Unlock [0 ] 0 - -I_L L1_GETS [0 ] 0 -I_L L1_GETX [0 ] 0 -I_L L1_INV [0 ] 0 -I_L Transient_GETX [0 ] 0 -I_L Transient_GETS [0 ] 0 -I_L Transient_GETS_Last_Token [0 ] 0 -I_L L2_Replacement [0 ] 0 -I_L Writeback_Tokens [0 ] 0 -I_L Writeback_Shared_Data [0 ] 0 -I_L Writeback_All_Tokens [0 ] 0 -I_L Writeback_Owned [0 ] 0 -I_L Data_Shared [0 ] 0 -I_L Data_Owner [0 ] 0 -I_L Data_All_Tokens [0 ] 0 -I_L Ack [0 ] 0 -I_L Persistent_GETX [0 ] 0 -I_L Persistent_GETS [0 ] 0 -I_L Own_Lock_or_Unlock [0 ] 0 - -S_L L1_GETS [0 ] 0 -S_L L1_GETS_Last_Token [0 ] 0 -S_L L1_GETX [0 ] 0 -S_L L1_INV [0 ] 0 -S_L Transient_GETX [0 ] 0 -S_L Transient_GETS [0 ] 0 -S_L Transient_GETS_Last_Token [0 ] 0 -S_L L2_Replacement [0 ] 0 -S_L Writeback_Tokens [0 ] 0 -S_L Writeback_Shared_Data [0 ] 0 -S_L Writeback_All_Tokens [0 ] 0 -S_L Writeback_Owned [0 ] 0 -S_L Data_Shared [0 ] 0 -S_L Data_Owner [0 ] 0 -S_L Data_All_Tokens [0 ] 0 -S_L Ack [0 ] 0 -S_L Persistent_GETX [0 ] 0 -S_L Persistent_GETS [0 ] 0 -S_L Persistent_GETS_Last_Token [0 ] 0 -S_L Own_Lock_or_Unlock [0 ] 0 - -Memory controller: system.ruby.dir_cntrl0.memBuffer: - memory_total_requests: 532 - memory_reads: 448 - memory_writes: 84 - memory_refreshes: 299 - memory_total_request_delays: 150 - memory_delays_per_request: 0.281955 - memory_delays_in_input_queue: 0 - memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 150 - memory_stalls_for_bank_busy: 38 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 16 - memory_stalls_for_bus: 90 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 6 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 19 10 0 39 20 19 31 22 5 3 6 4 22 41 22 3 4 6 7 13 10 18 14 42 16 5 5 12 13 18 14 69 - - --- Directory --- - - Event Counts - -GETX [70 ] 70 -GETS [405 ] 405 -Lockdown [0 ] 0 -Unlockdown [0 ] 0 -Own_Lock_or_Unlock [0 ] 0 -Own_Lock_or_Unlock_Tokens [0 ] 0 -Data_Owner [3 ] 3 -Data_All_Tokens [81 ] 81 -Ack_Owner [16 ] 16 -Ack_Owner_All_Tokens [334 ] 334 -Tokens [0 ] 0 -Ack_All_Tokens [15 ] 15 -Request_Timeout [0 ] 0 -Memory_Data [448 ] 448 -Memory_Ack [84 ] 84 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -DMA_WRITE_All_Tokens [0 ] 0 - - - Transitions - -O GETX [52 ] 52 -O GETS [396 ] 396 -O Lockdown [0 ] 0 -O Unlockdown [0 ] 0 -O Own_Lock_or_Unlock [0 ] 0 -O Own_Lock_or_Unlock_Tokens [0 ] 0 -O Data_Owner [0 ] 0 -O Data_All_Tokens [0 ] 0 -O Tokens [0 ] 0 -O Ack_All_Tokens [15 ] 15 -O DMA_READ [0 ] 0 -O DMA_WRITE [0 ] 0 -O DMA_WRITE_All_Tokens [0 ] 0 - -NO GETX [6 ] 6 -NO GETS [0 ] 0 -NO Lockdown [0 ] 0 -NO Unlockdown [0 ] 0 -NO Own_Lock_or_Unlock [0 ] 0 -NO Own_Lock_or_Unlock_Tokens [0 ] 0 -NO Data_Owner [3 ] 3 -NO Data_All_Tokens [81 ] 81 -NO Ack_Owner [16 ] 16 -NO Ack_Owner_All_Tokens [334 ] 334 -NO Tokens [0 ] 0 -NO DMA_READ [0 ] 0 -NO DMA_WRITE [0 ] 0 - -L GETX [0 ] 0 -L GETS [0 ] 0 -L Lockdown [0 ] 0 -L Unlockdown [0 ] 0 -L Own_Lock_or_Unlock [0 ] 0 -L Own_Lock_or_Unlock_Tokens [0 ] 0 -L Data_Owner [0 ] 0 -L Data_All_Tokens [0 ] 0 -L Ack_Owner [0 ] 0 -L Ack_Owner_All_Tokens [0 ] 0 -L Tokens [0 ] 0 -L DMA_READ [0 ] 0 -L DMA_WRITE [0 ] 0 -L DMA_WRITE_All_Tokens [0 ] 0 - -O_W GETX [12 ] 12 -O_W GETS [9 ] 9 -O_W Lockdown [0 ] 0 -O_W Unlockdown [0 ] 0 -O_W Own_Lock_or_Unlock [0 ] 0 -O_W Own_Lock_or_Unlock_Tokens [0 ] 0 -O_W Data_Owner [0 ] 0 -O_W Data_All_Tokens [0 ] 0 -O_W Ack_Owner [0 ] 0 -O_W Tokens [0 ] 0 -O_W Ack_All_Tokens [0 ] 0 -O_W Memory_Data [0 ] 0 -O_W Memory_Ack [84 ] 84 -O_W DMA_READ [0 ] 0 -O_W DMA_WRITE [0 ] 0 -O_W DMA_WRITE_All_Tokens [0 ] 0 - -L_O_W GETX [0 ] 0 -L_O_W GETS [0 ] 0 -L_O_W Lockdown [0 ] 0 -L_O_W Unlockdown [0 ] 0 -L_O_W Own_Lock_or_Unlock [0 ] 0 -L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0 -L_O_W Data_Owner [0 ] 0 -L_O_W Data_All_Tokens [0 ] 0 -L_O_W Ack_Owner [0 ] 0 -L_O_W Tokens [0 ] 0 -L_O_W Ack_All_Tokens [0 ] 0 -L_O_W Memory_Data [0 ] 0 -L_O_W Memory_Ack [0 ] 0 -L_O_W DMA_READ [0 ] 0 -L_O_W DMA_WRITE [0 ] 0 -L_O_W DMA_WRITE_All_Tokens [0 ] 0 - -L_NO_W GETX [0 ] 0 -L_NO_W GETS [0 ] 0 -L_NO_W Lockdown [0 ] 0 -L_NO_W Unlockdown [0 ] 0 -L_NO_W Own_Lock_or_Unlock [0 ] 0 -L_NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 -L_NO_W Data_Owner [0 ] 0 -L_NO_W Data_All_Tokens [0 ] 0 -L_NO_W Ack_Owner [0 ] 0 -L_NO_W Tokens [0 ] 0 -L_NO_W Ack_All_Tokens [0 ] 0 -L_NO_W Memory_Data [0 ] 0 -L_NO_W DMA_READ [0 ] 0 -L_NO_W DMA_WRITE [0 ] 0 -L_NO_W DMA_WRITE_All_Tokens [0 ] 0 - -DR_L_W GETX [0 ] 0 -DR_L_W GETS [0 ] 0 -DR_L_W Lockdown [0 ] 0 -DR_L_W Unlockdown [0 ] 0 -DR_L_W Own_Lock_or_Unlock [0 ] 0 -DR_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 -DR_L_W Data_Owner [0 ] 0 -DR_L_W Data_All_Tokens [0 ] 0 -DR_L_W Ack_Owner [0 ] 0 -DR_L_W Tokens [0 ] 0 -DR_L_W Ack_All_Tokens [0 ] 0 -DR_L_W Request_Timeout [0 ] 0 -DR_L_W Memory_Data [0 ] 0 -DR_L_W DMA_READ [0 ] 0 -DR_L_W DMA_WRITE [0 ] 0 -DR_L_W DMA_WRITE_All_Tokens [0 ] 0 - -DW_L_W GETX [0 ] 0 -DW_L_W GETS [0 ] 0 -DW_L_W Lockdown [0 ] 0 -DW_L_W Unlockdown [0 ] 0 -DW_L_W Own_Lock_or_Unlock [0 ] 0 -DW_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 -DW_L_W Data_Owner [0 ] 0 -DW_L_W Data_All_Tokens [0 ] 0 -DW_L_W Ack_Owner [0 ] 0 -DW_L_W Tokens [0 ] 0 -DW_L_W Ack_All_Tokens [0 ] 0 -DW_L_W Request_Timeout [0 ] 0 -DW_L_W Memory_Ack [0 ] 0 -DW_L_W DMA_READ [0 ] 0 -DW_L_W DMA_WRITE [0 ] 0 -DW_L_W DMA_WRITE_All_Tokens [0 ] 0 - -NO_W GETX [0 ] 0 -NO_W GETS [0 ] 0 -NO_W Lockdown [0 ] 0 -NO_W Unlockdown [0 ] 0 -NO_W Own_Lock_or_Unlock [0 ] 0 -NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 -NO_W Data_Owner [0 ] 0 -NO_W Data_All_Tokens [0 ] 0 -NO_W Ack_Owner [0 ] 0 -NO_W Tokens [0 ] 0 -NO_W Ack_All_Tokens [0 ] 0 -NO_W Memory_Data [448 ] 448 -NO_W DMA_READ [0 ] 0 -NO_W DMA_WRITE [0 ] 0 -NO_W DMA_WRITE_All_Tokens [0 ] 0 - -O_DW_W GETX [0 ] 0 -O_DW_W GETS [0 ] 0 -O_DW_W Lockdown [0 ] 0 -O_DW_W Unlockdown [0 ] 0 -O_DW_W Own_Lock_or_Unlock [0 ] 0 -O_DW_W Own_Lock_or_Unlock_Tokens [0 ] 0 -O_DW_W Data_Owner [0 ] 0 -O_DW_W Data_All_Tokens [0 ] 0 -O_DW_W Ack_Owner [0 ] 0 -O_DW_W Tokens [0 ] 0 -O_DW_W Ack_All_Tokens [0 ] 0 -O_DW_W Request_Timeout [0 ] 0 -O_DW_W Memory_Ack [0 ] 0 -O_DW_W DMA_READ [0 ] 0 -O_DW_W DMA_WRITE [0 ] 0 -O_DW_W DMA_WRITE_All_Tokens [0 ] 0 - -O_DR_W GETX [0 ] 0 -O_DR_W GETS [0 ] 0 -O_DR_W Lockdown [0 ] 0 -O_DR_W Unlockdown [0 ] 0 -O_DR_W Own_Lock_or_Unlock [0 ] 0 -O_DR_W Own_Lock_or_Unlock_Tokens [0 ] 0 -O_DR_W Data_Owner [0 ] 0 -O_DR_W Data_All_Tokens [0 ] 0 -O_DR_W Ack_Owner [0 ] 0 -O_DR_W Tokens [0 ] 0 -O_DR_W Ack_All_Tokens [0 ] 0 -O_DR_W Request_Timeout [0 ] 0 -O_DR_W Memory_Data [0 ] 0 -O_DR_W DMA_READ [0 ] 0 -O_DR_W DMA_WRITE [0 ] 0 -O_DR_W DMA_WRITE_All_Tokens [0 ] 0 - -O_DW GETX [0 ] 0 -O_DW GETS [0 ] 0 -O_DW Lockdown [0 ] 0 -O_DW Unlockdown [0 ] 0 -O_DW Own_Lock_or_Unlock [0 ] 0 -O_DW Own_Lock_or_Unlock_Tokens [0 ] 0 -O_DW Data_Owner [0 ] 0 -O_DW Data_All_Tokens [0 ] 0 -O_DW Ack_Owner [0 ] 0 -O_DW Ack_Owner_All_Tokens [0 ] 0 -O_DW Tokens [0 ] 0 -O_DW Ack_All_Tokens [0 ] 0 -O_DW Request_Timeout [0 ] 0 -O_DW DMA_READ [0 ] 0 -O_DW DMA_WRITE [0 ] 0 -O_DW DMA_WRITE_All_Tokens [0 ] 0 - -NO_DW GETX [0 ] 0 -NO_DW GETS [0 ] 0 -NO_DW Lockdown [0 ] 0 -NO_DW Unlockdown [0 ] 0 -NO_DW Own_Lock_or_Unlock [0 ] 0 -NO_DW Own_Lock_or_Unlock_Tokens [0 ] 0 -NO_DW Data_Owner [0 ] 0 -NO_DW Data_All_Tokens [0 ] 0 -NO_DW Tokens [0 ] 0 -NO_DW Request_Timeout [0 ] 0 -NO_DW DMA_READ [0 ] 0 -NO_DW DMA_WRITE [0 ] 0 -NO_DW DMA_WRITE_All_Tokens [0 ] 0 - -NO_DR GETX [0 ] 0 -NO_DR GETS [0 ] 0 -NO_DR Lockdown [0 ] 0 -NO_DR Unlockdown [0 ] 0 -NO_DR Own_Lock_or_Unlock [0 ] 0 -NO_DR Own_Lock_or_Unlock_Tokens [0 ] 0 -NO_DR Data_Owner [0 ] 0 -NO_DR Data_All_Tokens [0 ] 0 -NO_DR Tokens [0 ] 0 -NO_DR Request_Timeout [0 ] 0 -NO_DR DMA_READ [0 ] 0 -NO_DR DMA_WRITE [0 ] 0 -NO_DR DMA_WRITE_All_Tokens [0 ] 0 - -DW_L GETX [0 ] 0 -DW_L GETS [0 ] 0 -DW_L Lockdown [0 ] 0 -DW_L Unlockdown [0 ] 0 -DW_L Own_Lock_or_Unlock [0 ] 0 -DW_L Own_Lock_or_Unlock_Tokens [0 ] 0 -DW_L Data_Owner [0 ] 0 -DW_L Data_All_Tokens [0 ] 0 -DW_L Ack_Owner [0 ] 0 -DW_L Ack_Owner_All_Tokens [0 ] 0 -DW_L Tokens [0 ] 0 -DW_L Request_Timeout [0 ] 0 -DW_L DMA_READ [0 ] 0 -DW_L DMA_WRITE [0 ] 0 -DW_L DMA_WRITE_All_Tokens [0 ] 0 - -DR_L GETX [0 ] 0 -DR_L GETS [0 ] 0 -DR_L Lockdown [0 ] 0 -DR_L Unlockdown [0 ] 0 -DR_L Own_Lock_or_Unlock [0 ] 0 -DR_L Own_Lock_or_Unlock_Tokens [0 ] 0 -DR_L Data_Owner [0 ] 0 -DR_L Data_All_Tokens [0 ] 0 -DR_L Ack_Owner [0 ] 0 -DR_L Ack_Owner_All_Tokens [0 ] 0 -DR_L Tokens [0 ] 0 -DR_L Request_Timeout [0 ] 0 -DR_L DMA_READ [0 ] 0 -DR_L DMA_WRITE [0 ] 0 -DR_L DMA_WRITE_All_Tokens [0 ] 0 - diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index 2b0dd9ad2..48058efde 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000043 # Nu sim_ticks 43073 # Number of ticks simulated final_tick 43073 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 14561 # Simulator instruction rate (inst/s) -host_op_rate 14560 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 243330 # Simulator tick rate (ticks/s) -host_mem_usage 151252 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 29444 # Simulator instruction rate (inst/s) +host_op_rate 29437 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 491916 # Simulator tick rate (ticks/s) +host_mem_usage 144372 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.ruby.l2_cntrl0.L2cache.demand_hits 64 # Number of cache demand hits @@ -20,6 +20,20 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses +system.ruby.dir_cntrl0.memBuffer.memReq 532 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 448 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 84 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 299 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 150 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 150 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.281955 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 38 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 90 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 6 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 16 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 19 3.57% 3.57% | 10 1.88% 5.45% | 0 0.00% 5.45% | 39 7.33% 12.78% | 20 3.76% 16.54% | 19 3.57% 20.11% | 31 5.83% 25.94% | 22 4.14% 30.08% | 5 0.94% 31.02% | 3 0.56% 31.58% | 6 1.13% 32.71% | 4 0.75% 33.46% | 22 4.14% 37.59% | 41 7.71% 45.30% | 22 4.14% 49.44% | 3 0.56% 50.00% | 4 0.75% 50.75% | 6 1.13% 51.88% | 7 1.32% 53.20% | 13 2.44% 55.64% | 10 1.88% 57.52% | 18 3.38% 60.90% | 14 2.63% 63.53% | 42 7.89% 71.43% | 16 3.01% 74.44% | 5 0.94% 75.38% | 5 0.94% 76.32% | 12 2.26% 78.57% | 13 2.44% 81.02% | 18 3.38% 84.40% | 14 2.63% 87.03% | 69 12.97% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 532 # Number of accesses per bank + system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -75,5 +89,85 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 43073 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles +system.ruby.l2_cntrl0.L1_GETS 448 0.00% 0.00% +system.ruby.l2_cntrl0.L1_GETS_Last_Token 4 0.00% 0.00% +system.ruby.l2_cntrl0.L1_GETX 66 0.00% 0.00% +system.ruby.l2_cntrl0.L2_Replacement 458 0.00% 0.00% +system.ruby.l2_cntrl0.Writeback_Shared_Data 21 0.00% 0.00% +system.ruby.l2_cntrl0.Writeback_All_Tokens 481 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETS 396 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETX 50 0.00% 0.00% +system.ruby.l2_cntrl0.NP.Writeback_Shared_Data 18 0.00% 0.00% +system.ruby.l2_cntrl0.NP.Writeback_All_Tokens 448 0.00% 0.00% +system.ruby.l2_cntrl0.I.L1_GETX 1 0.00% 0.00% +system.ruby.l2_cntrl0.I.L2_Replacement 9 0.00% 0.00% +system.ruby.l2_cntrl0.I.Writeback_Shared_Data 3 0.00% 0.00% +system.ruby.l2_cntrl0.I.Writeback_All_Tokens 6 0.00% 0.00% +system.ruby.l2_cntrl0.S.L1_GETS_Last_Token 4 0.00% 0.00% +system.ruby.l2_cntrl0.S.L1_GETX 1 0.00% 0.00% +system.ruby.l2_cntrl0.S.L2_Replacement 15 0.00% 0.00% +system.ruby.l2_cntrl0.O.L1_GETX 6 0.00% 0.00% +system.ruby.l2_cntrl0.O.L2_Replacement 19 0.00% 0.00% +system.ruby.l2_cntrl0.O.Writeback_All_Tokens 27 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETS 52 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETX 8 0.00% 0.00% +system.ruby.l2_cntrl0.M.L2_Replacement 415 0.00% 0.00% +system.ruby.l1_cntrl0.Load 415 0.00% 0.00% +system.ruby.l1_cntrl0.Ifetch 2585 0.00% 0.00% +system.ruby.l1_cntrl0.Store 294 0.00% 0.00% +system.ruby.l1_cntrl0.L1_Replacement 504 0.00% 0.00% +system.ruby.l1_cntrl0.Data_Shared 56 0.00% 0.00% +system.ruby.l1_cntrl0.Data_All_Tokens 462 0.00% 0.00% +system.ruby.l1_cntrl0.Ack 1 0.00% 0.00% +system.ruby.l1_cntrl0.Use_TimeoutNoStarvers 461 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Load 182 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Ifetch 270 0.00% 0.00% +system.ruby.l1_cntrl0.NP.Store 58 0.00% 0.00% +system.ruby.l1_cntrl0.S.Load 29 0.00% 0.00% +system.ruby.l1_cntrl0.S.Ifetch 158 0.00% 0.00% +system.ruby.l1_cntrl0.S.Store 8 0.00% 0.00% +system.ruby.l1_cntrl0.S.L1_Replacement 48 0.00% 0.00% +system.ruby.l1_cntrl0.M.Load 66 0.00% 0.00% +system.ruby.l1_cntrl0.M.Ifetch 1161 0.00% 0.00% +system.ruby.l1_cntrl0.M.Store 29 0.00% 0.00% +system.ruby.l1_cntrl0.M.L1_Replacement 358 0.00% 0.00% +system.ruby.l1_cntrl0.MM.Load 96 0.00% 0.00% +system.ruby.l1_cntrl0.MM.Store 104 0.00% 0.00% +system.ruby.l1_cntrl0.MM.L1_Replacement 96 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.Load 36 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.Ifetch 996 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.Store 3 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.L1_Replacement 1 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.Use_TimeoutNoStarvers 392 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.Load 6 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.Store 92 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.L1_Replacement 1 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.Use_TimeoutNoStarvers 69 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Data_All_Tokens 58 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Ack 1 0.00% 0.00% +system.ruby.l1_cntrl0.SM.Data_All_Tokens 8 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data_Shared 56 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data_All_Tokens 396 0.00% 0.00% +system.ruby.dir_cntrl0.GETX 70 0.00% 0.00% +system.ruby.dir_cntrl0.GETS 405 0.00% 0.00% +system.ruby.dir_cntrl0.Data_Owner 3 0.00% 0.00% +system.ruby.dir_cntrl0.Data_All_Tokens 81 0.00% 0.00% +system.ruby.dir_cntrl0.Ack_Owner 16 0.00% 0.00% +system.ruby.dir_cntrl0.Ack_Owner_All_Tokens 334 0.00% 0.00% +system.ruby.dir_cntrl0.Ack_All_Tokens 15 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 448 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 84 0.00% 0.00% +system.ruby.dir_cntrl0.O.GETX 52 0.00% 0.00% +system.ruby.dir_cntrl0.O.GETS 396 0.00% 0.00% +system.ruby.dir_cntrl0.O.Ack_All_Tokens 15 0.00% 0.00% +system.ruby.dir_cntrl0.NO.GETX 6 0.00% 0.00% +system.ruby.dir_cntrl0.NO.Data_Owner 3 0.00% 0.00% +system.ruby.dir_cntrl0.NO.Data_All_Tokens 81 0.00% 0.00% +system.ruby.dir_cntrl0.NO.Ack_Owner 16 0.00% 0.00% +system.ruby.dir_cntrl0.NO.Ack_Owner_All_Tokens 334 0.00% 0.00% +system.ruby.dir_cntrl0.O_W.GETX 12 0.00% 0.00% +system.ruby.dir_cntrl0.O_W.GETS 9 0.00% 0.00% +system.ruby.dir_cntrl0.O_W.Memory_Ack 84 0.00% 0.00% +system.ruby.dir_cntrl0.NO_W.Memory_Data 448 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats index 665871e67..38023d4ac 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats @@ -1,26 +1,24 @@ -Real time: Mar/06/2013 20:34:50 +Real time: Jun/08/2013 13:28:07 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.51 -Virtual_time_in_minutes: 0.0085 -Virtual_time_in_hours: 0.000141667 -Virtual_time_in_days: 5.90278e-06 +Virtual_time_in_seconds: 0.5 +Virtual_time_in_minutes: 0.00833333 +Virtual_time_in_hours: 0.000138889 +Virtual_time_in_days: 5.78704e-06 Ruby_current_time: 35432 Ruby_start_time: 0 Ruby_cycles: 35432 -mbytes_resident: 52.5391 -mbytes_total: 144.84 -resident_ratio: 0.362793 - -ruby_cycles_executed: [ 35433 ] +mbytes_resident: 53.8984 +mbytes_total: 141.902 +resident_ratio: 0.379883 Busy Controller Counts: L1Cache-0:0 @@ -68,7 +66,6 @@ Request vs. RubySystem State Profile -------------------------------- -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- @@ -89,11 +86,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10230 -page_faults: 0 +page_reclaims: 15042 +page_faults: 6 swaps: 0 -block_inputs: 8 -block_outputs: 88 +block_inputs: 936 +block_outputs: 16712 Network Stats ------------- @@ -144,749 +141,3 @@ links_utilized_percent_switch_2: 4.77887 outgoing_messages_switch_2_link_1_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1 - --- L1Cache --- - - Event Counts - -Load [422 ] 422 -Ifetch [2591 ] 2591 -Store [298 ] 298 -L2_Replacement [425 ] 425 -L1_to_L2 [502 ] 502 -Trigger_L2_to_L1D [47 ] 47 -Trigger_L2_to_L1I [22 ] 22 -Complete_L2_to_L1 [69 ] 69 -Other_GETX [0 ] 0 -Other_GETS [0 ] 0 -Merged_GETS [0 ] 0 -Other_GETS_No_Mig [0 ] 0 -NC_DMA_GETS [0 ] 0 -Invalidate [0 ] 0 -Ack [0 ] 0 -Shared_Ack [0 ] 0 -Data [0 ] 0 -Shared_Data [0 ] 0 -Exclusive_Data [441 ] 441 -Writeback_Ack [425 ] 425 -Writeback_Nack [0 ] 0 -All_acks [0 ] 0 -All_acks_no_sharers [441 ] 441 -Flush_line [0 ] 0 -Block_Ack [0 ] 0 - - - Transitions - -I Load [146 ] 146 -I Ifetch [248 ] 248 -I Store [47 ] 47 -I L2_Replacement [0 ] 0 -I L1_to_L2 [0 ] 0 -I Trigger_L2_to_L1D [0 ] 0 -I Trigger_L2_to_L1I [0 ] 0 -I Other_GETX [0 ] 0 -I Other_GETS [0 ] 0 -I Other_GETS_No_Mig [0 ] 0 -I NC_DMA_GETS [0 ] 0 -I Invalidate [0 ] 0 -I Flush_line [0 ] 0 - -S Load [0 ] 0 -S Ifetch [0 ] 0 -S Store [0 ] 0 -S L2_Replacement [0 ] 0 -S L1_to_L2 [0 ] 0 -S Trigger_L2_to_L1D [0 ] 0 -S Trigger_L2_to_L1I [0 ] 0 -S Other_GETX [0 ] 0 -S Other_GETS [0 ] 0 -S Other_GETS_No_Mig [0 ] 0 -S NC_DMA_GETS [0 ] 0 -S Invalidate [0 ] 0 -S Flush_line [0 ] 0 - -O Load [0 ] 0 -O Ifetch [0 ] 0 -O Store [0 ] 0 -O L2_Replacement [0 ] 0 -O L1_to_L2 [0 ] 0 -O Trigger_L2_to_L1D [0 ] 0 -O Trigger_L2_to_L1I [0 ] 0 -O Other_GETX [0 ] 0 -O Other_GETS [0 ] 0 -O Merged_GETS [0 ] 0 -O Other_GETS_No_Mig [0 ] 0 -O NC_DMA_GETS [0 ] 0 -O Invalidate [0 ] 0 -O Flush_line [0 ] 0 - -M Load [109 ] 109 -M Ifetch [2315 ] 2315 -M Store [35 ] 35 -M L2_Replacement [344 ] 344 -M L1_to_L2 [397 ] 397 -M Trigger_L2_to_L1D [23 ] 23 -M Trigger_L2_to_L1I [22 ] 22 -M Other_GETX [0 ] 0 -M Other_GETS [0 ] 0 -M Merged_GETS [0 ] 0 -M Other_GETS_No_Mig [0 ] 0 -M NC_DMA_GETS [0 ] 0 -M Invalidate [0 ] 0 -M Flush_line [0 ] 0 - -MM Load [124 ] 124 -MM Ifetch [0 ] 0 -MM Store [201 ] 201 -MM L2_Replacement [81 ] 81 -MM L1_to_L2 [105 ] 105 -MM Trigger_L2_to_L1D [24 ] 24 -MM Trigger_L2_to_L1I [0 ] 0 -MM Other_GETX [0 ] 0 -MM Other_GETS [0 ] 0 -MM Merged_GETS [0 ] 0 -MM Other_GETS_No_Mig [0 ] 0 -MM NC_DMA_GETS [0 ] 0 -MM Invalidate [0 ] 0 -MM Flush_line [0 ] 0 - -IR Load [0 ] 0 -IR Ifetch [0 ] 0 -IR Store [0 ] 0 -IR L1_to_L2 [0 ] 0 -IR Flush_line [0 ] 0 - -SR Load [0 ] 0 -SR Ifetch [0 ] 0 -SR Store [0 ] 0 -SR L1_to_L2 [0 ] 0 -SR Flush_line [0 ] 0 - -OR Load [0 ] 0 -OR Ifetch [0 ] 0 -OR Store [0 ] 0 -OR L1_to_L2 [0 ] 0 -OR Flush_line [0 ] 0 - -MR Load [22 ] 22 -MR Ifetch [22 ] 22 -MR Store [1 ] 1 -MR L1_to_L2 [0 ] 0 -MR Flush_line [0 ] 0 - -MMR Load [14 ] 14 -MMR Ifetch [0 ] 0 -MMR Store [10 ] 10 -MMR L1_to_L2 [0 ] 0 -MMR Flush_line [0 ] 0 - -IM Load [0 ] 0 -IM Ifetch [0 ] 0 -IM Store [0 ] 0 -IM L2_Replacement [0 ] 0 -IM L1_to_L2 [0 ] 0 -IM Other_GETX [0 ] 0 -IM Other_GETS [0 ] 0 -IM Other_GETS_No_Mig [0 ] 0 -IM NC_DMA_GETS [0 ] 0 -IM Invalidate [0 ] 0 -IM Ack [0 ] 0 -IM Data [0 ] 0 -IM Exclusive_Data [47 ] 47 -IM Flush_line [0 ] 0 - -SM Load [0 ] 0 -SM Ifetch [0 ] 0 -SM Store [0 ] 0 -SM L2_Replacement [0 ] 0 -SM L1_to_L2 [0 ] 0 -SM Other_GETX [0 ] 0 -SM Other_GETS [0 ] 0 -SM Other_GETS_No_Mig [0 ] 0 -SM NC_DMA_GETS [0 ] 0 -SM Invalidate [0 ] 0 -SM Ack [0 ] 0 -SM Data [0 ] 0 -SM Exclusive_Data [0 ] 0 -SM Flush_line [0 ] 0 - -OM Load [0 ] 0 -OM Ifetch [0 ] 0 -OM Store [0 ] 0 -OM L2_Replacement [0 ] 0 -OM L1_to_L2 [0 ] 0 -OM Other_GETX [0 ] 0 -OM Other_GETS [0 ] 0 -OM Merged_GETS [0 ] 0 -OM Other_GETS_No_Mig [0 ] 0 -OM NC_DMA_GETS [0 ] 0 -OM Invalidate [0 ] 0 -OM Ack [0 ] 0 -OM All_acks [0 ] 0 -OM All_acks_no_sharers [0 ] 0 -OM Flush_line [0 ] 0 - -ISM Load [0 ] 0 -ISM Ifetch [0 ] 0 -ISM Store [0 ] 0 -ISM L2_Replacement [0 ] 0 -ISM L1_to_L2 [0 ] 0 -ISM Ack [0 ] 0 -ISM All_acks_no_sharers [0 ] 0 -ISM Flush_line [0 ] 0 - -M_W Load [0 ] 0 -M_W Ifetch [0 ] 0 -M_W Store [0 ] 0 -M_W L2_Replacement [0 ] 0 -M_W L1_to_L2 [0 ] 0 -M_W Ack [0 ] 0 -M_W All_acks_no_sharers [394 ] 394 -M_W Flush_line [0 ] 0 - -MM_W Load [0 ] 0 -MM_W Ifetch [0 ] 0 -MM_W Store [0 ] 0 -MM_W L2_Replacement [0 ] 0 -MM_W L1_to_L2 [0 ] 0 -MM_W Ack [0 ] 0 -MM_W All_acks_no_sharers [47 ] 47 -MM_W Flush_line [0 ] 0 - -IS Load [0 ] 0 -IS Ifetch [0 ] 0 -IS Store [0 ] 0 -IS L2_Replacement [0 ] 0 -IS L1_to_L2 [0 ] 0 -IS Other_GETX [0 ] 0 -IS Other_GETS [0 ] 0 -IS Other_GETS_No_Mig [0 ] 0 -IS NC_DMA_GETS [0 ] 0 -IS Invalidate [0 ] 0 -IS Ack [0 ] 0 -IS Shared_Ack [0 ] 0 -IS Data [0 ] 0 -IS Shared_Data [0 ] 0 -IS Exclusive_Data [394 ] 394 -IS Flush_line [0 ] 0 - -SS Load [0 ] 0 -SS Ifetch [0 ] 0 -SS Store [0 ] 0 -SS L2_Replacement [0 ] 0 -SS L1_to_L2 [0 ] 0 -SS Ack [0 ] 0 -SS Shared_Ack [0 ] 0 -SS All_acks [0 ] 0 -SS All_acks_no_sharers [0 ] 0 -SS Flush_line [0 ] 0 - -OI Load [0 ] 0 -OI Ifetch [0 ] 0 -OI Store [0 ] 0 -OI L2_Replacement [0 ] 0 -OI L1_to_L2 [0 ] 0 -OI Other_GETX [0 ] 0 -OI Other_GETS [0 ] 0 -OI Merged_GETS [0 ] 0 -OI Other_GETS_No_Mig [0 ] 0 -OI NC_DMA_GETS [0 ] 0 -OI Invalidate [0 ] 0 -OI Writeback_Ack [0 ] 0 -OI Flush_line [0 ] 0 - -MI Load [7 ] 7 -MI Ifetch [6 ] 6 -MI Store [4 ] 4 -MI L2_Replacement [0 ] 0 -MI L1_to_L2 [0 ] 0 -MI Other_GETX [0 ] 0 -MI Other_GETS [0 ] 0 -MI Merged_GETS [0 ] 0 -MI Other_GETS_No_Mig [0 ] 0 -MI NC_DMA_GETS [0 ] 0 -MI Invalidate [0 ] 0 -MI Writeback_Ack [425 ] 425 -MI Flush_line [0 ] 0 - -II Load [0 ] 0 -II Ifetch [0 ] 0 -II Store [0 ] 0 -II L2_Replacement [0 ] 0 -II L1_to_L2 [0 ] 0 -II Other_GETX [0 ] 0 -II Other_GETS [0 ] 0 -II Other_GETS_No_Mig [0 ] 0 -II NC_DMA_GETS [0 ] 0 -II Invalidate [0 ] 0 -II Writeback_Ack [0 ] 0 -II Writeback_Nack [0 ] 0 -II Flush_line [0 ] 0 - -IT Load [0 ] 0 -IT Ifetch [0 ] 0 -IT Store [0 ] 0 -IT L2_Replacement [0 ] 0 -IT L1_to_L2 [0 ] 0 -IT Complete_L2_to_L1 [0 ] 0 - -ST Load [0 ] 0 -ST Ifetch [0 ] 0 -ST Store [0 ] 0 -ST L2_Replacement [0 ] 0 -ST L1_to_L2 [0 ] 0 -ST Complete_L2_to_L1 [0 ] 0 - -OT Load [0 ] 0 -OT Ifetch [0 ] 0 -OT Store [0 ] 0 -OT L2_Replacement [0 ] 0 -OT L1_to_L2 [0 ] 0 -OT Complete_L2_to_L1 [0 ] 0 - -MT Load [0 ] 0 -MT Ifetch [0 ] 0 -MT Store [0 ] 0 -MT L2_Replacement [0 ] 0 -MT L1_to_L2 [0 ] 0 -MT Complete_L2_to_L1 [45 ] 45 - -MMT Load [0 ] 0 -MMT Ifetch [0 ] 0 -MMT Store [0 ] 0 -MMT L2_Replacement [0 ] 0 -MMT L1_to_L2 [0 ] 0 -MMT Complete_L2_to_L1 [24 ] 24 - -MI_F Load [0 ] 0 -MI_F Ifetch [0 ] 0 -MI_F Store [0 ] 0 -MI_F L1_to_L2 [0 ] 0 -MI_F Writeback_Ack [0 ] 0 -MI_F Flush_line [0 ] 0 - -MM_F Load [0 ] 0 -MM_F Ifetch [0 ] 0 -MM_F Store [0 ] 0 -MM_F L1_to_L2 [0 ] 0 -MM_F Other_GETX [0 ] 0 -MM_F Other_GETS [0 ] 0 -MM_F Merged_GETS [0 ] 0 -MM_F Other_GETS_No_Mig [0 ] 0 -MM_F NC_DMA_GETS [0 ] 0 -MM_F Invalidate [0 ] 0 -MM_F Ack [0 ] 0 -MM_F All_acks [0 ] 0 -MM_F All_acks_no_sharers [0 ] 0 -MM_F Flush_line [0 ] 0 -MM_F Block_Ack [0 ] 0 - -IM_F Load [0 ] 0 -IM_F Ifetch [0 ] 0 -IM_F Store [0 ] 0 -IM_F L2_Replacement [0 ] 0 -IM_F L1_to_L2 [0 ] 0 -IM_F Other_GETX [0 ] 0 -IM_F Other_GETS [0 ] 0 -IM_F Other_GETS_No_Mig [0 ] 0 -IM_F NC_DMA_GETS [0 ] 0 -IM_F Invalidate [0 ] 0 -IM_F Ack [0 ] 0 -IM_F Data [0 ] 0 -IM_F Exclusive_Data [0 ] 0 -IM_F Flush_line [0 ] 0 - -ISM_F Load [0 ] 0 -ISM_F Ifetch [0 ] 0 -ISM_F Store [0 ] 0 -ISM_F L2_Replacement [0 ] 0 -ISM_F L1_to_L2 [0 ] 0 -ISM_F Ack [0 ] 0 -ISM_F All_acks_no_sharers [0 ] 0 -ISM_F Flush_line [0 ] 0 - -SM_F Load [0 ] 0 -SM_F Ifetch [0 ] 0 -SM_F Store [0 ] 0 -SM_F L2_Replacement [0 ] 0 -SM_F L1_to_L2 [0 ] 0 -SM_F Other_GETX [0 ] 0 -SM_F Other_GETS [0 ] 0 -SM_F Other_GETS_No_Mig [0 ] 0 -SM_F NC_DMA_GETS [0 ] 0 -SM_F Invalidate [0 ] 0 -SM_F Ack [0 ] 0 -SM_F Data [0 ] 0 -SM_F Exclusive_Data [0 ] 0 -SM_F Flush_line [0 ] 0 - -OM_F Load [0 ] 0 -OM_F Ifetch [0 ] 0 -OM_F Store [0 ] 0 -OM_F L2_Replacement [0 ] 0 -OM_F L1_to_L2 [0 ] 0 -OM_F Other_GETX [0 ] 0 -OM_F Other_GETS [0 ] 0 -OM_F Merged_GETS [0 ] 0 -OM_F Other_GETS_No_Mig [0 ] 0 -OM_F NC_DMA_GETS [0 ] 0 -OM_F Invalidate [0 ] 0 -OM_F Ack [0 ] 0 -OM_F All_acks [0 ] 0 -OM_F All_acks_no_sharers [0 ] 0 -OM_F Flush_line [0 ] 0 - -MM_WF Load [0 ] 0 -MM_WF Ifetch [0 ] 0 -MM_WF Store [0 ] 0 -MM_WF L2_Replacement [0 ] 0 -MM_WF L1_to_L2 [0 ] 0 -MM_WF Ack [0 ] 0 -MM_WF All_acks_no_sharers [0 ] 0 -MM_WF Flush_line [0 ] 0 - -Memory controller: system.ruby.dir_cntrl0.memBuffer: - memory_total_requests: 522 - memory_reads: 441 - memory_writes: 81 - memory_refreshes: 246 - memory_total_request_delays: 39 - memory_delays_per_request: 0.0747126 - memory_delays_in_input_queue: 0 - memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 39 - memory_stalls_for_bank_busy: 15 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 5 - memory_stalls_for_bus: 15 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 4 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 18 10 0 36 20 19 31 22 5 4 7 4 22 41 22 3 4 6 7 13 10 18 14 41 16 5 5 12 13 18 14 62 - - --- Directory --- - - Event Counts - -GETX [51 ] 51 -GETS [410 ] 410 -PUT [425 ] 425 -Unblock [0 ] 0 -UnblockS [0 ] 0 -UnblockM [440 ] 440 -Writeback_Clean [0 ] 0 -Writeback_Dirty [0 ] 0 -Writeback_Exclusive_Clean [344 ] 344 -Writeback_Exclusive_Dirty [81 ] 81 -Pf_Replacement [0 ] 0 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -Memory_Data [441 ] 441 -Memory_Ack [81 ] 81 -Ack [0 ] 0 -Shared_Ack [0 ] 0 -Shared_Data [0 ] 0 -Data [0 ] 0 -Exclusive_Data [0 ] 0 -All_acks_and_shared_data [0 ] 0 -All_acks_and_owner_data [0 ] 0 -All_acks_and_data_no_sharers [0 ] 0 -All_Unblocks [0 ] 0 -GETF [0 ] 0 -PUTF [0 ] 0 - - - Transitions - -NX GETX [0 ] 0 -NX GETS [0 ] 0 -NX PUT [0 ] 0 -NX Pf_Replacement [0 ] 0 -NX DMA_READ [0 ] 0 -NX DMA_WRITE [0 ] 0 -NX GETF [0 ] 0 - -NO GETX [0 ] 0 -NO GETS [0 ] 0 -NO PUT [425 ] 425 -NO Pf_Replacement [0 ] 0 -NO DMA_READ [0 ] 0 -NO DMA_WRITE [0 ] 0 -NO GETF [0 ] 0 - -S GETX [0 ] 0 -S GETS [0 ] 0 -S PUT [0 ] 0 -S Pf_Replacement [0 ] 0 -S DMA_READ [0 ] 0 -S DMA_WRITE [0 ] 0 -S GETF [0 ] 0 - -O GETX [0 ] 0 -O GETS [0 ] 0 -O PUT [0 ] 0 -O Pf_Replacement [0 ] 0 -O DMA_READ [0 ] 0 -O DMA_WRITE [0 ] 0 -O GETF [0 ] 0 - -E GETX [47 ] 47 -E GETS [394 ] 394 -E PUT [0 ] 0 -E DMA_READ [0 ] 0 -E DMA_WRITE [0 ] 0 -E GETF [0 ] 0 - -O_R GETX [0 ] 0 -O_R GETS [0 ] 0 -O_R PUT [0 ] 0 -O_R Pf_Replacement [0 ] 0 -O_R DMA_READ [0 ] 0 -O_R DMA_WRITE [0 ] 0 -O_R Ack [0 ] 0 -O_R All_acks_and_data_no_sharers [0 ] 0 -O_R GETF [0 ] 0 - -S_R GETX [0 ] 0 -S_R GETS [0 ] 0 -S_R PUT [0 ] 0 -S_R Pf_Replacement [0 ] 0 -S_R DMA_READ [0 ] 0 -S_R DMA_WRITE [0 ] 0 -S_R Ack [0 ] 0 -S_R Data [0 ] 0 -S_R All_acks_and_data_no_sharers [0 ] 0 -S_R GETF [0 ] 0 - -NO_R GETX [0 ] 0 -NO_R GETS [0 ] 0 -NO_R PUT [0 ] 0 -NO_R Pf_Replacement [0 ] 0 -NO_R DMA_READ [0 ] 0 -NO_R DMA_WRITE [0 ] 0 -NO_R Ack [0 ] 0 -NO_R Data [0 ] 0 -NO_R Exclusive_Data [0 ] 0 -NO_R All_acks_and_data_no_sharers [0 ] 0 -NO_R GETF [0 ] 0 - -NO_B GETX [0 ] 0 -NO_B GETS [0 ] 0 -NO_B PUT [0 ] 0 -NO_B UnblockS [0 ] 0 -NO_B UnblockM [440 ] 440 -NO_B Pf_Replacement [0 ] 0 -NO_B DMA_READ [0 ] 0 -NO_B DMA_WRITE [0 ] 0 -NO_B GETF [0 ] 0 - -NO_B_X GETX [0 ] 0 -NO_B_X GETS [0 ] 0 -NO_B_X PUT [0 ] 0 -NO_B_X UnblockS [0 ] 0 -NO_B_X UnblockM [0 ] 0 -NO_B_X Pf_Replacement [0 ] 0 -NO_B_X DMA_READ [0 ] 0 -NO_B_X DMA_WRITE [0 ] 0 -NO_B_X GETF [0 ] 0 - -NO_B_S GETX [0 ] 0 -NO_B_S GETS [0 ] 0 -NO_B_S PUT [0 ] 0 -NO_B_S UnblockS [0 ] 0 -NO_B_S UnblockM [0 ] 0 -NO_B_S Pf_Replacement [0 ] 0 -NO_B_S DMA_READ [0 ] 0 -NO_B_S DMA_WRITE [0 ] 0 -NO_B_S GETF [0 ] 0 - -NO_B_S_W GETX [0 ] 0 -NO_B_S_W GETS [0 ] 0 -NO_B_S_W PUT [0 ] 0 -NO_B_S_W UnblockS [0 ] 0 -NO_B_S_W Pf_Replacement [0 ] 0 -NO_B_S_W DMA_READ [0 ] 0 -NO_B_S_W DMA_WRITE [0 ] 0 -NO_B_S_W All_Unblocks [0 ] 0 -NO_B_S_W GETF [0 ] 0 - -O_B GETX [0 ] 0 -O_B GETS [0 ] 0 -O_B PUT [0 ] 0 -O_B UnblockS [0 ] 0 -O_B UnblockM [0 ] 0 -O_B Pf_Replacement [0 ] 0 -O_B DMA_READ [0 ] 0 -O_B DMA_WRITE [0 ] 0 -O_B GETF [0 ] 0 - -NO_B_W GETX [0 ] 0 -NO_B_W GETS [0 ] 0 -NO_B_W PUT [0 ] 0 -NO_B_W UnblockS [0 ] 0 -NO_B_W UnblockM [0 ] 0 -NO_B_W Pf_Replacement [0 ] 0 -NO_B_W DMA_READ [0 ] 0 -NO_B_W DMA_WRITE [0 ] 0 -NO_B_W Memory_Data [441 ] 441 -NO_B_W GETF [0 ] 0 - -O_B_W GETX [0 ] 0 -O_B_W GETS [0 ] 0 -O_B_W PUT [0 ] 0 -O_B_W UnblockS [0 ] 0 -O_B_W Pf_Replacement [0 ] 0 -O_B_W DMA_READ [0 ] 0 -O_B_W DMA_WRITE [0 ] 0 -O_B_W Memory_Data [0 ] 0 -O_B_W GETF [0 ] 0 - -NO_W GETX [0 ] 0 -NO_W GETS [0 ] 0 -NO_W PUT [0 ] 0 -NO_W Pf_Replacement [0 ] 0 -NO_W DMA_READ [0 ] 0 -NO_W DMA_WRITE [0 ] 0 -NO_W Memory_Data [0 ] 0 -NO_W GETF [0 ] 0 - -O_W GETX [0 ] 0 -O_W GETS [0 ] 0 -O_W PUT [0 ] 0 -O_W Pf_Replacement [0 ] 0 -O_W DMA_READ [0 ] 0 -O_W DMA_WRITE [0 ] 0 -O_W Memory_Data [0 ] 0 -O_W GETF [0 ] 0 - -NO_DW_B_W GETX [0 ] 0 -NO_DW_B_W GETS [0 ] 0 -NO_DW_B_W PUT [0 ] 0 -NO_DW_B_W Pf_Replacement [0 ] 0 -NO_DW_B_W DMA_READ [0 ] 0 -NO_DW_B_W DMA_WRITE [0 ] 0 -NO_DW_B_W Ack [0 ] 0 -NO_DW_B_W Data [0 ] 0 -NO_DW_B_W Exclusive_Data [0 ] 0 -NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0 -NO_DW_B_W GETF [0 ] 0 - -NO_DR_B_W GETX [0 ] 0 -NO_DR_B_W GETS [0 ] 0 -NO_DR_B_W PUT [0 ] 0 -NO_DR_B_W Pf_Replacement [0 ] 0 -NO_DR_B_W DMA_READ [0 ] 0 -NO_DR_B_W DMA_WRITE [0 ] 0 -NO_DR_B_W Memory_Data [0 ] 0 -NO_DR_B_W Ack [0 ] 0 -NO_DR_B_W Shared_Ack [0 ] 0 -NO_DR_B_W Shared_Data [0 ] 0 -NO_DR_B_W Data [0 ] 0 -NO_DR_B_W Exclusive_Data [0 ] 0 -NO_DR_B_W GETF [0 ] 0 - -NO_DR_B_D GETX [0 ] 0 -NO_DR_B_D GETS [0 ] 0 -NO_DR_B_D PUT [0 ] 0 -NO_DR_B_D Pf_Replacement [0 ] 0 -NO_DR_B_D DMA_READ [0 ] 0 -NO_DR_B_D DMA_WRITE [0 ] 0 -NO_DR_B_D Ack [0 ] 0 -NO_DR_B_D Shared_Ack [0 ] 0 -NO_DR_B_D Shared_Data [0 ] 0 -NO_DR_B_D Data [0 ] 0 -NO_DR_B_D Exclusive_Data [0 ] 0 -NO_DR_B_D All_acks_and_shared_data [0 ] 0 -NO_DR_B_D All_acks_and_owner_data [0 ] 0 -NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0 -NO_DR_B_D GETF [0 ] 0 - -NO_DR_B GETX [0 ] 0 -NO_DR_B GETS [0 ] 0 -NO_DR_B PUT [0 ] 0 -NO_DR_B Pf_Replacement [0 ] 0 -NO_DR_B DMA_READ [0 ] 0 -NO_DR_B DMA_WRITE [0 ] 0 -NO_DR_B Ack [0 ] 0 -NO_DR_B Shared_Ack [0 ] 0 -NO_DR_B Shared_Data [0 ] 0 -NO_DR_B Data [0 ] 0 -NO_DR_B Exclusive_Data [0 ] 0 -NO_DR_B All_acks_and_shared_data [0 ] 0 -NO_DR_B All_acks_and_owner_data [0 ] 0 -NO_DR_B All_acks_and_data_no_sharers [0 ] 0 -NO_DR_B GETF [0 ] 0 - -NO_DW_W GETX [0 ] 0 -NO_DW_W GETS [0 ] 0 -NO_DW_W PUT [0 ] 0 -NO_DW_W Pf_Replacement [0 ] 0 -NO_DW_W DMA_READ [0 ] 0 -NO_DW_W DMA_WRITE [0 ] 0 -NO_DW_W Memory_Ack [0 ] 0 -NO_DW_W GETF [0 ] 0 - -O_DR_B_W GETX [0 ] 0 -O_DR_B_W GETS [0 ] 0 -O_DR_B_W PUT [0 ] 0 -O_DR_B_W Pf_Replacement [0 ] 0 -O_DR_B_W DMA_READ [0 ] 0 -O_DR_B_W DMA_WRITE [0 ] 0 -O_DR_B_W Memory_Data [0 ] 0 -O_DR_B_W Ack [0 ] 0 -O_DR_B_W Shared_Ack [0 ] 0 -O_DR_B_W GETF [0 ] 0 - -O_DR_B GETX [0 ] 0 -O_DR_B GETS [0 ] 0 -O_DR_B PUT [0 ] 0 -O_DR_B Pf_Replacement [0 ] 0 -O_DR_B DMA_READ [0 ] 0 -O_DR_B DMA_WRITE [0 ] 0 -O_DR_B Ack [0 ] 0 -O_DR_B Shared_Ack [0 ] 0 -O_DR_B All_acks_and_owner_data [0 ] 0 -O_DR_B All_acks_and_data_no_sharers [0 ] 0 -O_DR_B GETF [0 ] 0 - -WB GETX [4 ] 4 -WB GETS [14 ] 14 -WB PUT [0 ] 0 -WB Unblock [0 ] 0 -WB Writeback_Clean [0 ] 0 -WB Writeback_Dirty [0 ] 0 -WB Writeback_Exclusive_Clean [344 ] 344 -WB Writeback_Exclusive_Dirty [81 ] 81 -WB Pf_Replacement [0 ] 0 -WB DMA_READ [0 ] 0 -WB DMA_WRITE [0 ] 0 -WB GETF [0 ] 0 - -WB_O_W GETX [0 ] 0 -WB_O_W GETS [0 ] 0 -WB_O_W PUT [0 ] 0 -WB_O_W Pf_Replacement [0 ] 0 -WB_O_W DMA_READ [0 ] 0 -WB_O_W DMA_WRITE [0 ] 0 -WB_O_W Memory_Ack [0 ] 0 -WB_O_W GETF [0 ] 0 - -WB_E_W GETX [0 ] 0 -WB_E_W GETS [2 ] 2 -WB_E_W PUT [0 ] 0 -WB_E_W Pf_Replacement [0 ] 0 -WB_E_W DMA_READ [0 ] 0 -WB_E_W DMA_WRITE [0 ] 0 -WB_E_W Memory_Ack [81 ] 81 -WB_E_W GETF [0 ] 0 - -NO_F GETX [0 ] 0 -NO_F GETS [0 ] 0 -NO_F PUT [0 ] 0 -NO_F UnblockM [0 ] 0 -NO_F Pf_Replacement [0 ] 0 -NO_F GETF [0 ] 0 -NO_F PUTF [0 ] 0 - -NO_F_W GETX [0 ] 0 -NO_F_W GETS [0 ] 0 -NO_F_W PUT [0 ] 0 -NO_F_W Pf_Replacement [0 ] 0 -NO_F_W DMA_READ [0 ] 0 -NO_F_W DMA_WRITE [0 ] 0 -NO_F_W Memory_Data [0 ] 0 -NO_F_W GETF [0 ] 0 - diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index d3fbb9bcf..f1ed0212f 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000035 # Nu sim_ticks 35432 # Number of ticks simulated final_tick 35432 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 17259 # Simulator instruction rate (inst/s) -host_op_rate 17257 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 237238 # Simulator tick rate (ticks/s) -host_mem_usage 151196 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 14099 # Simulator instruction rate (inst/s) +host_op_rate 14097 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 193809 # Simulator tick rate (ticks/s) +host_mem_usage 145312 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.ruby.l1_cntrl0.L1Dcache.demand_hits 469 # Number of cache demand hits @@ -20,6 +20,20 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 system.ruby.l1_cntrl0.L2cache.demand_hits 69 # Number of cache demand hits system.ruby.l1_cntrl0.L2cache.demand_misses 441 # Number of cache demand misses system.ruby.l1_cntrl0.L2cache.demand_accesses 510 # Number of cache demand accesses +system.ruby.dir_cntrl0.memBuffer.memReq 522 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 441 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 81 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 246 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 39 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 39 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.074713 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 15 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 15 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 4 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 5 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 18 3.45% 3.45% | 10 1.92% 5.36% | 0 0.00% 5.36% | 36 6.90% 12.26% | 20 3.83% 16.09% | 19 3.64% 19.73% | 31 5.94% 25.67% | 22 4.21% 29.89% | 5 0.96% 30.84% | 4 0.77% 31.61% | 7 1.34% 32.95% | 4 0.77% 33.72% | 22 4.21% 37.93% | 41 7.85% 45.79% | 22 4.21% 50.00% | 3 0.57% 50.57% | 4 0.77% 51.34% | 6 1.15% 52.49% | 7 1.34% 53.83% | 13 2.49% 56.32% | 10 1.92% 58.24% | 18 3.45% 61.69% | 14 2.68% 64.37% | 41 7.85% 72.22% | 16 3.07% 75.29% | 5 0.96% 76.25% | 5 0.96% 77.20% | 12 2.30% 79.50% | 13 2.49% 81.99% | 18 3.45% 85.44% | 14 2.68% 88.12% | 62 11.88% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 522 # Number of accesses per bank + system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses @@ -78,5 +92,65 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 35432 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles +system.ruby.l1_cntrl0.Load 422 0.00% 0.00% +system.ruby.l1_cntrl0.Ifetch 2591 0.00% 0.00% +system.ruby.l1_cntrl0.Store 298 0.00% 0.00% +system.ruby.l1_cntrl0.L2_Replacement 425 0.00% 0.00% +system.ruby.l1_cntrl0.L1_to_L2 502 0.00% 0.00% +system.ruby.l1_cntrl0.Trigger_L2_to_L1D 47 0.00% 0.00% +system.ruby.l1_cntrl0.Trigger_L2_to_L1I 22 0.00% 0.00% +system.ruby.l1_cntrl0.Complete_L2_to_L1 69 0.00% 0.00% +system.ruby.l1_cntrl0.Exclusive_Data 441 0.00% 0.00% +system.ruby.l1_cntrl0.Writeback_Ack 425 0.00% 0.00% +system.ruby.l1_cntrl0.All_acks_no_sharers 441 0.00% 0.00% +system.ruby.l1_cntrl0.I.Load 146 0.00% 0.00% +system.ruby.l1_cntrl0.I.Ifetch 248 0.00% 0.00% +system.ruby.l1_cntrl0.I.Store 47 0.00% 0.00% +system.ruby.l1_cntrl0.M.Load 109 0.00% 0.00% +system.ruby.l1_cntrl0.M.Ifetch 2315 0.00% 0.00% +system.ruby.l1_cntrl0.M.Store 35 0.00% 0.00% +system.ruby.l1_cntrl0.M.L2_Replacement 344 0.00% 0.00% +system.ruby.l1_cntrl0.M.L1_to_L2 397 0.00% 0.00% +system.ruby.l1_cntrl0.M.Trigger_L2_to_L1D 23 0.00% 0.00% +system.ruby.l1_cntrl0.M.Trigger_L2_to_L1I 22 0.00% 0.00% +system.ruby.l1_cntrl0.MM.Load 124 0.00% 0.00% +system.ruby.l1_cntrl0.MM.Store 201 0.00% 0.00% +system.ruby.l1_cntrl0.MM.L2_Replacement 81 0.00% 0.00% +system.ruby.l1_cntrl0.MM.L1_to_L2 105 0.00% 0.00% +system.ruby.l1_cntrl0.MM.Trigger_L2_to_L1D 24 0.00% 0.00% +system.ruby.l1_cntrl0.MR.Load 22 0.00% 0.00% +system.ruby.l1_cntrl0.MR.Ifetch 22 0.00% 0.00% +system.ruby.l1_cntrl0.MR.Store 1 0.00% 0.00% +system.ruby.l1_cntrl0.MMR.Load 14 0.00% 0.00% +system.ruby.l1_cntrl0.MMR.Store 10 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Exclusive_Data 47 0.00% 0.00% +system.ruby.l1_cntrl0.M_W.All_acks_no_sharers 394 0.00% 0.00% +system.ruby.l1_cntrl0.MM_W.All_acks_no_sharers 47 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Exclusive_Data 394 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Load 7 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Ifetch 6 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Store 4 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Writeback_Ack 425 0.00% 0.00% +system.ruby.l1_cntrl0.MT.Complete_L2_to_L1 45 0.00% 0.00% +system.ruby.l1_cntrl0.MMT.Complete_L2_to_L1 24 0.00% 0.00% +system.ruby.dir_cntrl0.GETX 51 0.00% 0.00% +system.ruby.dir_cntrl0.GETS 410 0.00% 0.00% +system.ruby.dir_cntrl0.PUT 425 0.00% 0.00% +system.ruby.dir_cntrl0.UnblockM 440 0.00% 0.00% +system.ruby.dir_cntrl0.Writeback_Exclusive_Clean 344 0.00% 0.00% +system.ruby.dir_cntrl0.Writeback_Exclusive_Dirty 81 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 441 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 81 0.00% 0.00% +system.ruby.dir_cntrl0.NO.PUT 425 0.00% 0.00% +system.ruby.dir_cntrl0.E.GETX 47 0.00% 0.00% +system.ruby.dir_cntrl0.E.GETS 394 0.00% 0.00% +system.ruby.dir_cntrl0.NO_B.UnblockM 440 0.00% 0.00% +system.ruby.dir_cntrl0.NO_B_W.Memory_Data 441 0.00% 0.00% +system.ruby.dir_cntrl0.WB.GETX 4 0.00% 0.00% +system.ruby.dir_cntrl0.WB.GETS 14 0.00% 0.00% +system.ruby.dir_cntrl0.WB.Writeback_Exclusive_Clean 344 0.00% 0.00% +system.ruby.dir_cntrl0.WB.Writeback_Exclusive_Dirty 81 0.00% 0.00% +system.ruby.dir_cntrl0.WB_E_W.GETS 2 0.00% 0.00% +system.ruby.dir_cntrl0.WB_E_W.Memory_Ack 81 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats index 819d00fb8..4ce431f90 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats @@ -1,4 +1,4 @@ -Real time: Mar/06/2013 20:31:07 +Real time: Jun/08/2013 13:43:10 Profiler Stats -------------- @@ -7,20 +7,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.51 -Virtual_time_in_minutes: 0.0085 -Virtual_time_in_hours: 0.000141667 -Virtual_time_in_days: 5.90278e-06 +Virtual_time_in_seconds: 0.44 +Virtual_time_in_minutes: 0.00733333 +Virtual_time_in_hours: 0.000122222 +Virtual_time_in_days: 5.09259e-06 Ruby_current_time: 52498 Ruby_start_time: 0 Ruby_cycles: 52498 -mbytes_resident: 53.0938 -mbytes_total: 145.422 -resident_ratio: 0.365182 - -ruby_cycles_executed: [ 52499 ] +mbytes_resident: 53.0039 +mbytes_total: 140.805 +resident_ratio: 0.376491 Busy Controller Counts: L1Cache-0:0 @@ -64,7 +62,6 @@ Request vs. RubySystem State Profile -------------------------------- -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- @@ -85,10 +82,10 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10892 +page_reclaims: 11286 page_faults: 0 swaps: 0 -block_inputs: 1328 +block_inputs: 0 block_outputs: 88 Network Stats @@ -133,129 +130,3 @@ links_utilized_percent_switch_2: 5.94308 outgoing_messages_switch_2_link_1_Control: 626 5008 [ 0 0 626 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Data: 622 44784 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1 - --- L1Cache --- - - Event Counts - -Load [415 ] 415 -Ifetch [2585 ] 2585 -Store [294 ] 294 -Data [626 ] 626 -Fwd_GETX [0 ] 0 -Inv [0 ] 0 -Replacement [622 ] 622 -Writeback_Ack [622 ] 622 -Writeback_Nack [0 ] 0 - - - Transitions - -I Load [245 ] 245 -I Ifetch [297 ] 297 -I Store [84 ] 84 -I Inv [0 ] 0 -I Replacement [0 ] 0 - -II Writeback_Nack [0 ] 0 - -M Load [170 ] 170 -M Ifetch [2288 ] 2288 -M Store [210 ] 210 -M Fwd_GETX [0 ] 0 -M Inv [0 ] 0 -M Replacement [622 ] 622 - -MI Fwd_GETX [0 ] 0 -MI Inv [0 ] 0 -MI Writeback_Ack [622 ] 622 -MI Writeback_Nack [0 ] 0 - -MII Fwd_GETX [0 ] 0 - -IS Data [542 ] 542 - -IM Data [84 ] 84 - -Memory controller: system.ruby.dir_cntrl0.memBuffer: - memory_total_requests: 1248 - memory_reads: 626 - memory_writes: 622 - memory_refreshes: 365 - memory_total_request_delays: 915 - memory_delays_per_request: 0.733173 - memory_delays_in_input_queue: 0 - memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 915 - memory_stalls_for_bank_busy: 352 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 40 - memory_stalls_for_bus: 497 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 26 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 55 40 0 100 42 42 88 45 14 10 14 10 46 82 38 6 22 14 14 48 20 52 26 92 34 10 12 24 28 44 38 138 - - --- Directory --- - - Event Counts - -GETX [626 ] 626 -GETS [0 ] 0 -PUTX [622 ] 622 -PUTX_NotOwner [0 ] 0 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -Memory_Data [626 ] 626 -Memory_Ack [622 ] 622 - - - Transitions - -I GETX [626 ] 626 -I PUTX_NotOwner [0 ] 0 -I DMA_READ [0 ] 0 -I DMA_WRITE [0 ] 0 - -M GETX [0 ] 0 -M PUTX [622 ] 622 -M PUTX_NotOwner [0 ] 0 -M DMA_READ [0 ] 0 -M DMA_WRITE [0 ] 0 - -M_DRD GETX [0 ] 0 -M_DRD PUTX [0 ] 0 - -M_DWR GETX [0 ] 0 -M_DWR PUTX [0 ] 0 - -M_DWRI GETX [0 ] 0 -M_DWRI Memory_Ack [0 ] 0 - -M_DRDI GETX [0 ] 0 -M_DRDI Memory_Ack [0 ] 0 - -IM GETX [0 ] 0 -IM GETS [0 ] 0 -IM PUTX [0 ] 0 -IM PUTX_NotOwner [0 ] 0 -IM DMA_READ [0 ] 0 -IM DMA_WRITE [0 ] 0 -IM Memory_Data [626 ] 626 - -MI GETX [0 ] 0 -MI GETS [0 ] 0 -MI PUTX [0 ] 0 -MI PUTX_NotOwner [0 ] 0 -MI DMA_READ [0 ] 0 -MI DMA_WRITE [0 ] 0 -MI Memory_Ack [622 ] 622 - -ID GETX [0 ] 0 -ID GETS [0 ] 0 -ID PUTX [0 ] 0 -ID PUTX_NotOwner [0 ] 0 -ID DMA_READ [0 ] 0 -ID DMA_WRITE [0 ] 0 -ID Memory_Data [0 ] 0 - -ID_W GETX [0 ] 0 -ID_W GETS [0 ] 0 -ID_W PUTX [0 ] 0 -ID_W PUTX_NotOwner [0 ] 0 -ID_W DMA_READ [0 ] 0 -ID_W DMA_WRITE [0 ] 0 -ID_W Memory_Ack [0 ] 0 - diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index 98abd69d6..408d1d326 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -4,16 +4,30 @@ sim_seconds 0.000052 # Nu sim_ticks 52498 # Number of ticks simulated final_tick 52498 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 9649 # Simulator instruction rate (inst/s) -host_op_rate 9649 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 196549 # Simulator tick rate (ticks/s) -host_mem_usage 151788 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host +host_inst_rate 30872 # Simulator instruction rate (inst/s) +host_op_rate 30864 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 628609 # Simulator tick rate (ticks/s) +host_mem_usage 144188 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses +system.ruby.dir_cntrl0.memBuffer.memReq 1248 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 626 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 622 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 365 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 915 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 915 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.733173 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 352 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 497 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 26 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 40 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 55 4.41% 4.41% | 40 3.21% 7.61% | 0 0.00% 7.61% | 100 8.01% 15.62% | 42 3.37% 18.99% | 42 3.37% 22.36% | 88 7.05% 29.41% | 45 3.61% 33.01% | 14 1.12% 34.13% | 10 0.80% 34.94% | 14 1.12% 36.06% | 10 0.80% 36.86% | 46 3.69% 40.54% | 82 6.57% 47.12% | 38 3.04% 50.16% | 6 0.48% 50.64% | 22 1.76% 52.40% | 14 1.12% 53.53% | 14 1.12% 54.65% | 48 3.85% 58.49% | 20 1.60% 60.10% | 52 4.17% 64.26% | 26 2.08% 66.35% | 92 7.37% 73.72% | 34 2.72% 76.44% | 10 0.80% 77.24% | 12 0.96% 78.21% | 24 1.92% 80.13% | 28 2.24% 82.37% | 44 3.53% 85.90% | 38 3.04% 88.94% | 138 11.06% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1248 # Number of accesses per bank + system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -69,5 +83,29 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 52498 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles +system.ruby.l1_cntrl0.Load 415 0.00% 0.00% +system.ruby.l1_cntrl0.Ifetch 2585 0.00% 0.00% +system.ruby.l1_cntrl0.Store 294 0.00% 0.00% +system.ruby.l1_cntrl0.Data 626 0.00% 0.00% +system.ruby.l1_cntrl0.Replacement 622 0.00% 0.00% +system.ruby.l1_cntrl0.Writeback_Ack 622 0.00% 0.00% +system.ruby.l1_cntrl0.I.Load 245 0.00% 0.00% +system.ruby.l1_cntrl0.I.Ifetch 297 0.00% 0.00% +system.ruby.l1_cntrl0.I.Store 84 0.00% 0.00% +system.ruby.l1_cntrl0.M.Load 170 0.00% 0.00% +system.ruby.l1_cntrl0.M.Ifetch 2288 0.00% 0.00% +system.ruby.l1_cntrl0.M.Store 210 0.00% 0.00% +system.ruby.l1_cntrl0.M.Replacement 622 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Writeback_Ack 622 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data 542 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Data 84 0.00% 0.00% +system.ruby.dir_cntrl0.GETX 626 0.00% 0.00% +system.ruby.dir_cntrl0.PUTX 622 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 626 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 622 0.00% 0.00% +system.ruby.dir_cntrl0.I.GETX 626 0.00% 0.00% +system.ruby.dir_cntrl0.M.PUTX 622 0.00% 0.00% +system.ruby.dir_cntrl0.IM.Memory_Data 626 0.00% 0.00% +system.ruby.dir_cntrl0.MI.Memory_Ack 622 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 2410b0ce7..7f2c21c70 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -4,16 +4,31 @@ sim_seconds 0.000125 # Nu sim_ticks 125334 # Number of ticks simulated final_tick 125334 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 24800 # Simulator instruction rate (inst/s) -host_op_rate 24798 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 534538 # Simulator tick rate (ticks/s) -host_mem_usage 154892 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host +host_inst_rate 43626 # Simulator instruction rate (inst/s) +host_op_rate 43619 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 940162 # Simulator tick rate (ticks/s) +host_mem_usage 147408 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.ruby.l1_cntrl0.cacheMemory.demand_hits 6410 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1493 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7903 # Number of cache demand accesses +system.ruby.dir_cntrl0.memBuffer.memReq 2982 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 1493 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 1489 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 871 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 2125 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memBankQ 5 # Delay behind the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 2130 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.714286 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 839 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 1172 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 34 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 80 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 236 7.91% 7.91% | 108 3.62% 11.54% | 74 2.48% 14.02% | 51 1.71% 15.73% | 26 0.87% 16.60% | 104 3.49% 20.09% | 18 0.60% 20.69% | 38 1.27% 21.97% | 16 0.54% 22.50% | 52 1.74% 24.25% | 154 5.16% 29.41% | 50 1.68% 31.09% | 22 0.74% 31.82% | 70 2.35% 34.17% | 30 1.01% 35.18% | 220 7.38% 42.56% | 80 2.68% 45.24% | 58 1.95% 47.18% | 80 2.68% 49.87% | 118 3.96% 53.82% | 42 1.41% 55.23% | 52 1.74% 56.98% | 82 2.75% 59.73% | 168 5.63% 65.36% | 116 3.89% 69.25% | 80 2.68% 71.93% | 138 4.63% 76.56% | 110 3.69% 80.25% | 208 6.98% 87.22% | 273 9.15% 96.38% | 40 1.34% 97.72% | 68 2.28% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 2982 # Number of accesses per bank + system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -55,5 +70,29 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 125334 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles +system.ruby.l1_cntrl0.Load 1163 0.00% 0.00% +system.ruby.l1_cntrl0.Ifetch 5815 0.00% 0.00% +system.ruby.l1_cntrl0.Store 925 0.00% 0.00% +system.ruby.l1_cntrl0.Data 1493 0.00% 0.00% +system.ruby.l1_cntrl0.Replacement 1489 0.00% 0.00% +system.ruby.l1_cntrl0.Writeback_Ack 1489 0.00% 0.00% +system.ruby.l1_cntrl0.I.Load 677 0.00% 0.00% +system.ruby.l1_cntrl0.I.Ifetch 596 0.00% 0.00% +system.ruby.l1_cntrl0.I.Store 220 0.00% 0.00% +system.ruby.l1_cntrl0.M.Load 486 0.00% 0.00% +system.ruby.l1_cntrl0.M.Ifetch 5219 0.00% 0.00% +system.ruby.l1_cntrl0.M.Store 705 0.00% 0.00% +system.ruby.l1_cntrl0.M.Replacement 1489 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Writeback_Ack 1489 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data 1273 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Data 220 0.00% 0.00% +system.ruby.dir_cntrl0.GETX 1493 0.00% 0.00% +system.ruby.dir_cntrl0.PUTX 1489 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 1493 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 1489 0.00% 0.00% +system.ruby.dir_cntrl0.I.GETX 1493 0.00% 0.00% +system.ruby.dir_cntrl0.M.PUTX 1489 0.00% 0.00% +system.ruby.dir_cntrl0.IM.Memory_Data 1493 0.00% 0.00% +system.ruby.dir_cntrl0.MI.Memory_Ack 1489 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats index 97d6545aa..0cadf0143 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats @@ -1,4 +1,4 @@ -Real time: Mar/06/2013 20:57:13 +Real time: Jun/08/2013 14:17:53 Profiler Stats -------------- @@ -7,20 +7,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.57 -Virtual_time_in_minutes: 0.0095 -Virtual_time_in_hours: 0.000158333 -Virtual_time_in_days: 6.59722e-06 +Virtual_time_in_seconds: 0.49 +Virtual_time_in_minutes: 0.00816667 +Virtual_time_in_hours: 0.000136111 +Virtual_time_in_days: 5.6713e-06 Ruby_current_time: 107952 Ruby_start_time: 0 Ruby_cycles: 107952 -mbytes_resident: 55.75 -mbytes_total: 154.406 -resident_ratio: 0.361111 - -ruby_cycles_executed: [ 107953 ] +mbytes_resident: 55.6289 +mbytes_total: 144.984 +resident_ratio: 0.383743 Busy Controller Counts: L1Cache-0:0 @@ -64,7 +62,6 @@ Request vs. RubySystem State Profile -------------------------------- -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- @@ -85,10 +82,10 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 12080 -page_faults: 2 +page_reclaims: 11996 +page_faults: 0 swaps: 0 -block_inputs: 32 +block_inputs: 0 block_outputs: 88 Network Stats @@ -133,129 +130,3 @@ links_utilized_percent_switch_2: 5.96098 outgoing_messages_switch_2_link_1_Control: 1289 10312 [ 0 0 1289 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Data: 1285 92520 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1 - --- L1Cache --- - - Event Counts - -Load [715 ] 715 -Ifetch [5370 ] 5370 -Store [673 ] 673 -Data [1289 ] 1289 -Fwd_GETX [0 ] 0 -Inv [0 ] 0 -Replacement [1285 ] 1285 -Writeback_Ack [1285 ] 1285 -Writeback_Nack [0 ] 0 - - - Transitions - -I Load [395 ] 395 -I Ifetch [715 ] 715 -I Store [179 ] 179 -I Inv [0 ] 0 -I Replacement [0 ] 0 - -II Writeback_Nack [0 ] 0 - -M Load [320 ] 320 -M Ifetch [4655 ] 4655 -M Store [494 ] 494 -M Fwd_GETX [0 ] 0 -M Inv [0 ] 0 -M Replacement [1285 ] 1285 - -MI Fwd_GETX [0 ] 0 -MI Inv [0 ] 0 -MI Writeback_Ack [1285 ] 1285 -MI Writeback_Nack [0 ] 0 - -MII Fwd_GETX [0 ] 0 - -IS Data [1110 ] 1110 - -IM Data [179 ] 179 - -Memory controller: system.ruby.dir_cntrl0.memBuffer: - memory_total_requests: 2574 - memory_reads: 1289 - memory_writes: 1285 - memory_refreshes: 750 - memory_total_request_delays: 1873 - memory_delays_per_request: 0.727661 - memory_delays_in_input_queue: 0 - memory_delays_behind_head_of_bank_queue: 2 - memory_delays_stalled_at_head_of_bank_queue: 1871 - memory_stalls_for_bank_busy: 758 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 69 - memory_stalls_for_bus: 992 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 52 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 166 40 36 48 109 42 63 241 50 34 16 26 60 64 38 46 30 88 202 144 40 58 22 20 60 120 136 125 84 134 166 66 - - --- Directory --- - - Event Counts - -GETX [1289 ] 1289 -GETS [0 ] 0 -PUTX [1285 ] 1285 -PUTX_NotOwner [0 ] 0 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -Memory_Data [1289 ] 1289 -Memory_Ack [1285 ] 1285 - - - Transitions - -I GETX [1289 ] 1289 -I PUTX_NotOwner [0 ] 0 -I DMA_READ [0 ] 0 -I DMA_WRITE [0 ] 0 - -M GETX [0 ] 0 -M PUTX [1285 ] 1285 -M PUTX_NotOwner [0 ] 0 -M DMA_READ [0 ] 0 -M DMA_WRITE [0 ] 0 - -M_DRD GETX [0 ] 0 -M_DRD PUTX [0 ] 0 - -M_DWR GETX [0 ] 0 -M_DWR PUTX [0 ] 0 - -M_DWRI GETX [0 ] 0 -M_DWRI Memory_Ack [0 ] 0 - -M_DRDI GETX [0 ] 0 -M_DRDI Memory_Ack [0 ] 0 - -IM GETX [0 ] 0 -IM GETS [0 ] 0 -IM PUTX [0 ] 0 -IM PUTX_NotOwner [0 ] 0 -IM DMA_READ [0 ] 0 -IM DMA_WRITE [0 ] 0 -IM Memory_Data [1289 ] 1289 - -MI GETX [0 ] 0 -MI GETS [0 ] 0 -MI PUTX [0 ] 0 -MI PUTX_NotOwner [0 ] 0 -MI DMA_READ [0 ] 0 -MI DMA_WRITE [0 ] 0 -MI Memory_Ack [1285 ] 1285 - -ID GETX [0 ] 0 -ID GETS [0 ] 0 -ID PUTX [0 ] 0 -ID PUTX_NotOwner [0 ] 0 -ID DMA_READ [0 ] 0 -ID DMA_WRITE [0 ] 0 -ID Memory_Data [0 ] 0 - -ID_W GETX [0 ] 0 -ID_W GETS [0 ] 0 -ID_W PUTX [0 ] 0 -ID_W PUTX_NotOwner [0 ] 0 -ID_W DMA_READ [0 ] 0 -ID_W DMA_WRITE [0 ] 0 -ID_W Memory_Ack [0 ] 0 - diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index 1ca0b6acd..87117a3bf 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -4,16 +4,31 @@ sim_seconds 0.000108 # Nu sim_ticks 107952 # Number of ticks simulated final_tick 107952 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 36056 # Simulator instruction rate (inst/s) -host_op_rate 36051 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 730482 # Simulator tick rate (ticks/s) -host_mem_usage 160860 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 37306 # Simulator instruction rate (inst/s) +host_op_rate 37301 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 755806 # Simulator tick rate (ticks/s) +host_mem_usage 148468 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses +system.ruby.dir_cntrl0.memBuffer.memReq 2574 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 1289 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 1285 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 750 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 1871 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memBankQ 2 # Delay behind the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 1873 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.727661 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 758 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 992 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 52 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 69 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 166 6.45% 6.45% | 40 1.55% 8.00% | 36 1.40% 9.40% | 48 1.86% 11.27% | 109 4.23% 15.50% | 42 1.63% 17.13% | 63 2.45% 19.58% | 241 9.36% 28.94% | 50 1.94% 30.89% | 34 1.32% 32.21% | 16 0.62% 32.83% | 26 1.01% 33.84% | 60 2.33% 36.17% | 64 2.49% 38.66% | 38 1.48% 40.13% | 46 1.79% 41.92% | 30 1.17% 43.08% | 88 3.42% 46.50% | 202 7.85% 54.35% | 144 5.59% 59.95% | 40 1.55% 61.50% | 58 2.25% 63.75% | 22 0.85% 64.61% | 20 0.78% 65.38% | 60 2.33% 67.72% | 120 4.66% 72.38% | 136 5.28% 77.66% | 125 4.86% 82.52% | 84 3.26% 85.78% | 134 5.21% 90.99% | 166 6.45% 97.44% | 66 2.56% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 2574 # Number of accesses per bank + system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 107952 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -37,5 +52,29 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 107952 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles +system.ruby.l1_cntrl0.Load 715 0.00% 0.00% +system.ruby.l1_cntrl0.Ifetch 5370 0.00% 0.00% +system.ruby.l1_cntrl0.Store 673 0.00% 0.00% +system.ruby.l1_cntrl0.Data 1289 0.00% 0.00% +system.ruby.l1_cntrl0.Replacement 1285 0.00% 0.00% +system.ruby.l1_cntrl0.Writeback_Ack 1285 0.00% 0.00% +system.ruby.l1_cntrl0.I.Load 395 0.00% 0.00% +system.ruby.l1_cntrl0.I.Ifetch 715 0.00% 0.00% +system.ruby.l1_cntrl0.I.Store 179 0.00% 0.00% +system.ruby.l1_cntrl0.M.Load 320 0.00% 0.00% +system.ruby.l1_cntrl0.M.Ifetch 4655 0.00% 0.00% +system.ruby.l1_cntrl0.M.Store 494 0.00% 0.00% +system.ruby.l1_cntrl0.M.Replacement 1285 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Writeback_Ack 1285 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data 1110 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Data 179 0.00% 0.00% +system.ruby.dir_cntrl0.GETX 1289 0.00% 0.00% +system.ruby.dir_cntrl0.PUTX 1285 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 1289 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 1285 0.00% 0.00% +system.ruby.dir_cntrl0.I.GETX 1289 0.00% 0.00% +system.ruby.dir_cntrl0.M.PUTX 1285 0.00% 0.00% +system.ruby.dir_cntrl0.IM.Memory_Data 1289 0.00% 0.00% +system.ruby.dir_cntrl0.MI.Memory_Ack 1285 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats index ba4f2ee21..459a4eba9 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats @@ -1,26 +1,24 @@ -Real time: Mar/11/2013 13:21:59 +Real time: Jun/08/2013 14:40:51 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.6 -Virtual_time_in_minutes: 0.01 -Virtual_time_in_hours: 0.000166667 -Virtual_time_in_days: 6.94444e-06 +Virtual_time_in_seconds: 0.54 +Virtual_time_in_minutes: 0.009 +Virtual_time_in_hours: 0.00015 +Virtual_time_in_days: 6.25e-06 Ruby_current_time: 121759 Ruby_start_time: 0 Ruby_cycles: 121759 -mbytes_resident: 66.582 -mbytes_total: 163.426 -resident_ratio: 0.407486 - -ruby_cycles_executed: [ 121760 ] +mbytes_resident: 66.5 +mbytes_total: 158.215 +resident_ratio: 0.420364 Busy Controller Counts: L1Cache-0:0 @@ -67,7 +65,6 @@ Request vs. RubySystem State Profile -------------------------------- -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- @@ -88,11 +85,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 14769 +page_reclaims: 13753 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 88 +block_outputs: 96 Network Stats ------------- @@ -136,129 +133,3 @@ links_utilized_percent_switch_2: 5.6464 outgoing_messages_switch_2_link_1_Control: 1377 11016 [ 0 0 1377 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Data: 1373 98856 [ 0 0 1373 0 0 0 0 0 0 0 ] base_latency: 1 - --- L1Cache --- - - Event Counts - -Load [1045 ] 1045 -Ifetch [6864 ] 6864 -Store [943 ] 943 -Data [1377 ] 1377 -Fwd_GETX [0 ] 0 -Inv [0 ] 0 -Replacement [1373 ] 1373 -Writeback_Ack [1373 ] 1373 -Writeback_Nack [0 ] 0 - - - Transitions - -I Load [499 ] 499 -I Ifetch [623 ] 623 -I Store [255 ] 255 -I Inv [0 ] 0 -I Replacement [0 ] 0 - -II Writeback_Nack [0 ] 0 - -M Load [546 ] 546 -M Ifetch [6241 ] 6241 -M Store [688 ] 688 -M Fwd_GETX [0 ] 0 -M Inv [0 ] 0 -M Replacement [1373 ] 1373 - -MI Fwd_GETX [0 ] 0 -MI Inv [0 ] 0 -MI Writeback_Ack [1373 ] 1373 -MI Writeback_Nack [0 ] 0 - -MII Fwd_GETX [0 ] 0 - -IS Data [1122 ] 1122 - -IM Data [255 ] 255 - -Memory controller: system.ruby.dir_cntrl0.memBuffer: - memory_total_requests: 2750 - memory_reads: 1377 - memory_writes: 1373 - memory_refreshes: 846 - memory_total_request_delays: 1968 - memory_delays_per_request: 0.715636 - memory_delays_in_input_queue: 0 - memory_delays_behind_head_of_bank_queue: 3 - memory_delays_stalled_at_head_of_bank_queue: 1965 - memory_stalls_for_bank_busy: 823 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 65 - memory_stalls_for_bus: 1044 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 33 - memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 160 144 210 146 196 96 66 38 22 20 184 297 71 124 60 18 84 6 8 14 92 56 14 60 34 58 84 66 42 122 104 54 - - --- Directory --- - - Event Counts - -GETX [1377 ] 1377 -GETS [0 ] 0 -PUTX [1373 ] 1373 -PUTX_NotOwner [0 ] 0 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -Memory_Data [1377 ] 1377 -Memory_Ack [1373 ] 1373 - - - Transitions - -I GETX [1377 ] 1377 -I PUTX_NotOwner [0 ] 0 -I DMA_READ [0 ] 0 -I DMA_WRITE [0 ] 0 - -M GETX [0 ] 0 -M PUTX [1373 ] 1373 -M PUTX_NotOwner [0 ] 0 -M DMA_READ [0 ] 0 -M DMA_WRITE [0 ] 0 - -M_DRD GETX [0 ] 0 -M_DRD PUTX [0 ] 0 - -M_DWR GETX [0 ] 0 -M_DWR PUTX [0 ] 0 - -M_DWRI GETX [0 ] 0 -M_DWRI Memory_Ack [0 ] 0 - -M_DRDI GETX [0 ] 0 -M_DRDI Memory_Ack [0 ] 0 - -IM GETX [0 ] 0 -IM GETS [0 ] 0 -IM PUTX [0 ] 0 -IM PUTX_NotOwner [0 ] 0 -IM DMA_READ [0 ] 0 -IM DMA_WRITE [0 ] 0 -IM Memory_Data [1377 ] 1377 - -MI GETX [0 ] 0 -MI GETS [0 ] 0 -MI PUTX [0 ] 0 -MI PUTX_NotOwner [0 ] 0 -MI DMA_READ [0 ] 0 -MI DMA_WRITE [0 ] 0 -MI Memory_Ack [1373 ] 1373 - -ID GETX [0 ] 0 -ID GETS [0 ] 0 -ID PUTX [0 ] 0 -ID PUTX_NotOwner [0 ] 0 -ID DMA_READ [0 ] 0 -ID DMA_WRITE [0 ] 0 -ID Memory_Data [0 ] 0 - -ID_W GETX [0 ] 0 -ID_W GETS [0 ] 0 -ID_W PUTX [0 ] 0 -ID_W PUTX_NotOwner [0 ] 0 -ID_W DMA_READ [0 ] 0 -ID_W DMA_WRITE [0 ] 0 -ID_W Memory_Ack [0 ] 0 - diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index db0163c4d..da9d2213e 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,16 +4,31 @@ sim_seconds 0.000122 # Nu sim_ticks 121759 # Number of ticks simulated final_tick 121759 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 32232 # Simulator instruction rate (inst/s) -host_op_rate 58383 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 729156 # Simulator tick rate (ticks/s) -host_mem_usage 170120 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 37945 # Simulator instruction rate (inst/s) +host_op_rate 68729 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 858310 # Simulator tick rate (ticks/s) +host_mem_usage 162016 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses +system.ruby.dir_cntrl0.memBuffer.memReq 2750 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 1377 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 1373 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 846 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 1965 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memBankQ 3 # Delay behind the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 1968 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.715636 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 823 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 1044 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 33 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 65 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 160 5.82% 5.82% | 144 5.24% 11.05% | 210 7.64% 18.69% | 146 5.31% 24.00% | 196 7.13% 31.13% | 96 3.49% 34.62% | 66 2.40% 37.02% | 38 1.38% 38.40% | 22 0.80% 39.20% | 20 0.73% 39.93% | 184 6.69% 46.62% | 297 10.80% 57.42% | 71 2.58% 60.00% | 124 4.51% 64.51% | 60 2.18% 66.69% | 18 0.65% 67.35% | 84 3.05% 70.40% | 6 0.22% 70.62% | 8 0.29% 70.91% | 14 0.51% 71.42% | 92 3.35% 74.76% | 56 2.04% 76.80% | 14 0.51% 77.31% | 60 2.18% 79.49% | 34 1.24% 80.73% | 58 2.11% 82.84% | 84 3.05% 85.89% | 66 2.40% 88.29% | 42 1.53% 89.82% | 122 4.44% 94.25% | 104 3.78% 98.04% | 54 1.96% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 2750 # Number of accesses per bank + system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 121759 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -37,5 +52,29 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 121759 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles +system.ruby.l1_cntrl0.Load 1045 0.00% 0.00% +system.ruby.l1_cntrl0.Ifetch 6864 0.00% 0.00% +system.ruby.l1_cntrl0.Store 943 0.00% 0.00% +system.ruby.l1_cntrl0.Data 1377 0.00% 0.00% +system.ruby.l1_cntrl0.Replacement 1373 0.00% 0.00% +system.ruby.l1_cntrl0.Writeback_Ack 1373 0.00% 0.00% +system.ruby.l1_cntrl0.I.Load 499 0.00% 0.00% +system.ruby.l1_cntrl0.I.Ifetch 623 0.00% 0.00% +system.ruby.l1_cntrl0.I.Store 255 0.00% 0.00% +system.ruby.l1_cntrl0.M.Load 546 0.00% 0.00% +system.ruby.l1_cntrl0.M.Ifetch 6241 0.00% 0.00% +system.ruby.l1_cntrl0.M.Store 688 0.00% 0.00% +system.ruby.l1_cntrl0.M.Replacement 1373 0.00% 0.00% +system.ruby.l1_cntrl0.MI.Writeback_Ack 1373 0.00% 0.00% +system.ruby.l1_cntrl0.IS.Data 1122 0.00% 0.00% +system.ruby.l1_cntrl0.IM.Data 255 0.00% 0.00% +system.ruby.dir_cntrl0.GETX 1377 0.00% 0.00% +system.ruby.dir_cntrl0.PUTX 1373 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 1377 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 1373 0.00% 0.00% +system.ruby.dir_cntrl0.I.GETX 1377 0.00% 0.00% +system.ruby.dir_cntrl0.M.PUTX 1373 0.00% 0.00% +system.ruby.dir_cntrl0.IM.Memory_Data 1377 0.00% 0.00% +system.ruby.dir_cntrl0.MI.Memory_Ack 1373 0.00% 0.00% ---------- End Simulation Statistics ---------- |