diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-09-25 07:27:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-09-25 07:27:03 -0400 |
| commit | 806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6 (patch) | |
| tree | bf8944a02c194cb657534276190f2a17859b3675 /tests/quick/se/00.hello/ref | |
| parent | a9a7002a3b3ad1e423d16ace826e80574d4ddc4f (diff) | |
| download | gem5-806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6.tar.xz | |
stats: Update stats to reflect snoop-filter changes
Diffstat (limited to 'tests/quick/se/00.hello/ref')
16 files changed, 1462 insertions, 1366 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index 1a6e00d22..e3deed2b6 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000038 # Number of seconds simulated -sim_ticks 37552000 # Number of ticks simulated -final_tick 37552000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 37553000 # Number of ticks simulated +final_tick 37553000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72134 # Simulator instruction rate (inst/s) -host_op_rate 72118 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 423067865 # Simulator tick rate (ticks/s) -host_mem_usage 288748 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 161315 # Simulator instruction rate (inst/s) +host_op_rate 161262 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 945919395 # Simulator tick rate (ticks/s) +host_mem_usage 296228 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 6400 # Number of instructions simulated sim_ops 6400 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 23296 # Nu system.physmem.num_reads::cpu.inst 364 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory system.physmem.num_reads::total 533 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 620366425 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 288027269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 908393694 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 620366425 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 620366425 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 620366425 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 288027269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 908393694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 620349905 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 288019599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 908369504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 620349905 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 620349905 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 620349905 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 288019599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 908369504 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 533 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 37447500 # Total gap between requests +system.physmem.totGap 37448500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -206,9 +206,9 @@ system.physmem.totBusLat 2665000 # To system.physmem.avgQLat 6205.91 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 24955.91 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 908.39 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBW 908.37 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 908.39 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 908.37 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 7.10 # Data bus utilization in percentage @@ -220,7 +220,7 @@ system.physmem.readRowHits 437 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 70257.97 # Average gap between requests +system.physmem.avgGap 70259.85 # Average gap between requests system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 226800 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 123750 # Energy for precharge commands per rank (pJ) @@ -293,24 +293,24 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 75104 # number of cpu cycles simulated +system.cpu.numCycles 75106 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6400 # Number of instructions committed system.cpu.committedOps 6400 # Number of ops (including micro ops) committed system.cpu.discardedOps 1085 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 11.735000 # CPI: cycles per instruction -system.cpu.ipc 0.085215 # IPC: instructions per cycle +system.cpu.cpi 11.735312 # CPI: cycles per instruction +system.cpu.ipc 0.085213 # IPC: instructions per cycle system.cpu.tickCycles 12517 # Number of cycles that the object actually ticked -system.cpu.idleCycles 62587 # Total number of cycles that the object has spent stopped +system.cpu.idleCycles 62589 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.919220 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.920661 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1972 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.668639 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.919220 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 103.920661 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.025371 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.025371 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id @@ -417,14 +417,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78047.337278 system.cpu.dcache.overall_avg_mshr_miss_latency::total 78047.337278 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 175.811080 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 175.815240 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2286 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 6.263014 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 175.811080 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.085845 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.085845 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 175.815240 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.085847 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.085847 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id @@ -443,12 +443,12 @@ system.cpu.icache.demand_misses::cpu.inst 365 # n system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 27931500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 27931500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 27931500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 27931500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 27931500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 27931500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 27932500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 27932500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 27932500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 27932500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 27932500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 27932500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2651 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2651 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2651 # number of demand (read+write) accesses @@ -461,12 +461,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.137684 system.cpu.icache.demand_miss_rate::total 0.137684 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.137684 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.137684 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76524.657534 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76524.657534 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76524.657534 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76524.657534 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76524.657534 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76524.657534 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76527.397260 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76527.397260 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76527.397260 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76527.397260 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76527.397260 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76527.397260 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,33 +481,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365 system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27566500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27566500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27566500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27566500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27566500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27566500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27567500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27567500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27567500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27567500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27567500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27567500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.137684 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.137684 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.137684 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75524.657534 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75524.657534 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75524.657534 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75524.657534 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75524.657534 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75524.657534 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75527.397260 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75527.397260 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75527.397260 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75527.397260 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75527.397260 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75527.397260 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 233.447652 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 233.452540 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.824515 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.623137 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.828674 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.623866 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005366 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001759 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.007124 # Average percentage of cache occupancy @@ -640,6 +640,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64197.802198 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66532.544379 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64938.086304 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 534 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution @@ -653,14 +659,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 534 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001873 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.043274 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 534 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 533 99.81% 99.81% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.19% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 85a8b430a..58b2620bf 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 21900500 # Number of ticks simulated final_tick 21900500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 43231 # Simulator instruction rate (inst/s) -host_op_rate 43225 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 148545474 # Simulator tick rate (ticks/s) -host_mem_usage 289772 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 94413 # Simulator instruction rate (inst/s) +host_op_rate 94393 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 324370159 # Simulator tick rate (ticks/s) +host_mem_usage 297000 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -698,12 +698,12 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81932.748538 system.cpu.dcache.overall_avg_mshr_miss_latency::total 81932.748538 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 157.774053 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 157.774008 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1627 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 311 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 5.231511 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 157.774053 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 157.774008 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.077038 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.077038 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id @@ -724,12 +724,12 @@ system.cpu.icache.demand_misses::cpu.inst 459 # n system.cpu.icache.demand_misses::total 459 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 459 # number of overall misses system.cpu.icache.overall_misses::total 459 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32352500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32352500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32352500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32352500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32352500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32352500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32353500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32353500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32353500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32353500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32353500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32353500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2086 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2086 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2086 # number of demand (read+write) accesses @@ -742,12 +742,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.220038 system.cpu.icache.demand_miss_rate::total 0.220038 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.220038 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.220038 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70484.749455 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70484.749455 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70484.749455 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70484.749455 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70484.749455 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70484.749455 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70486.928105 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70486.928105 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70486.928105 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70486.928105 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70486.928105 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70486.928105 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -768,24 +768,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 311 system.cpu.icache.demand_mshr_misses::total 311 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 311 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 311 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23859500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23859500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23859500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23859500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23859500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23859500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23860500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23860500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23860500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23860500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23860500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23860500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149089 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.149089 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.149089 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76718.649518 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76718.649518 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76718.649518 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 76718.649518 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76718.649518 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 76718.649518 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76721.864952 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76721.864952 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76721.864952 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76721.864952 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76721.864952 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76721.864952 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 218.211579 # Cycle average of tags in use @@ -927,6 +927,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65419.354839 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70371.345029 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67179.833680 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 482 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution @@ -940,14 +946,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 482 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002075 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.045549 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 482 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 481 99.79% 99.79% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 482 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index 2c1174c59..e7401ee31 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000033 # Number of seconds simulated -sim_ticks 32544500 # Number of ticks simulated -final_tick 32544500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 32545500 # Number of ticks simulated +final_tick 32545500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 619666 # Simulator instruction rate (inst/s) -host_op_rate 618826 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3148046044 # Simulator tick rate (ticks/s) -host_mem_usage 291528 # Number of bytes of host memory used +host_inst_rate 507828 # Simulator instruction rate (inst/s) +host_op_rate 507304 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2581337246 # Simulator tick rate (ticks/s) +host_mem_usage 294696 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 546697599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 330378405 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 877076004 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 546697599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 546697599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 546697599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 330378405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 877076004 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 546680801 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 330368254 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 877049054 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 546680801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 546680801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 546680801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 330368254 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 877049054 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -63,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 65089 # number of cpu cycles simulated +system.cpu.numCycles 65091 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6390 # Number of instructions committed @@ -82,7 +82,7 @@ system.cpu.num_mem_refs 2058 # nu system.cpu.num_load_insts 1190 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 65089 # Number of busy cycles +system.cpu.num_busy_cycles 65091 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched @@ -122,12 +122,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6400 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.755352 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.756988 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.755352 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 103.756988 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.025331 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.025331 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id @@ -226,14 +226,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 127.988451 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 127.992231 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 127.988451 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.062494 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.062494 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 127.992231 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.062496 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.062496 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id @@ -252,12 +252,12 @@ system.cpu.icache.demand_misses::cpu.inst 279 # n system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses system.cpu.icache.overall_misses::total 279 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15303500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15303500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15303500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15303500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15303500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15304500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15304500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15304500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15304500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15304500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15304500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses @@ -270,12 +270,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54851.254480 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54851.254480 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54851.254480 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54851.254480 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54854.838710 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54854.838710 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54854.838710 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54854.838710 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54854.838710 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54854.838710 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -290,36 +290,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 279 system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15024500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15024500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15024500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15024500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15024500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15024500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15025500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15025500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15025500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15025500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15025500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15025500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53851.254480 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53851.254480 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53851.254480 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53851.254480 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53851.254480 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53851.254480 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53854.838710 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53854.838710 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53854.838710 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53854.838710 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53854.838710 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53854.838710 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 184.465722 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 184.470347 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.994443 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.471279 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.998222 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.472125 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003906 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001723 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005629 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id @@ -449,6 +449,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.121076 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 447 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution @@ -462,14 +468,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 447 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002237 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.047298 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 447 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 446 99.78% 99.78% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.22% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 447 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index 2f7c0906a..a420f2b35 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 20075000 # Number of ticks simulated final_tick 20075000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42420 # Simulator instruction rate (inst/s) -host_op_rate 42407 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 329231154 # Simulator tick rate (ticks/s) -host_mem_usage 287436 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 131673 # Simulator instruction rate (inst/s) +host_op_rate 131586 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1021264689 # Simulator tick rate (ticks/s) +host_mem_usage 295944 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -634,6 +634,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63641.255605 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64482.352941 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63873.376623 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 308 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution @@ -647,15 +653,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 308 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 308 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 308 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 308 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 154000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 6ee889334..c4983f8bd 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu sim_ticks 12363500 # Number of ticks simulated final_tick 12363500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 20992 # Simulator instruction rate (inst/s) -host_op_rate 20989 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 108692792 # Simulator tick rate (ticks/s) -host_mem_usage 288464 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 79745 # Simulator instruction rate (inst/s) +host_op_rate 79707 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 412680664 # Simulator tick rate (ticks/s) +host_mem_usage 295680 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -919,6 +919,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64320.855615 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66847.058824 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65110.294118 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution @@ -932,15 +938,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 272 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 272 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 7411927e4..6bacfac4e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000017 # Nu sim_ticks 16524500 # Number of ticks simulated final_tick 16524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 374183 # Simulator instruction rate (inst/s) -host_op_rate 373424 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2390351512 # Simulator tick rate (ticks/s) -host_mem_usage 291260 # Number of bytes of host memory used +host_inst_rate 315037 # Simulator instruction rate (inst/s) +host_op_rate 314537 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2013954906 # Simulator tick rate (ticks/s) +host_mem_usage 293376 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated @@ -443,6 +443,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.067485 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42502.040816 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 245 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution @@ -456,15 +462,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 245 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 245 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 245 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 122500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 3e86bd3ac..ffa31a0bc 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 29941500 # Number of ticks simulated -final_tick 29941500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 29949500 # Number of ticks simulated +final_tick 29949500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 58660 # Simulator instruction rate (inst/s) -host_op_rate 68656 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 381226078 # Simulator tick rate (ticks/s) -host_mem_usage 304332 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 110305 # Simulator instruction rate (inst/s) +host_op_rate 129095 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 716958322 # Simulator tick rate (ticks/s) +host_mem_usage 313816 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 4605 # Number of instructions simulated sim_ops 5391 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory system.physmem.num_reads::total 421 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 651937946 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 247950169 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 899888115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 651937946 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 651937946 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 651937946 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 247950169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 899888115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 651763802 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 247883938 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 899647740 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 651763802 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 651763802 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 651763802 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 247883938 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 899647740 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 421 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 29851000 # Total gap between requests +system.physmem.totGap 29858000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -200,15 +200,15 @@ system.physmem.bytesPerActivate::768-895 3 4.84% 83.87% # By system.physmem.bytesPerActivate::896-1023 1 1.61% 85.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation -system.physmem.totQLat 2218000 # Total ticks spent queuing -system.physmem.totMemAccLat 10111750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 2201000 # Total ticks spent queuing +system.physmem.totMemAccLat 10094750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5268.41 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5228.03 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24018.41 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 899.89 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23978.03 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 899.65 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 899.89 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 899.65 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 7.03 # Data bus utilization in percentage @@ -220,7 +220,7 @@ system.physmem.readRowHits 350 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 70904.99 # Average gap between requests +system.physmem.avgGap 70921.62 # Average gap between requests system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) @@ -377,24 +377,24 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 59883 # number of cpu cycles simulated +system.cpu.numCycles 59899 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4605 # Number of instructions committed system.cpu.committedOps 5391 # Number of ops (including micro ops) committed system.cpu.discardedOps 1120 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 13.003909 # CPI: cycles per instruction -system.cpu.ipc 0.076900 # IPC: instructions per cycle +system.cpu.cpi 13.007383 # CPI: cycles per instruction +system.cpu.ipc 0.076879 # IPC: instructions per cycle system.cpu.tickCycles 10593 # Number of cycles that the object actually ticked -system.cpu.idleCycles 49290 # Total number of cycles that the object has spent stopped +system.cpu.idleCycles 49306 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.506122 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 86.506555 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.116438 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.506122 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 86.506555 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.021120 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.021120 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id @@ -423,14 +423,14 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6956500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6956500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6982500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6982500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 5019500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 5019500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 11976000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 11976000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 11976000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 11976000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12002000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12002000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12002000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12002000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1162 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1162 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -451,14 +451,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.087711 system.cpu.dcache.demand_miss_rate::total 0.087711 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.087711 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.087711 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60491.304348 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60491.304348 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60717.391304 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60717.391304 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74917.910448 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 74917.910448 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65802.197802 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65802.197802 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65802.197802 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65802.197802 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65945.054945 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65945.054945 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65945.054945 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -483,14 +483,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6353500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6353500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6375500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6375500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3198000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3198000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9551500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9551500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9551500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9551500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9573500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9573500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9573500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9573500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088640 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088640 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses @@ -499,24 +499,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070361 system.cpu.dcache.demand_mshr_miss_rate::total 0.070361 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070361 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.070361 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61684.466019 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61684.466019 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61898.058252 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61898.058252 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74372.093023 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74372.093023 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65421.232877 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65421.232877 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65421.232877 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65421.232877 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65571.917808 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 65571.917808 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 161.800750 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 161.807665 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1920 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 5.962733 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 161.800750 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.079004 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.079004 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 161.807665 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.079008 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.079008 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id @@ -535,12 +535,12 @@ system.cpu.icache.demand_misses::cpu.inst 322 # n system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses system.cpu.icache.overall_misses::total 322 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23597500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23597500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23597500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23597500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23597500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23597500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23598000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23598000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23598000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23598000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23598000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23598000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2242 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2242 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2242 # number of demand (read+write) accesses @@ -553,12 +553,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.143622 system.cpu.icache.demand_miss_rate::total 0.143622 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.143622 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.143622 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73284.161491 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 73284.161491 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 73284.161491 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 73284.161491 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 73284.161491 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73284.161491 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73285.714286 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73285.714286 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 73285.714286 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73285.714286 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 73285.714286 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73285.714286 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -573,34 +573,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 322 system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23275500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23275500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23275500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23275500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23275500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23275500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23276000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23276000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23276000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23276000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23276000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23276000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143622 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.143622 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.143622 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72284.161491 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72284.161491 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72284.161491 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72284.161491 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72284.161491 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72284.161491 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72285.714286 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72285.714286 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72285.714286 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72285.714286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72285.714286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72285.714286 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 195.452372 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 195.460131 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 41 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.108466 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.314702 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 41.137670 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004709 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.322264 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 41.137866 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004710 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005965 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id @@ -633,16 +633,16 @@ system.cpu.l2cache.overall_misses::cpu.data 124 # system.cpu.l2cache.overall_misses::total 429 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3133500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3133500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22614000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 22614000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22597500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 22597500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5961000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 5961000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22614000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22597500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 9094500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31708500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22614000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 31692000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22597500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 9094500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31708500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31692000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses) @@ -669,16 +669,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72872.093023 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72872.093023 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74144.262295 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74144.262295 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74090.163934 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74090.163934 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73592.592593 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73592.592593 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74144.262295 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74090.163934 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73912.587413 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74144.262295 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73874.125874 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74090.163934 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73912.587413 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73874.125874 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -707,16 +707,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 116 system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2703500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2703500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19564000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19564000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19547500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19547500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4701000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4701000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19564000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19547500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7404500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26968500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19564000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26952000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19547500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7404500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26968500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26952000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses @@ -731,17 +731,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62872.093023 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62872.093023 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64144.262295 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64144.262295 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64090.163934 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64090.163934 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64397.260274 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64397.260274 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64144.262295 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64058.194774 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64144.262295 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64090.163934 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64058.194774 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64019.002375 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 471 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 49 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -756,14 +762,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 471 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.101911 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.302853 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 471 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 423 89.81% 89.81% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 48 10.19% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 471 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 235500 # Layer occupancy (ticks) @@ -791,7 +797,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 421 # Request fanout histogram -system.membus.reqLayer0.occupancy 491000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 491500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) system.membus.respLayer1.occupancy 2236500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 7.5 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index be50d79db..0d7cf1bb4 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17163000 # Number of ticks simulated -final_tick 17163000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 17170000 # Number of ticks simulated +final_tick 17170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25428 # Simulator instruction rate (inst/s) -host_op_rate 29777 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 95019968 # Simulator tick rate (ticks/s) -host_mem_usage 305352 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 50361 # Simulator instruction rate (inst/s) +host_op_rate 58973 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 188251031 # Simulator tick rate (ticks/s) +host_mem_usage 313812 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17600 # Nu system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory system.physmem.num_reads::total 396 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1025461749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 451203170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1476664919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1025461749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1025461749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1025461749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 451203170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1476664919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1025043681 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 451019220 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1476062900 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1025043681 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1025043681 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1025043681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 451019220 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1476062900 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 396 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 17090000 # Total gap between requests +system.physmem.totGap 17097000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -200,19 +200,19 @@ system.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # By system.physmem.bytesPerActivate::896-1023 2 3.17% 85.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 3055250 # Total ticks spent queuing -system.physmem.totMemAccLat 10480250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3045250 # Total ticks spent queuing +system.physmem.totMemAccLat 10470250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7715.28 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7690.03 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26465.28 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1476.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26440.03 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1476.06 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1476.66 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1476.06 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.54 # Data bus utilization in percentage -system.physmem.busUtilRead 11.54 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.53 # Data bus utilization in percentage +system.physmem.busUtilRead 11.53 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,21 +220,21 @@ system.physmem.readRowHits 330 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.33 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43156.57 # Average gap between requests +system.physmem.avgGap 43174.24 # Average gap between requests system.physmem.pageHitRate 83.33 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2106000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10794375 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 10798650 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14428830 # Total energy per rank (pJ) -system.physmem_0.averagePower 911.198611 # Core power per rank (mW) +system.physmem_0.totalEnergy 14433105 # Total energy per rank (pJ) +system.physmem_0.averagePower 911.108972 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 65750 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16176750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16183750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) @@ -245,18 +245,18 @@ system.physmem_1.actBackEnergy 10407915 # En system.physmem_1.preBackEnergy 369750 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 12777285 # Total energy per rank (pJ) system.physmem_1.averagePower 807.028896 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 665250 # Time in different power states +system.physmem_1.memoryStateTime::IDLE 672250 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 14752750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2533 # Number of BP lookups -system.cpu.branchPred.condPredicted 1576 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 452 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2102 # Number of BTB lookups -system.cpu.branchPred.BTBHits 812 # Number of BTB hits +system.cpu.branchPred.lookups 2537 # Number of BP lookups +system.cpu.branchPred.condPredicted 1577 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 453 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2106 # Number of BTB lookups +system.cpu.branchPred.BTBHits 814 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 38.629876 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 38.651472 # BTB Hit Percentage system.cpu.branchPred.usedRAS 321 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -496,95 +496,95 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 34327 # number of cpu cycles simulated +system.cpu.numCycles 34341 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7647 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11725 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2533 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1133 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4667 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 953 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 7661 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11733 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2537 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1135 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4671 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 955 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1968 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 290 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13059 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.059729 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.422792 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1971 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 292 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13078 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.059336 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.422082 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10498 80.39% 80.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 262 2.01% 82.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 215 1.65% 84.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 219 1.68% 85.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 263 2.01% 87.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 312 2.39% 90.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 142 1.09% 91.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 158 1.21% 92.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 990 7.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10515 80.40% 80.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 260 1.99% 82.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 215 1.64% 84.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 219 1.67% 85.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 267 2.04% 87.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 312 2.39% 90.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 142 1.09% 91.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 157 1.20% 92.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 991 7.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13059 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.073790 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.341568 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6338 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4216 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 13078 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.073877 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.341662 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6351 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4223 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2063 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 121 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 321 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 380 # Number of times decode resolved a branch +system.cpu.decode.UnblockCycles 119 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 322 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11316 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 11299 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 321 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6551 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 647 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2328 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1964 # Number of cycles rename is running +system.cpu.rename.SquashCycles 322 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6564 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 644 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2338 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1962 # Number of cycles rename is running system.cpu.rename.UnblockCycles 1248 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 10673 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 10655 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 168 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 130 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 1076 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 10857 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 48954 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 11788 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 10847 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 48852 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 11762 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 74 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5363 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 5353 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 42 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 428 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2126 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1537 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2118 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1531 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9711 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9695 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7972 # Number of instructions issued +system.cpu.iq.iqInstsIssued 7975 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4379 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 10941 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 4363 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 10837 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13059 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.610460 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.342240 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13078 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.609803 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.341106 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9876 75.63% 75.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1174 8.99% 84.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 762 5.84% 90.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 454 3.48% 93.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 326 2.50% 96.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 278 2.13% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 116 0.89% 99.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9890 75.62% 75.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1180 9.02% 84.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 762 5.83% 90.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 451 3.45% 93.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 329 2.52% 96.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 278 2.13% 98.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 115 0.88% 99.44% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 62 0.47% 99.92% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13059 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13078 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 9 5.92% 5.92% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 5.92% # attempts to use FU when none available @@ -620,69 +620,69 @@ system.cpu.iq.fu_full::MemWrite 76 50.00% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4885 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.09% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1831 22.97% 84.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1246 15.63% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4886 61.27% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.09% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1833 22.98% 84.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1246 15.62% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7972 # Type of FU issued -system.cpu.iq.rate 0.232237 # Inst issue rate +system.cpu.iq.FU_type_0::total 7975 # Type of FU issued +system.cpu.iq.rate 0.232230 # Inst issue rate system.cpu.iq.fu_busy_cnt 152 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019067 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29107 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14039 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7309 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.019060 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29132 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14007 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7313 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 93 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 116 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8081 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8084 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1099 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1091 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 599 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 593 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 34 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 321 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 613 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 322 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 611 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 9766 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 9750 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 119 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2126 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1537 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2118 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1531 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall @@ -690,43 +690,43 @@ system.cpu.iew.memOrderViolationEvents 19 # Nu system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 215 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 327 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7697 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 7701 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 1736 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 275 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 274 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 9 # number of nop insts executed -system.cpu.iew.exec_refs 2930 # number of memory reference insts executed -system.cpu.iew.exec_branches 1433 # Number of branches executed -system.cpu.iew.exec_stores 1194 # Number of stores executed -system.cpu.iew.exec_rate 0.224226 # Inst execution rate -system.cpu.iew.wb_sent 7432 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7341 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3456 # num instructions producing a value -system.cpu.iew.wb_consumers 6757 # num instructions consuming a value +system.cpu.iew.exec_refs 2933 # number of memory reference insts executed +system.cpu.iew.exec_branches 1435 # Number of branches executed +system.cpu.iew.exec_stores 1197 # Number of stores executed +system.cpu.iew.exec_rate 0.224251 # Inst execution rate +system.cpu.iew.wb_sent 7436 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7345 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3459 # num instructions producing a value +system.cpu.iew.wb_consumers 6763 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.213855 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.511470 # average fanout of values written-back +system.cpu.iew.wb_rate 0.213884 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.511459 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4387 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4371 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 297 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12286 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.437734 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.284067 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 298 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12306 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.437023 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.282384 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10235 83.31% 83.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 882 7.18% 90.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 420 3.42% 93.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 222 1.81% 95.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 111 0.90% 96.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 213 1.73% 98.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 51 0.42% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.33% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10254 83.33% 83.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 882 7.17% 90.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 420 3.41% 93.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 223 1.81% 95.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 112 0.91% 96.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 213 1.73% 98.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 51 0.41% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 40 0.33% 99.10% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 111 0.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12286 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12306 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -773,32 +773,32 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 111 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 21783 # The number of ROB reads -system.cpu.rob.rob_writes 20313 # The number of ROB writes -system.cpu.timesIdled 192 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21268 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21787 # The number of ROB reads +system.cpu.rob.rob_writes 20281 # The number of ROB writes +system.cpu.timesIdled 193 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 21263 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.475392 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.475392 # CPI: Total CPI of All Threads -system.cpu.ipc 0.133772 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.133772 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7631 # number of integer regfile reads +system.cpu.cpi 7.478441 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.478441 # CPI: Total CPI of All Threads +system.cpu.ipc 0.133718 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.133718 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 7636 # number of integer regfile reads system.cpu.int_regfile_writes 4176 # number of integer regfile writes system.cpu.fp_regfile_reads 32 # number of floating regfile reads -system.cpu.cc_regfile_reads 27375 # number of cc regfile reads -system.cpu.cc_regfile_writes 3204 # number of cc regfile writes -system.cpu.misc_regfile_reads 3054 # number of misc regfile reads +system.cpu.cc_regfile_reads 27387 # number of cc regfile reads +system.cpu.cc_regfile_writes 3201 # number of cc regfile writes +system.cpu.misc_regfile_reads 3057 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.851603 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 87.846363 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2054 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.972789 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.851603 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021448 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021448 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 87.846363 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021447 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021447 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id @@ -827,16 +827,16 @@ system.cpu.dcache.demand_misses::cpu.data 498 # n system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses system.cpu.dcache.overall_misses::total 498 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10572000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10572000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22577500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22577500 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10593000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10593000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22578500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22578500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 142000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33149500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33149500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33149500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33149500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33171500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33171500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33171500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33171500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1617 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1617 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -859,16 +859,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.196838 system.cpu.dcache.demand_miss_rate::total 0.196838 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.196838 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.196838 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58408.839779 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58408.839779 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71222.397476 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 71222.397476 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58524.861878 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58524.861878 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71225.552050 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 71225.552050 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66565.261044 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66565.261044 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66565.261044 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66565.261044 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66609.437751 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66609.437751 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66609.437751 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66609.437751 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -895,14 +895,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6969000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6969000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3397000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3397000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10366000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10366000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10366000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10366000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6985000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6985000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3398000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3398000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10383000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10383000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10383000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10383000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.064935 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.064935 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses @@ -911,66 +911,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058103 system.cpu.dcache.demand_mshr_miss_rate::total 0.058103 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058103 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.058103 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66371.428571 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66371.428571 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80880.952381 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80880.952381 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70517.006803 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70517.006803 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70517.006803 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70517.006803 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66523.809524 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66523.809524 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80904.761905 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80904.761905 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70632.653061 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70632.653061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70632.653061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70632.653061 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 149.741808 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1582 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 149.742670 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1585 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 293 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.399317 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.409556 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 149.741808 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073116 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073116 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 149.742670 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073117 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073117 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4229 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4229 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1582 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1582 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1582 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1582 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1582 # number of overall hits -system.cpu.icache.overall_hits::total 1582 # number of overall hits +system.cpu.icache.tags.tag_accesses 4235 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4235 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1585 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1585 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1585 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1585 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1585 # number of overall hits +system.cpu.icache.overall_hits::total 1585 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 386 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 386 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 386 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 386 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 386 # number of overall misses system.cpu.icache.overall_misses::total 386 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26869500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26869500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26869500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26869500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26869500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26869500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1968 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1968 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1968 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1968 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1968 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1968 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196138 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.196138 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.196138 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.196138 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.196138 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.196138 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69610.103627 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69610.103627 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69610.103627 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69610.103627 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69610.103627 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69610.103627 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26879500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26879500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26879500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26879500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26879500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26879500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1971 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1971 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1971 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1971 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1971 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195840 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.195840 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.195840 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.195840 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.195840 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.195840 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69636.010363 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69636.010363 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69636.010363 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69636.010363 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69636.010363 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69636.010363 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 432 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -991,33 +991,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 293 system.cpu.icache.demand_mshr_misses::total 293 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 293 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21385500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21385500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21385500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21385500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21385500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21385500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148882 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148882 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148882 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.148882 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148882 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.148882 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72988.054608 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72988.054608 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72988.054608 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72988.054608 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72988.054608 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72988.054608 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21398500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21398500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21398500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21398500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21398500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21398500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148656 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148656 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148656 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148656 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148656 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148656 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73032.423208 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73032.423208 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73032.423208 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73032.423208 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73032.423208 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73032.423208 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 187.228350 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 187.228140 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 354 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.110169 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.551776 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.676574 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.553706 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 46.674434 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004289 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001424 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005714 # Average percentage of cache occupancy @@ -1051,16 +1051,16 @@ system.cpu.l2cache.overall_misses::cpu.data 126 # system.cpu.l2cache.overall_misses::total 401 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3333000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3333000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 20756000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 20756000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6584500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6584500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20756000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9917500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30673500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20756000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9917500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30673500 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 20751000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 20751000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6579500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6579500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20751000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9912500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30663500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20751000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9912500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30663500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 293 # number of ReadCleanReq accesses(hits+misses) @@ -1087,16 +1087,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.857143 system.cpu.l2cache.overall_miss_rate::total 0.911364 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79357.142857 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79357.142857 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75476.363636 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75476.363636 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78386.904762 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78386.904762 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75476.363636 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78710.317460 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76492.518703 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75476.363636 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78710.317460 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76492.518703 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75458.181818 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75458.181818 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78327.380952 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78327.380952 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75458.181818 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78670.634921 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76467.581047 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75458.181818 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78670.634921 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76467.581047 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1125,16 +1125,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 121 system.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2913000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2913000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18006000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18006000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5464000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5464000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18006000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8377000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26383000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18006000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8377000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26383000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18001000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18001000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5459000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5459000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18001000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8372000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26373000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18001000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8372000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26373000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for ReadCleanReq accesses @@ -1149,17 +1149,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69357.142857 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69357.142857 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65476.363636 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65476.363636 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69164.556962 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69164.556962 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65476.363636 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69231.404959 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66623.737374 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65476.363636 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69231.404959 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66623.737374 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65458.181818 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65458.181818 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69101.265823 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69101.265823 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65458.181818 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69190.082645 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66598.484848 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65458.181818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69190.082645 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66598.484848 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 441 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 44 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution @@ -1173,14 +1179,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.102041 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.303046 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 441 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 396 89.80% 89.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 45 10.20% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index c7177147a..8015f8322 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 17777000 # Number of ticks simulated -final_tick 17777000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 17778000 # Number of ticks simulated +final_tick 17778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 63242 # Simulator instruction rate (inst/s) -host_op_rate 74054 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 244740900 # Simulator tick rate (ticks/s) -host_mem_usage 307828 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 58925 # Simulator instruction rate (inst/s) +host_op_rate 69000 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 228057572 # Simulator tick rate (ticks/s) +host_mem_usage 310616 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.inst 271 # Nu system.physmem.num_reads::cpu.data 108 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory system.physmem.num_reads::total 406 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 975642684 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 388817011 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 97204253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1461663948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 975642684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 975642684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 975642684 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 388817011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 97204253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1461663948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 975587805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 388795140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 97198785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1461581730 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 975587805 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 975587805 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 975587805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 388795140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 97198785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1461581730 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 407 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 407 # Number of DRAM read bursts, including those serviced by the write queue @@ -79,7 +79,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 17763500 # Total gap between requests +system.physmem.totGap 17764500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -204,15 +204,15 @@ system.physmem.bytesPerActivate::768-895 3 5.08% 79.66% # By system.physmem.bytesPerActivate::896-1023 2 3.39% 83.05% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 16.95% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation -system.physmem.totQLat 3130500 # Total ticks spent queuing -system.physmem.totMemAccLat 10761750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3121500 # Total ticks spent queuing +system.physmem.totMemAccLat 10752750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2035000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7691.65 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7669.53 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26441.65 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1465.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26419.53 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1465.18 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1465.26 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1465.18 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 11.45 # Data bus utilization in percentage @@ -224,35 +224,35 @@ system.physmem.readRowHits 340 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43644.96 # Average gap between requests +system.physmem.avgGap 43647.42 # Average gap between requests system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10766160 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 10769580 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 63750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14346345 # Total energy per rank (pJ) -system.physmem_0.averagePower 905.346375 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 321250 # Time in different power states +system.physmem_0.totalEnergy 14349765 # Total energy per rank (pJ) +system.physmem_0.averagePower 905.276555 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 315250 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15288250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15294250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10149705 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 596250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12757320 # Total energy per rank (pJ) -system.physmem_1.averagePower 805.767883 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 952000 # Time in different power states +system.physmem_1.actBackEnergy 10147140 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 598500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12757005 # Total energy per rank (pJ) +system.physmem_1.averagePower 805.747987 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 956000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14374250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14370250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 2336 # Number of BP lookups system.cpu.branchPred.condPredicted 1386 # Number of conditional branches predicted @@ -381,84 +381,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 35555 # number of cpu cycles simulated +system.cpu.numCycles 35557 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6171 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11259 # Number of instructions fetch has processed +system.cpu.fetch.icacheStallCycles 6181 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11260 # Number of instructions fetch has processed system.cpu.fetch.Branches 2336 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 731 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 7640 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 7643 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1059 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 155 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 303 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 318 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3825 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 176 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15116 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.870204 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.208015 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 322 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 3826 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 175 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15133 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.869491 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.207772 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8919 59.00% 59.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2458 16.26% 75.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 521 3.45% 78.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3218 21.29% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8934 59.04% 59.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2459 16.25% 75.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 521 3.44% 78.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3219 21.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15116 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.065701 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.316664 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5920 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3659 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5038 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 15133 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.065697 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.316675 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5932 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3662 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5040 # Number of cycles decode is running system.cpu.decode.UnblockCycles 131 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 368 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 329 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 9862 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1622 # Number of squashed instructions handled by decode +system.cpu.decode.BranchResolved 331 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 165 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 9865 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1623 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 368 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6989 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 961 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1965 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4094 # Number of cycles rename is running +system.cpu.rename.IdleCycles 7001 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 962 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1967 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4096 # Number of cycles rename is running system.cpu.rename.UnblockCycles 739 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 8883 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 411 # Number of squashed instructions processed by rename +system.cpu.rename.RenamedInsts 8887 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 410 # Number of squashed instructions processed by rename system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 665 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9235 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 40294 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9761 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 9238 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 40311 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9765 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3741 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3744 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 299 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1807 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 1809 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1277 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8348 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8352 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7146 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 184 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3009 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7843 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 7148 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 188 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3013 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7853 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15116 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.472744 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.858488 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15133 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.472345 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.858310 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10916 72.21% 72.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1949 12.89% 85.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1601 10.59% 95.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 605 4.00% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 45 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10931 72.23% 72.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1952 12.90% 85.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1600 10.57% 95.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 604 3.99% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 46 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -466,90 +466,90 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15116 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15133 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 412 28.93% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 465 32.65% 61.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 547 38.41% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 412 28.91% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 465 32.63% 61.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 548 38.46% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4468 62.52% 62.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.64% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1589 22.24% 84.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1081 15.13% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4470 62.53% 62.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.65% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.65% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1589 22.23% 84.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1081 15.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7146 # Type of FU issued -system.cpu.iq.rate 0.200984 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1424 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.199272 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30972 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11387 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6551 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 7148 # Type of FU issued +system.cpu.iq.rate 0.201029 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1425 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.199356 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30998 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11395 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 6553 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8542 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8545 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 780 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 782 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 339 # Number of stores squashed @@ -561,9 +561,9 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewSquashCycles 368 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 357 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 8401 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 8405 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1807 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 1809 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1277 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall @@ -572,7 +572,7 @@ system.cpu.iew.memOrderViolationEvents 7 # Nu system.cpu.iew.predictedTakenIncorrect 67 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 361 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6742 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 6744 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 1404 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed @@ -580,35 +580,35 @@ system.cpu.iew.exec_nop 14 # nu system.cpu.iew.exec_refs 2427 # number of memory reference insts executed system.cpu.iew.exec_branches 1272 # Number of branches executed system.cpu.iew.exec_stores 1023 # Number of stores executed -system.cpu.iew.exec_rate 0.189622 # Inst execution rate -system.cpu.iew.wb_sent 6609 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6567 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2975 # num instructions producing a value -system.cpu.iew.wb_consumers 5372 # num instructions consuming a value +system.cpu.iew.exec_rate 0.189667 # Inst execution rate +system.cpu.iew.wb_sent 6611 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6569 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2977 # num instructions producing a value +system.cpu.iew.wb_consumers 5378 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.184700 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.553797 # average fanout of values written-back +system.cpu.iew.wb_rate 0.184746 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.553552 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2568 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2574 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 347 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14574 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.369013 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.017093 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 14591 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.368583 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.017117 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11924 81.82% 81.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1388 9.52% 91.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 602 4.13% 95.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11942 81.84% 81.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1388 9.51% 91.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 601 4.12% 95.48% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 293 2.01% 97.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 168 1.15% 98.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 78 0.54% 99.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 45 0.31% 99.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 33 0.23% 99.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 43 0.30% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 167 1.14% 98.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 78 0.53% 99.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 46 0.32% 99.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 33 0.23% 99.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 43 0.29% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14574 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14591 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -655,32 +655,32 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22320 # The number of ROB reads -system.cpu.rob.rob_writes 16439 # The number of ROB writes -system.cpu.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20439 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22343 # The number of ROB reads +system.cpu.rob.rob_writes 16451 # The number of ROB writes +system.cpu.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20424 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.742814 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.742814 # CPI: Total CPI of All Threads -system.cpu.ipc 0.129152 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.129152 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6718 # number of integer regfile reads -system.cpu.int_regfile_writes 3745 # number of integer regfile writes +system.cpu.cpi 7.743249 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.743249 # CPI: Total CPI of All Threads +system.cpu.ipc 0.129145 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.129145 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 6720 # number of integer regfile reads +system.cpu.int_regfile_writes 3747 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 23959 # number of cc regfile reads +system.cpu.cc_regfile_reads 23965 # number of cc regfile reads system.cpu.cc_regfile_writes 2898 # number of cc regfile writes system.cpu.misc_regfile_reads 2607 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.292966 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 84.271040 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.485915 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.292966 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.164635 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.164635 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.271040 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.164592 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.164592 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id @@ -709,16 +709,16 @@ system.cpu.dcache.demand_misses::cpu.data 358 # n system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses system.cpu.dcache.overall_misses::total 358 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9199500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9199500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9210000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9210000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 7717500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 7717500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 125000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16917000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16917000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16917000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16917000 # number of overall miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 125500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16927500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16927500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16927500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16927500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1340 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1340 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -741,16 +741,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.158899 system.cpu.dcache.demand_miss_rate::total 0.158899 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.158899 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.158899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55086.826347 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55086.826347 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55149.700599 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55149.700599 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40405.759162 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 40405.759162 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47254.189944 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47254.189944 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47254.189944 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47254.189944 # average overall miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47283.519553 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47283.519553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47283.519553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47283.519553 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 829 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -777,14 +777,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 143 system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5829500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5829500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5839000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5839000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2454500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2454500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8284000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8284000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8284000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8284000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8293500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8293500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8293500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8293500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076119 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076119 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses @@ -793,71 +793,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063471 system.cpu.dcache.demand_mshr_miss_rate::total 0.063471 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063471 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.063471 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57151.960784 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57151.960784 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57245.098039 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57245.098039 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59865.853659 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59865.853659 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57930.069930 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57930.069930 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57930.069930 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57930.069930 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57996.503497 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57996.503497 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57996.503497 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57996.503497 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 42 # number of replacements -system.cpu.icache.tags.tagsinuse 136.256883 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3459 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 136.212207 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3460 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.725424 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.728814 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 136.256883 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.266127 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.266127 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 136.212207 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.266039 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.266039 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 253 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 7941 # Number of tag accesses -system.cpu.icache.tags.data_accesses 7941 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 3459 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3459 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3459 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3459 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3459 # number of overall hits -system.cpu.icache.overall_hits::total 3459 # number of overall hits +system.cpu.icache.tags.tag_accesses 7943 # Number of tag accesses +system.cpu.icache.tags.data_accesses 7943 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 3460 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3460 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3460 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3460 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3460 # number of overall hits +system.cpu.icache.overall_hits::total 3460 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21567493 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21567493 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21567493 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21567493 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21567493 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21567493 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3823 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3823 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3823 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3823 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.095213 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.095213 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.095213 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.095213 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.095213 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.095213 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59251.354396 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 59251.354396 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 59251.354396 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 59251.354396 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 59251.354396 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 59251.354396 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8431 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21574493 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21574493 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21574493 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21574493 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21574493 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21574493 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 3824 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 3824 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 3824 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 3824 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 3824 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 3824 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.095188 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.095188 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.095188 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.095188 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.095188 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.095188 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59270.585165 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 59270.585165 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 59270.585165 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 59270.585165 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 59270.585165 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 59270.585165 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8439 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 33 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 89 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 94.730337 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 94.820225 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -873,24 +873,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 296 system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18780993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 18780993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18780993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 18780993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18780993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 18780993 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077426 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.077426 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.077426 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63449.300676 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63449.300676 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63449.300676 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 63449.300676 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63449.300676 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 63449.300676 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18788993 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 18788993 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18788993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 18788993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18788993 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 18788993 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077406 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077406 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077406 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.077406 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077406 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.077406 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63476.327703 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63476.327703 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63476.327703 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 63476.327703 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63476.327703 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 63476.327703 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified @@ -899,18 +899,18 @@ system.cpu.l2cache.prefetcher.pfInCache 0 # nu system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 192.829480 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 192.769134 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 74 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.203297 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.531593 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 45.093662 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.204225 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008455 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.484820 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 45.082970 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.201345 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008452 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.002752 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000562 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.011769 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.011766 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id @@ -947,16 +947,16 @@ system.cpu.l2cache.overall_misses::cpu.data 113 # system.cpu.l2cache.overall_misses::total 386 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2320000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2320000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18332000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 18332000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18323500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 18323500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5549000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 5549000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 18332000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 18323500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 7869000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 26201000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 18332000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 26192500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 18323500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 7869000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 26201000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 26192500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 296 # number of ReadCleanReq accesses(hits+misses) @@ -983,16 +983,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.790210 system.cpu.l2cache.overall_miss_rate::total 0.879271 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77333.333333 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77333.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67150.183150 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67150.183150 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67119.047619 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67119.047619 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66855.421687 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66855.421687 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67150.183150 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67119.047619 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69637.168142 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67878.238342 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67150.183150 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67856.217617 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67119.047619 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69637.168142 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67878.238342 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67856.217617 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1030,17 +1030,17 @@ system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1625 system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1625926 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2140000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2140000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 16650500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 16650500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4788500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4788500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16650500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6928500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23579000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16650500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6928500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 16642000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 16642000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4788000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4788000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16642000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6928000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23570000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16642000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6928000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25204926 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25195926 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses @@ -1060,18 +1060,24 @@ system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33873 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33873.458333 # average HardPFReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71333.333333 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71333.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61215.073529 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61215.073529 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61391.025641 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61391.025641 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61215.073529 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64152.777778 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62050 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61215.073529 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64152.777778 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61183.823529 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61183.823529 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61384.615385 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61384.615385 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61183.823529 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64148.148148 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62026.315789 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61183.823529 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64148.148148 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33873.458333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58890.014019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58868.985981 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 482 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 21 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 21 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 32 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFReq 64 # Transaction distribution @@ -1087,15 +1093,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 64 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 546 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.117216 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.321973 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.133700 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.340641 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 482 88.28% 88.28% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 64 11.72% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 473 86.63% 86.63% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 73 13.37% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 546 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) @@ -1122,9 +1128,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 407 # Request fanout histogram -system.membus.reqLayer0.occupancy 514444 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 514944 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2136000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2135000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 12.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 85d747802..d4b2570c8 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 25816500 # Number of ticks simulated -final_tick 25816500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 25848500 # Number of ticks simulated +final_tick 25848500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 428411 # Simulator instruction rate (inst/s) -host_op_rate 499438 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2416370273 # Simulator tick rate (ticks/s) -host_mem_usage 308620 # Number of bytes of host memory used +host_inst_rate 341128 # Simulator instruction rate (inst/s) +host_op_rate 397821 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1927554064 # Simulator tick rate (ticks/s) +host_mem_usage 312280 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4566 # Number of instructions simulated sim_ops 5330 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 557782813 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 309879341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 867662154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 557782813 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 557782813 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 557782813 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 309879341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 867662154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 557092288 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 309495715 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 866588003 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 557092288 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 557092288 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 557092288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 309495715 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 866588003 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 51633 # number of cpu cycles simulated +system.cpu.numCycles 51697 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4566 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 1965 # nu system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 51632.998000 # Number of busy cycles +system.cpu.num_busy_cycles 51696.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1008 # Number of branches fetched @@ -208,14 +208,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5391 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.893462 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 82.887597 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.893462 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020238 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020238 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 82.887597 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020236 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020236 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id @@ -242,14 +242,14 @@ system.cpu.dcache.demand_misses::cpu.data 141 # n system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses system.cpu.dcache.overall_misses::total 141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4734000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4734000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7099000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7099000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7099000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7099000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -270,14 +270,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48306.122449 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 48306.122449 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 50347.517730 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 50347.517730 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 50347.517730 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 50347.517730 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -294,14 +294,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4620000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4620000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4636000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4636000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2322000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2322000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6942000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6942000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6942000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6942000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6958000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6958000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6958000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6958000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses @@ -310,24 +310,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47142.857143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47142.857143 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47306.122449 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47306.122449 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49234.042553 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 49234.042553 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49347.517730 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 49347.517730 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49347.517730 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 49347.517730 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 114.412880 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 114.411093 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 114.412880 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.055866 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.055866 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 114.411093 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.055865 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.055865 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id @@ -346,12 +346,12 @@ system.cpu.icache.demand_misses::cpu.inst 241 # n system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses system.cpu.icache.overall_misses::total 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12588500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12588500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12588500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12588500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12588500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12604500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12604500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12604500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12604500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12604500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12604500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses @@ -364,12 +364,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052323 system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52234.439834 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52234.439834 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52234.439834 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52234.439834 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52300.829876 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52300.829876 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52300.829876 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52300.829876 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52300.829876 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52300.829876 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -384,33 +384,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 241 system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12347500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12347500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12347500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12347500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12347500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12347500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12363500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12363500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12363500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12363500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12363500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12363500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51234.439834 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51234.439834 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51234.439834 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51234.439834 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51234.439834 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51234.439834 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51300.829876 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51300.829876 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51300.829876 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51300.829876 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51300.829876 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51300.829876 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 153.810302 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 153.806088 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.682127 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48.128175 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.680973 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48.125115 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003225 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004694 # Average percentage of cache occupancy @@ -547,6 +547,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42524.444444 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42515.714286 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution @@ -560,14 +566,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 383 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.086162 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.280970 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 383 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 350 91.38% 91.38% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 33 8.62% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 383 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 191500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index d3878acf4..c52a652eb 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 22451000 # Number of ticks simulated final_tick 22451000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 41665 # Simulator instruction rate (inst/s) -host_op_rate 41658 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 187549895 # Simulator tick rate (ticks/s) -host_mem_usage 287968 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 76638 # Simulator instruction rate (inst/s) +host_op_rate 76622 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 344943613 # Simulator tick rate (ticks/s) +host_mem_usage 294148 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 4986 # Number of instructions simulated sim_ops 4986 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -912,6 +912,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67358.231707 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71294.326241 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68541.577825 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -926,15 +932,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 489 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 489 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 489 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 489 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 7140a68cc..d99d61508 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000031 # Nu sim_ticks 30902500 # Number of ticks simulated final_tick 30902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 339265 # Simulator instruction rate (inst/s) -host_op_rate 338999 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1861147916 # Simulator tick rate (ticks/s) -host_mem_usage 289452 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 459853 # Simulator instruction rate (inst/s) +host_op_rate 459290 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2521006690 # Simulator tick rate (ticks/s) +host_mem_usage 291832 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -435,6 +435,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.706485 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.162791 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 13 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 13 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -449,15 +455,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 27648 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 445 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 445 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 445 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 445 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 222500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 585054648..1b72b1558 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19922000 # Number of ticks simulated -final_tick 19922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19923000 # Number of ticks simulated +final_tick 19923000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 38523 # Simulator instruction rate (inst/s) -host_op_rate 38518 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 132470471 # Simulator tick rate (ticks/s) -host_mem_usage 286104 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 93968 # Simulator instruction rate (inst/s) +host_op_rate 93947 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 323084408 # Simulator tick rate (ticks/s) +host_mem_usage 291680 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21952 # Nu system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory system.physmem.num_reads::total 444 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1101897400 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 324465415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1426362815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1101897400 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1101897400 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1101897400 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 324465415 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1426362815 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1101842092 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 324449129 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1426291221 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1101842092 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1101842092 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1101842092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 324449129 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1426291221 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 444 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 19782500 # Total gap between requests +system.physmem.totGap 19783500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -200,15 +200,15 @@ system.physmem.bytesPerActivate::768-895 1 1.32% 84.21% # By system.physmem.bytesPerActivate::896-1023 3 3.95% 88.16% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 9 11.84% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation -system.physmem.totQLat 3750750 # Total ticks spent queuing -system.physmem.totMemAccLat 12075750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3746750 # Total ticks spent queuing +system.physmem.totMemAccLat 12071750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8447.64 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8438.63 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27197.64 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1426.36 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27188.63 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1426.29 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1426.36 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1426.29 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 11.14 # Data bus utilization in percentage @@ -220,7 +220,7 @@ system.physmem.readRowHits 359 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.86 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 44555.18 # Average gap between requests +system.physmem.avgGap 44557.43 # Average gap between requests system.physmem.pageHitRate 80.86 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 438480 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 239250 # Energy for precharge commands per rank (pJ) @@ -245,7 +245,7 @@ system.physmem_1.actBackEnergy 7628310 # En system.physmem_1.preBackEnergy 2808000 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 11847195 # Total energy per rank (pJ) system.physmem_1.averagePower 748.283278 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 6322250 # Time in different power states +system.physmem_1.memoryStateTime::IDLE 6323250 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 10715250 # Time in different power states @@ -279,7 +279,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 39845 # number of cpu cycles simulated +system.cpu.numCycles 39847 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 7679 # Number of cycles fetch is stalled on an Icache miss @@ -310,8 +310,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 12019 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.059204 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.330983 # Number of inst fetches per cycle +system.cpu.fetch.branchRate 0.059201 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.330966 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 7188 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 2504 # Number of cycles decode is blocked system.cpu.decode.RunCycles 1924 # Number of cycles decode is running @@ -437,7 +437,7 @@ system.cpu.iq.FU_type_0::MemWrite 1500 16.97% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 8840 # Type of FU issued -system.cpu.iq.rate 0.221860 # Inst issue rate +system.cpu.iq.rate 0.221849 # Inst issue rate system.cpu.iq.fu_busy_cnt 201 # FU busy when requested system.cpu.iq.fu_busy_rate 0.022738 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 29890 # Number of integer instruction queue reads @@ -481,13 +481,13 @@ system.cpu.iew.exec_nop 0 # nu system.cpu.iew.exec_refs 3121 # number of memory reference insts executed system.cpu.iew.exec_branches 1355 # Number of branches executed system.cpu.iew.exec_stores 1414 # Number of stores executed -system.cpu.iew.exec_rate 0.212950 # Inst execution rate +system.cpu.iew.exec_rate 0.212939 # Inst execution rate system.cpu.iew.wb_sent 8249 # cumulative count of insts sent to commit system.cpu.iew.wb_count 8147 # cumulative count of insts written-back system.cpu.iew.wb_producers 4452 # num instructions producing a value system.cpu.iew.wb_consumers 7114 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.204467 # insts written-back per cycle +system.cpu.iew.wb_rate 0.204457 # insts written-back per cycle system.cpu.iew.wb_fanout 0.625808 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 4414 # The number of squashed insts skipped by commit @@ -559,24 +559,24 @@ system.cpu.commit.bw_lim_events 110 # nu system.cpu.rob.rob_reads 21420 # The number of ROB reads system.cpu.rob.rob_writes 21108 # The number of ROB writes system.cpu.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27826 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 27828 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.879316 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.879316 # CPI: Total CPI of All Threads -system.cpu.ipc 0.145363 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.145363 # IPC: Total IPC of All Threads +system.cpu.cpi 6.879662 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.879662 # CPI: Total CPI of All Threads +system.cpu.ipc 0.145356 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.145356 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 13451 # number of integer regfile reads system.cpu.int_regfile_writes 7138 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 64.587343 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 64.587514 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2213 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 103 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 21.485437 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 64.587343 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 64.587514 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.015768 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.015768 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 103 # Occupied blocks per task id @@ -601,14 +601,14 @@ system.cpu.dcache.demand_misses::cpu.data 433 # n system.cpu.dcache.demand_misses::total 433 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 433 # number of overall misses system.cpu.dcache.overall_misses::total 433 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7902500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7902500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7905500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7905500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 23909996 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 23909996 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31812496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31812496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31812496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31812496 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31815496 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31815496 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31815496 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31815496 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1600 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1600 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -625,14 +625,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.163643 system.cpu.dcache.demand_miss_rate::total 0.163643 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.163643 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.163643 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73171.296296 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73171.296296 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73199.074074 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73199.074074 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73569.218462 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 73569.218462 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73469.967667 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73469.967667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73469.967667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73469.967667 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73476.896074 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73476.896074 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73476.896074 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73476.896074 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 598 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked @@ -657,14 +657,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 103 system.cpu.dcache.demand_mshr_misses::total 103 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 103 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 103 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4528500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4528500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4530500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4530500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4006498 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4006498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8534998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8534998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8534998 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8534998 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8536998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8536998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8536998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8536998 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035000 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035000 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses @@ -673,22 +673,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038927 system.cpu.dcache.demand_mshr_miss_rate::total 0.038927 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038927 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.038927 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80866.071429 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80866.071429 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80901.785714 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80901.785714 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85244.638298 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85244.638298 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82864.058252 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 82864.058252 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82864.058252 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 82864.058252 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82883.475728 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82883.475728 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82883.475728 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82883.475728 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 168.966654 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 168.966455 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1389 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.979943 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 168.966654 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 168.966455 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.082503 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.082503 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id @@ -709,12 +709,12 @@ system.cpu.icache.demand_misses::cpu.inst 433 # n system.cpu.icache.demand_misses::total 433 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 433 # number of overall misses system.cpu.icache.overall_misses::total 433 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32237500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32237500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32237500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32237500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32237500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32237500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32239500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32239500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32239500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32239500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32239500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32239500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1822 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1822 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1822 # number of demand (read+write) accesses @@ -727,12 +727,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.237651 system.cpu.icache.demand_miss_rate::total 0.237651 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.237651 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.237651 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74451.501155 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74451.501155 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74451.501155 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74451.501155 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74451.501155 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74451.501155 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74456.120092 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74456.120092 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74456.120092 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74456.120092 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74456.120092 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74456.120092 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 497 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -753,39 +753,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 350 system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26589500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26589500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26589500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26589500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26589500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 26589500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26591500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26591500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26591500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26591500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26591500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26591500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.192097 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.192097 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.192097 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75970 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75970 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75970 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75970 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75970 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75970 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75975.714286 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75975.714286 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75975.714286 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75975.714286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75975.714286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75975.714286 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 199.677803 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 199.677769 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.020151 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.770664 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.907139 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.770776 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.906993 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005120 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000974 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006094 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4068 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4068 # Number of data accesses @@ -813,16 +813,16 @@ system.cpu.l2cache.overall_misses::cpu.data 101 # system.cpu.l2cache.overall_misses::total 445 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3932500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 26002500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 26002500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25998500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 25998500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4422500 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 4422500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 26002500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 25998500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 8355000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34357500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 26002500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 34353500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 25998500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 8355000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34357500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34353500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 350 # number of ReadCleanReq accesses(hits+misses) @@ -849,16 +849,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.980583 system.cpu.l2cache.overall_miss_rate::total 0.982340 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83670.212766 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83670.212766 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75588.662791 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75588.662791 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75577.034884 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75577.034884 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81898.148148 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81898.148148 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75588.662791 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75577.034884 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82722.772277 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77207.865169 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75588.662791 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77198.876404 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75577.034884 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82722.772277 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77207.865169 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77198.876404 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -881,16 +881,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 101 system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3462500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3462500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22572500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22572500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22568500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22568500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3882500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3882500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22572500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22568500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7345000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29917500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22572500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29913500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22568500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7345000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 29917500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29913500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadCleanReq accesses @@ -905,17 +905,23 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980583 system.cpu.l2cache.overall_mshr_miss_rate::total 0.982340 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73670.212766 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73670.212766 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65617.732558 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65617.732558 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65606.104651 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65606.104651 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71898.148148 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71898.148148 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65617.732558 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65606.104651 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72722.772277 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67230.337079 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65617.732558 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67221.348315 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65606.104651 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72722.772277 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67230.337079 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67221.348315 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 453 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 8 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 405 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution @@ -929,14 +935,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 28928 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 453 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.017660 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.131858 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 453 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 445 98.23% 98.23% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 8 1.77% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 453 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index fd8319ed7..a369fae45 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 27800500 # Number of ticks simulated -final_tick 27800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 27803500 # Number of ticks simulated +final_tick 27803500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 428112 # Simulator instruction rate (inst/s) -host_op_rate 427631 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2229390537 # Simulator tick rate (ticks/s) -host_mem_usage 290104 # Number of bytes of host memory used +host_inst_rate 506128 # Simulator instruction rate (inst/s) +host_op_rate 505504 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2635153066 # Simulator tick rate (ticks/s) +host_mem_usage 292480 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated @@ -21,17 +21,17 @@ system.physmem.bytes_inst_read::total 16320 # Nu system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 389 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 587039801 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 308483660 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 895523462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 587039801 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 587039801 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 587039801 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 308483660 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 895523462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 586976460 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 308450375 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 895426835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 586976460 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 586976460 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 586976460 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 308450375 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 895426835 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 55601 # number of cpu cycles simulated +system.cpu.numCycles 55607 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5327 # Number of instructions committed @@ -50,7 +50,7 @@ system.cpu.num_mem_refs 1401 # nu system.cpu.num_load_insts 723 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 55600.998000 # Number of busy cycles +system.cpu.num_busy_cycles 55606.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1121 # Number of branches fetched @@ -90,12 +90,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5370 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.112122 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 82.111103 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.112122 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 82.111103 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.020047 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.020047 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id @@ -120,14 +120,14 @@ system.cpu.dcache.demand_misses::cpu.data 135 # n system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses system.cpu.dcache.overall_misses::total 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2929000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2929000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7384000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7384000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7384000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7384000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -144,14 +144,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54240.740741 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54240.740741 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54696.296296 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54696.296296 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54696.296296 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54696.296296 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -168,14 +168,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2874000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2874000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2875000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2875000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4374000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4374000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7248000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7248000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7248000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7248000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7249000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7249000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7249000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7249000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -184,24 +184,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53222.222222 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53222.222222 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53240.740741 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53240.740741 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53688.888889 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53688.888889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53688.888889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53688.888889 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53696.296296 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53696.296296 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53696.296296 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53696.296296 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 117.032289 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 117.031458 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 117.032289 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057145 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057145 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 117.031458 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057144 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057144 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id @@ -220,12 +220,12 @@ system.cpu.icache.demand_misses::cpu.inst 257 # n system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses system.cpu.icache.overall_misses::total 257 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14051500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14051500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14051500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14051500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14051500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14053500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14053500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14053500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14053500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14053500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14053500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses @@ -238,12 +238,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.047850 system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54675.097276 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54675.097276 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54675.097276 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54675.097276 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54682.879377 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54682.879377 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54682.879377 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54682.879377 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54682.879377 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54682.879377 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -258,33 +258,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 257 system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13794500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13794500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13794500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13794500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13794500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13794500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13796500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13796500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13796500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13796500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13796500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13796500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53675.097276 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53675.097276 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53675.097276 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53675.097276 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53675.097276 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53675.097276 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53682.879377 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53682.879377 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53682.879377 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53682.879377 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53682.879377 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53682.879377 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 142.153744 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 142.152541 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.494223 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 25.659521 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.493414 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 25.659127 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003555 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004338 # Average percentage of cache occupancy @@ -421,6 +421,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.960784 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.285347 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 392 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution @@ -434,14 +440,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 392 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.007653 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.087258 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 392 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 389 99.23% 99.23% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3 0.77% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 392 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index e476df038..b13c74560 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20817000 # Number of ticks simulated -final_tick 20817000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20818000 # Number of ticks simulated +final_tick 20818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31285 # Simulator instruction rate (inst/s) -host_op_rate 56673 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 121026192 # Simulator tick rate (ticks/s) -host_mem_usage 306568 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 48919 # Simulator instruction rate (inst/s) +host_op_rate 88616 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 189245943 # Simulator tick rate (ticks/s) +host_mem_usage 313416 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17664 # Nu system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 139 # Number of read requests responded to by this memory system.physmem.num_reads::total 415 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 848537253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 427343037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1275880290 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 848537253 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 848537253 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 848537253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 427343037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1275880290 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 848496493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 427322509 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1275819003 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 848496493 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 848496493 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 848496493 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 427322509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1275819003 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 415 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 415 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20721000 # Total gap between requests +system.physmem.totGap 20722000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -206,9 +206,9 @@ system.physmem.totBusLat 2075000 # To system.physmem.avgQLat 11433.73 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 30183.73 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1275.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBW 1275.82 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1275.88 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1275.82 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 9.97 # Data bus utilization in percentage @@ -220,7 +220,7 @@ system.physmem.readRowHits 309 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 74.46 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 49930.12 # Average gap between requests +system.physmem.avgGap 49932.53 # Average gap between requests system.physmem.pageHitRate 74.46 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ) @@ -262,7 +262,7 @@ system.cpu.branchPred.RASInCorrect 86 # Nu system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 41635 # number of cpu cycles simulated +system.cpu.numCycles 41637 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 11661 # Number of cycles fetch is stalled on an Icache miss @@ -293,8 +293,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 22725 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.077675 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.351555 # Number of inst fetches per cycle +system.cpu.fetch.branchRate 0.077671 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.351538 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 11462 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 7072 # Number of cycles decode is blocked system.cpu.decode.RunCycles 3206 # Number of cycles decode is running @@ -417,7 +417,7 @@ system.cpu.iq.FU_type_0::MemWrite 1369 7.98% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 17161 # Type of FU issued -system.cpu.iq.rate 0.412177 # Inst issue rate +system.cpu.iq.rate 0.412157 # Inst issue rate system.cpu.iq.fu_busy_cnt 212 # FU busy when requested system.cpu.iq.fu_busy_rate 0.012354 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 57316 # Number of integer instruction queue reads @@ -461,13 +461,13 @@ system.cpu.iew.exec_nop 0 # nu system.cpu.iew.exec_refs 3175 # number of memory reference insts executed system.cpu.iew.exec_branches 1626 # Number of branches executed system.cpu.iew.exec_stores 1262 # Number of stores executed -system.cpu.iew.exec_rate 0.390657 # Inst execution rate +system.cpu.iew.exec_rate 0.390638 # Inst execution rate system.cpu.iew.wb_sent 16001 # cumulative count of insts sent to commit system.cpu.iew.wb_count 15771 # cumulative count of insts written-back system.cpu.iew.wb_producers 10637 # num instructions producing a value system.cpu.iew.wb_consumers 16589 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.378792 # insts written-back per cycle +system.cpu.iew.wb_rate 0.378774 # insts written-back per cycle system.cpu.iew.wb_fanout 0.641208 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 10723 # The number of squashed insts skipped by commit @@ -539,13 +539,13 @@ system.cpu.commit.bw_lim_events 255 # nu system.cpu.rob.rob_reads 41158 # The number of ROB reads system.cpu.rob.rob_writes 42744 # The number of ROB writes system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18910 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 18912 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.738848 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.738848 # CPI: Total CPI of All Threads -system.cpu.ipc 0.129218 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.129218 # IPC: Total IPC of All Threads +system.cpu.cpi 7.739219 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.739219 # CPI: Total CPI of All Threads +system.cpu.ipc 0.129212 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.129212 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 20871 # number of integer regfile reads system.cpu.int_regfile_writes 12651 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads @@ -554,12 +554,12 @@ system.cpu.cc_regfile_writes 4880 # nu system.cpu.misc_regfile_reads 7277 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.971685 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 81.973847 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2383 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 139 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 17.143885 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.971685 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 81.973847 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.020013 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.020013 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 139 # Occupied blocks per task id @@ -664,17 +664,17 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83758.992806 system.cpu.dcache.overall_avg_mshr_miss_latency::total 83758.992806 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 130.298609 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 130.304167 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1706 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 277 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 6.158845 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 130.298609 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063622 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063622 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 130.304167 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.063625 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063625 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 277 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.135254 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4427 # Number of tag accesses system.cpu.icache.tags.data_accesses 4427 # Number of data accesses @@ -690,12 +690,12 @@ system.cpu.icache.demand_misses::cpu.inst 369 # n system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses system.cpu.icache.overall_misses::total 369 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28131500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28131500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28131500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28131500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28131500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28131500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28132500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28132500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28132500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28132500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28132500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28132500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2075 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2075 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2075 # number of demand (read+write) accesses @@ -708,12 +708,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.177831 system.cpu.icache.demand_miss_rate::total 0.177831 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.177831 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.177831 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76237.127371 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76237.127371 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76237.127371 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76237.127371 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76237.127371 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76237.127371 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76239.837398 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76239.837398 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76239.837398 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76239.837398 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76239.837398 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76239.837398 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -734,33 +734,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 277 system.cpu.icache.demand_mshr_misses::total 277 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 277 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22318000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22318000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22318000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22318000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22318000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22318000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22319000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22319000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22319000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22319000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22319000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22319000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133494 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.133494 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133494 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.133494 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80570.397112 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80570.397112 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80570.397112 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 80570.397112 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80570.397112 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 80570.397112 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80574.007220 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80574.007220 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80574.007220 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 80574.007220 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80574.007220 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 80574.007220 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 162.374270 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 162.380689 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 338 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002959 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.338432 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32.035838 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.343988 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 32.036700 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003978 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000978 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004955 # Average percentage of cache occupancy @@ -893,6 +893,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69317.028986 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72255.395683 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70301.204819 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 416 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution @@ -906,14 +912,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 416 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002404 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.049029 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 416 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 415 99.76% 99.76% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.24% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 416 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 208000 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index ef7ce3c79..a52dc699f 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 28358500 # Number of ticks simulated -final_tick 28358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 28359500 # Number of ticks simulated +final_tick 28359500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 304372 # Simulator instruction rate (inst/s) -host_op_rate 550952 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1601632215 # Simulator tick rate (ticks/s) -host_mem_usage 308112 # Number of bytes of host memory used +host_inst_rate 279983 # Simulator instruction rate (inst/s) +host_op_rate 506758 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1473373857 # Simulator tick rate (ticks/s) +host_mem_usage 311136 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated @@ -21,18 +21,18 @@ system.physmem.bytes_inst_read::total 14528 # Nu system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 361 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 512297900 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 302413738 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 814711638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 512297900 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 512297900 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 512297900 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 302413738 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 814711638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 512279836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 302403075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 814682910 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 512279836 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 512279836 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 512279836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 302403075 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 814682910 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 56717 # number of cpu cycles simulated +system.cpu.numCycles 56719 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5381 # Number of instructions committed @@ -53,7 +53,7 @@ system.cpu.num_mem_refs 1988 # nu system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 56716.998000 # Number of busy cycles +system.cpu.num_busy_cycles 56718.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched @@ -93,14 +93,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 9748 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 80.791087 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 80.792611 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 80.791087 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019724 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019724 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 80.792611 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.019725 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.019725 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id @@ -197,14 +197,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 105.540319 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 105.543720 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 105.540319 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.051533 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.051533 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 105.543720 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.051535 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.051535 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id @@ -223,12 +223,12 @@ system.cpu.icache.demand_misses::cpu.inst 228 # n system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses system.cpu.icache.overall_misses::total 228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12498500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12498500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12498500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12498500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12498500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12499500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12499500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12499500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12499500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12499500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12499500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses @@ -241,12 +241,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.033217 system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54817.982456 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54817.982456 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54817.982456 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54817.982456 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54817.982456 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54817.982456 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54822.368421 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54822.368421 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54822.368421 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54822.368421 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54822.368421 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54822.368421 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -261,33 +261,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 228 system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12270500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12270500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12270500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12270500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12270500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12270500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12271500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12271500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12271500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12271500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12271500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12271500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53817.982456 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53817.982456 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53817.982456 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53817.982456 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53817.982456 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53817.982456 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53822.368421 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53822.368421 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53822.368421 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53822.368421 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53822.368421 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53822.368421 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 134.006917 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 134.010901 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.536457 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.470460 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.539859 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.471042 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy @@ -420,6 +420,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42502.202643 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.385042 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution @@ -433,14 +439,14 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 362 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002762 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.052559 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 362 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 361 99.72% 99.72% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.28% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) |