diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-10-20 16:48:19 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-10-20 16:48:19 -0500 |
| commit | d2a0f60b69313ad869f81fb006c8e998e40cb3c1 (patch) | |
| tree | 39b323ea65cc3c21cf3b00a05df44bcec214c580 /tests/quick/se/00.hello/ref | |
| parent | 922a9d8ed2488a3483dbbfff47a4f341fb707b7b (diff) | |
| download | gem5-d2a0f60b69313ad869f81fb006c8e998e40cb3c1.tar.xz | |
stats: updates due to previous mmap and exit_group patches.
Diffstat (limited to 'tests/quick/se/00.hello/ref')
21 files changed, 1864 insertions, 1862 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index d8727c544..c9776266f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -599,7 +599,7 @@ system.cpu.cpi 6.446328 # CP system.cpu.cpi_total 6.446328 # CPI: Total CPI of All Threads system.cpu.ipc 0.155127 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.155127 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12991 # number of integer regfile reads +system.cpu.int_regfile_reads 12992 # number of integer regfile reads system.cpu.int_regfile_writes 7455 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 54adfc503..d08d4e917 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -371,9 +371,9 @@ system.cpu.tickCycles 10521 # Nu system.cpu.idleCycles 45301 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 3 # number of replacements system.cpu.icache.tags.tagsinuse 162.201432 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1919 # Total number of references to valid blocks. +system.cpu.icache.tags.total_refs 1918 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.978193 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.975078 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 162.201432 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.079200 # Average percentage of cache occupancy @@ -382,14 +382,14 @@ system.cpu.icache.tags.occ_task_id_blocks::1024 318 system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4801 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4801 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1919 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1919 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1919 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1919 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1919 # number of overall hits -system.cpu.icache.overall_hits::total 1919 # number of overall hits +system.cpu.icache.tags.tag_accesses 4799 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4799 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1918 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1918 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1918 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1918 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1918 # number of overall hits +system.cpu.icache.overall_hits::total 1918 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses @@ -402,18 +402,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 21503250 system.cpu.icache.demand_miss_latency::total 21503250 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 21503250 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 21503250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2240 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2240 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2240 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2240 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2240 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2240 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143304 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.143304 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.143304 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.143304 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.143304 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.143304 # miss rate for overall accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 2239 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2239 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2239 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2239 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2239 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2239 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143368 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.143368 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.143368 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.143368 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.143368 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.143368 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66988.317757 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 66988.317757 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency @@ -440,12 +440,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20730750 system.cpu.icache.demand_mshr_miss_latency::total 20730750 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20730750 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 20730750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143304 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.143304 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.143304 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143368 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.143368 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143368 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.143368 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64581.775701 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64581.775701 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 092386ab8..62f6dcd2b 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -457,7 +457,7 @@ system.cpu.fetch.Insts 12484 # Nu system.cpu.fetch.Branches 2638 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 1137 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 4850 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1010 # Number of cycles fetch has spent squashing +system.cpu.fetch.SquashCycles 1011 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR @@ -728,7 +728,7 @@ system.cpu.commit.op_class_0::total 5377 # Cl system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.rob.rob_reads 22692 # The number of ROB reads -system.cpu.rob.rob_writes 21719 # The number of ROB writes +system.cpu.rob.rob_writes 21720 # The number of ROB writes system.cpu.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 19014 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated @@ -737,7 +737,7 @@ system.cpu.cpi 7.067523 # CP system.cpu.cpi_total 7.067523 # CPI: Total CPI of All Threads system.cpu.ipc 0.141492 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.141492 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7944 # number of integer regfile reads +system.cpu.int_regfile_reads 7945 # number of integer regfile reads system.cpu.int_regfile_writes 4420 # number of integer regfile writes system.cpu.fp_regfile_reads 31 # number of floating regfile reads system.cpu.cc_regfile_reads 28734 # number of cc regfile reads diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index ce3916e93..6fc5d6de3 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -375,7 +375,7 @@ system.cpu.fetch.Insts 12370 # Nu system.cpu.fetch.Branches 2560 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 794 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 11397 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1062 # Number of cycles fetch has spent squashing +system.cpu.fetch.SquashCycles 1063 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 322 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 84 # Number of stall cycles due to full MSHR @@ -643,7 +643,7 @@ system.cpu.commit.op_class_0::total 5377 # Cl system.cpu.commit.bw_lim_events 52 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.rob.rob_reads 24066 # The number of ROB reads -system.cpu.rob.rob_writes 16749 # The number of ROB writes +system.cpu.rob.rob_writes 16750 # The number of ROB writes system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 6973 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated @@ -652,7 +652,7 @@ system.cpu.cpi 5.166630 # CP system.cpu.cpi_total 5.166630 # CPI: Total CPI of All Threads system.cpu.ipc 0.193550 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.193550 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6786 # number of integer regfile reads +system.cpu.int_regfile_reads 6787 # number of integer regfile reads system.cpu.int_regfile_writes 3839 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.cc_regfile_reads 24301 # number of cc regfile reads diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 9b7b2bcb6..398374723 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -256,10 +256,10 @@ system.cpu.num_cc_register_writes 2432 # nu system.cpu.num_mem_refs 1965 # number of memory refs system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5390 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 5389.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1007 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index 73cde8525..d2d36b722 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -169,10 +169,10 @@ system.cpu.num_cc_register_writes 2432 # nu system.cpu.num_mem_refs 1965 # number of memory refs system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5390 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 5389.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1007 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 8f2c9257f..83a7fcb5f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -158,10 +158,10 @@ system.cpu.num_cc_register_writes 2432 # nu system.cpu.num_mem_refs 1965 # number of memory refs system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 51630 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 51629.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1007 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index beeb90a4c..1593f969f 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,55 +1,55 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 24907000 # Number of ticks simulated -final_tick 24907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000024 # Number of seconds simulated +sim_ticks 24417000 # Number of ticks simulated +final_tick 24417000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 46022 # Simulator instruction rate (inst/s) -host_op_rate 46018 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 197122402 # Simulator tick rate (ticks/s) -host_mem_usage 234444 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -sim_insts 5814 # Number of instructions simulated -sim_ops 5814 # Number of ops (including micro ops) simulated +host_inst_rate 26948 # Simulator instruction rate (inst/s) +host_op_rate 26945 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 116974890 # Simulator tick rate (ticks/s) +host_mem_usage 277212 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host +sim_insts 5624 # Number of instructions simulated +sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory -system.physmem.bytes_read::total 29120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 20288 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 20288 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory -system.physmem.num_reads::total 455 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 814550126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 354599109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1169149235 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 814550126 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 814550126 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 814550126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 354599109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1169149235 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 455 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8768 # Number of bytes read from this memory +system.physmem.bytes_read::total 28800 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory +system.physmem.num_reads::total 450 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 820412008 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 359094074 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1179506082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 820412008 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 820412008 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 820412008 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 359094074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1179506082 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 450 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 455 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 450 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 29120 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 28800 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 29120 # Total read bytes from the system interface side +system.physmem.bytesReadSys 28800 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28 # Per bank write bursts +system.physmem.perBankRdBursts::0 27 # Per bank write bursts system.physmem.perBankRdBursts::1 0 # Per bank write bursts system.physmem.perBankRdBursts::2 0 # Per bank write bursts system.physmem.perBankRdBursts::3 0 # Per bank write bursts system.physmem.perBankRdBursts::4 8 # Per bank write bursts system.physmem.perBankRdBursts::5 3 # Per bank write bursts system.physmem.perBankRdBursts::6 12 # Per bank write bursts -system.physmem.perBankRdBursts::7 51 # Per bank write bursts -system.physmem.perBankRdBursts::8 59 # Per bank write bursts +system.physmem.perBankRdBursts::7 50 # Per bank write bursts +system.physmem.perBankRdBursts::8 56 # Per bank write bursts system.physmem.perBankRdBursts::9 75 # Per bank write bursts system.physmem.perBankRdBursts::10 36 # Per bank write bursts system.physmem.perBankRdBursts::11 19 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 24826000 # Total gap between requests +system.physmem.totGap 24336000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 455 # Read request sizes (log2) +system.physmem.readPktSize::6 450 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 303 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 299 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see @@ -186,97 +186,98 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 106 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 268.075472 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.680617 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 244.800860 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 25 23.58% 23.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40 37.74% 61.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14 13.21% 74.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 10 9.43% 83.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 7 6.60% 90.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 1.89% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 2.83% 95.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 4.72% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 106 # Bytes accessed per row activation -system.physmem.totQLat 4936500 # Total ticks spent queuing -system.physmem.totMemAccLat 13467750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2275000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10849.45 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 103 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 276.504854 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 191.986288 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 256.190297 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 25 24.27% 24.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 37 35.92% 60.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14 13.59% 73.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8 7.77% 81.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8 7.77% 89.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 1.94% 91.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 2.91% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 0.97% 95.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 4.85% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation +system.physmem.totQLat 4914500 # Total ticks spent queuing +system.physmem.totMemAccLat 13352000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2250000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10921.11 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29599.45 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1169.15 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29671.11 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1179.51 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1169.15 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1179.51 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.13 # Data bus utilization in percentage -system.physmem.busUtilRead 9.13 # Data bus utilization in percentage for reads +system.physmem.busUtil 9.21 # Data bus utilization in percentage +system.physmem.busUtilRead 9.21 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.51 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 344 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.60 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.44 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 54562.64 # Average gap between requests -system.physmem.pageHitRate 75.60 # Row buffer hit rate, read and write combined +system.physmem.avgGap 54080.00 # Average gap between requests +system.physmem.pageHitRate 76.44 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 11000 # Time in different power states system.physmem.memoryStateTime::REF 780000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 22841500 # Time in different power states +system.physmem.memoryStateTime::ACT 22851000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 196560 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::0 181440 # Energy for activate commands per rank (pJ) system.physmem.actEnergy::1 582120 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 107250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::0 99000 # Energy for precharge commands per rank (pJ) system.physmem.preEnergy::1 317625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 756600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 2644200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::0 772200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 2652000 # Energy for read commands per rank (pJ) system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) system.physmem.refreshEnergy::0 1525680 # Energy for refresh commands per rank (pJ) system.physmem.refreshEnergy::1 1525680 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 14747040 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 16041510 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::0 14753880 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 16048350 # Energy for active background per rank (pJ) system.physmem.preBackEnergy::0 1235250 # Energy for precharge background per rank (pJ) system.physmem.preBackEnergy::1 99750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 18568380 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 21210885 # Total energy per rank (pJ) -system.physmem.averagePower::0 786.171156 # Core power per rank (mW) -system.physmem.averagePower::1 898.052818 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 404 # Transaction distribution -system.membus.trans_dist::ReadResp 404 # Transaction distribution -system.membus.trans_dist::ReadExReq 51 # Transaction distribution -system.membus.trans_dist::ReadExResp 51 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 910 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 29120 # Cumulative packet size per connected master and slave (bytes) +system.physmem.totalEnergy::0 18567450 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 21225525 # Total energy per rank (pJ) +system.physmem.averagePower::0 785.799080 # Core power per rank (mW) +system.physmem.averagePower::1 898.292335 # Core power per rank (mW) +system.membus.trans_dist::ReadReq 400 # Transaction distribution +system.membus.trans_dist::ReadResp 400 # Transaction distribution +system.membus.trans_dist::ReadExReq 50 # Transaction distribution +system.membus.trans_dist::ReadExResp 50 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 900 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28800 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 455 # Request fanout histogram +system.membus.snoop_fanout::samples 450 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 455 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 450 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 455 # Request fanout histogram -system.membus.reqLayer0.occupancy 552000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 450 # Request fanout histogram +system.membus.reqLayer0.occupancy 545500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4259500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 4210750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 1156 # Number of BP lookups -system.cpu.branchPred.condPredicted 861 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 603 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 879 # Number of BTB lookups -system.cpu.branchPred.BTBHits 339 # Number of BTB hits +system.cpu.branchPred.lookups 1124 # Number of BP lookups +system.cpu.branchPred.condPredicted 833 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 586 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 850 # Number of BTB lookups +system.cpu.branchPred.BTBHits 329 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 38.566553 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 86 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 38.705882 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 84 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -295,118 +296,118 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 49815 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 7 # Number of system calls +system.cpu.numCycles 48835 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 432 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 724 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5088 # Number of Reads from Int. Register File -system.cpu.regfile_manager.intRegFileWrites 3396 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 8484 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.branch_predictor.predictedTaken 421 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 703 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 4929 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileWrites 3280 # Number of Writes to Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 8209 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1328 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 2229 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 274 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 320 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 594 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 321 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 64.918033 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 3133 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed +system.cpu.regfile_manager.regForwards 1292 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 2173 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 263 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 315 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 578 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 305 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 65.458664 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 3019 # Number of Instructions Executed. +system.cpu.mult_div_unit.multiplies 2 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9484 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9295 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 462 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 44434 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 5381 # Number of cycles cpu stages are processed. -system.cpu.activity 10.801967 # Percentage of cycles cpu is active -system.cpu.comLoads 1163 # Number of Load instructions committed -system.cpu.comStores 925 # Number of Store instructions committed -system.cpu.comBranches 915 # Number of Branches instructions committed -system.cpu.comNops 657 # Number of Nop instructions committed -system.cpu.comNonSpec 10 # Number of Non-Speculative instructions committed -system.cpu.comInts 2144 # Number of Integer instructions committed +system.cpu.timesIdled 454 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 43587 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 5248 # Number of cycles cpu stages are processed. +system.cpu.activity 10.746391 # Percentage of cycles cpu is active +system.cpu.comLoads 1132 # Number of Load instructions committed +system.cpu.comStores 901 # Number of Store instructions committed +system.cpu.comBranches 883 # Number of Branches instructions committed +system.cpu.comNops 637 # Number of Nop instructions committed +system.cpu.comNonSpec 9 # Number of Non-Speculative instructions committed +system.cpu.comInts 2062 # Number of Integer instructions committed system.cpu.comFloats 0 # Number of Floating Point instructions committed -system.cpu.committedInsts 5814 # Number of Instructions committed (Per-Thread) -system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread) +system.cpu.committedInsts 5624 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 5624 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) -system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total) -system.cpu.cpi 8.568111 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.committedInsts_total 5624 # Number of Instructions committed (Total) +system.cpu.cpi 8.683321 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 8.568111 # CPI: Total CPI of All Threads -system.cpu.ipc 0.116712 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 8.683321 # CPI: Total CPI of All Threads +system.cpu.ipc 0.115163 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.116712 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 46168 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 3647 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 7.321088 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 47003 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 2812 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 5.644886 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 47048 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 2767 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 5.554552 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 48577 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 1238 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.485195 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 46929 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 2886 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 5.793436 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.115163 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 45291 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 3544 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 7.257090 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 46099 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 2736 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 5.602539 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 46145 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 2690 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 5.508344 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 47641 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 1194 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 2.444968 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46041 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 2794 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 5.721306 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 150.581339 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 428 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 319 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1.341693 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 147.900639 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 418 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 315 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1.326984 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 150.581339 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073526 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073526 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 306 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.149414 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1875 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1875 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 428 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 428 # number of overall hits -system.cpu.icache.overall_hits::total 428 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses -system.cpu.icache.overall_misses::total 350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25285250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25285250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25285250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25285250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25285250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25285250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 778 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 778 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 778 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 778 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.449871 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.449871 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.449871 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.449871 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.449871 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.449871 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72243.571429 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72243.571429 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72243.571429 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72243.571429 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72243.571429 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72243.571429 # average overall miss latency +system.cpu.icache.tags.occ_blocks::cpu.inst 147.900639 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.072217 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.072217 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 302 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.147461 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1839 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1839 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 418 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 418 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 418 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 418 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 418 # number of overall hits +system.cpu.icache.overall_hits::total 418 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 344 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 344 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 344 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 344 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 344 # number of overall misses +system.cpu.icache.overall_misses::total 344 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25151000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25151000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25151000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25151000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25151000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25151000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 762 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 762 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 762 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 762 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 762 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 762 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.451444 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.451444 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.451444 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.451444 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.451444 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.451444 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73113.372093 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73113.372093 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 73113.372093 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73113.372093 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 73113.372093 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73113.372093 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -415,143 +416,143 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 31 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 31 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 31 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 31 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 31 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 31 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 319 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 319 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 319 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22950250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22950250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22950250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22950250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22950250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22950250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.410026 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.410026 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.410026 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71944.357367 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71944.357367 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71944.357367 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71944.357367 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71944.357367 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71944.357367 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 29 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 29 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 29 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 29 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 29 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 29 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22975000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22975000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22975000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22975000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22975000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22975000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.413386 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.413386 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.413386 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.413386 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.413386 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.413386 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72936.507937 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72936.507937 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72936.507937 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72936.507937 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72936.507937 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72936.507937 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 638 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 914 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 29248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 402 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 402 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 630 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 904 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28928 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 457 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 452 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 457 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 457 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 228500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 538750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 532000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 226250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 224750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 208.342392 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 204.797884 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 404 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.004950 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 400 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.005000 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.263135 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.079256 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004647 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001711 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006358 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 249 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012329 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4111 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4111 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::cpu.inst 149.365797 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 55.432088 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004558 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001692 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006250 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012207 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4066 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4066 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 317 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 313 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 404 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 317 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 455 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses -system.cpu.l2cache.overall_misses::total 455 # number of overall misses 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(read+write) accesses -system.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083405 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.083405 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381622 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.381622 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.215517 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.215517 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.215517 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.215517 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78791.237113 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 78791.237113 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61302.407932 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61302.407932 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65072.222222 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65072.222222 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65072.222222 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65072.222222 # average overall miss latency +system.cpu.dcache.WriteReq_misses::cpu.data 340 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 340 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses +system.cpu.dcache.overall_misses::total 437 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7368000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7368000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20584000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20584000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27952000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27952000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27952000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27952000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085689 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.085689 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.377358 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.377358 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.214953 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.214953 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.214953 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.214953 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75958.762887 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75958.762887 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60541.176471 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60541.176471 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63963.386728 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63963.386728 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63963.386728 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63963.386728 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked @@ -678,44 +679,44 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 302 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 302 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 312 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 312 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 312 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 312 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 290 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 290 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 300 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 300 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 300 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 300 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6978500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6978500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3866750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3866750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10845250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10845250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10845250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10845250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80212.643678 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80212.643678 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75818.627451 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75818.627451 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78588.768116 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78588.768116 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78588.768116 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78588.768116 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6703250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6703250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3776500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3776500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10479750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10479750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10479750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10479750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77048.850575 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77048.850575 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75530 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75530 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76494.525547 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76494.525547 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76494.525547 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76494.525547 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 83678472a..61d4efb5a 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,56 +1,56 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 21611500 # Number of ticks simulated -final_tick 21611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000021 # Number of seconds simulated +sim_ticks 21163500 # Number of ticks simulated +final_tick 21163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52948 # Simulator instruction rate (inst/s) -host_op_rate 52941 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 221880610 # Simulator tick rate (ticks/s) -host_mem_usage 236528 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -sim_insts 5156 # Number of instructions simulated -sim_ops 5156 # Number of ops (including micro ops) simulated +host_inst_rate 24711 # Simulator instruction rate (inst/s) +host_op_rate 24708 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 104867636 # Simulator tick rate (ticks/s) +host_mem_usage 278232 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host +sim_insts 4986 # Number of instructions simulated +sim_ops 4986 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 21568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory -system.physmem.bytes_read::total 30656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21568 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 337 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory -system.physmem.num_reads::total 479 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 997987183 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 420516854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1418504037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 997987183 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 997987183 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 997987183 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 420516854 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1418504037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 479 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 21120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory +system.physmem.bytes_read::total 30144 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21120 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 330 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory +system.physmem.num_reads::total 471 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 997944574 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 426394500 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1424339074 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 997944574 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 997944574 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 997944574 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 426394500 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1424339074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 471 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 479 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 471 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30656 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 30144 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30656 # Total read bytes from the system interface side +system.physmem.bytesReadSys 30144 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 30 # Per bank write bursts +system.physmem.perBankRdBursts::0 29 # Per bank write bursts system.physmem.perBankRdBursts::1 0 # Per bank write bursts system.physmem.perBankRdBursts::2 1 # Per bank write bursts system.physmem.perBankRdBursts::3 0 # Per bank write bursts system.physmem.perBankRdBursts::4 7 # Per bank write bursts system.physmem.perBankRdBursts::5 3 # Per bank write bursts system.physmem.perBankRdBursts::6 13 # Per bank write bursts -system.physmem.perBankRdBursts::7 54 # Per bank write bursts -system.physmem.perBankRdBursts::8 64 # Per bank write bursts -system.physmem.perBankRdBursts::9 77 # Per bank write bursts +system.physmem.perBankRdBursts::7 53 # Per bank write bursts +system.physmem.perBankRdBursts::8 59 # Per bank write bursts +system.physmem.perBankRdBursts::9 76 # Per bank write bursts system.physmem.perBankRdBursts::10 43 # Per bank write bursts system.physmem.perBankRdBursts::11 20 # Per bank write bursts system.physmem.perBankRdBursts::12 51 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21538500 # Total gap between requests +system.physmem.totGap 21083000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 479 # Read request sizes (log2) +system.physmem.readPktSize::6 471 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 39 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,41 +186,42 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 109 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 255.412844 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.780194 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 251.892291 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 32 29.36% 29.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38 34.86% 64.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15 13.76% 77.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 11 10.09% 88.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 2.75% 90.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 2.75% 93.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 1.83% 95.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 4.59% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 109 # Bytes accessed per row activation -system.physmem.totQLat 5601000 # Total ticks spent queuing -system.physmem.totMemAccLat 14582250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2395000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11693.11 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 105 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 262.095238 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.705030 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 253.763121 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 30 28.57% 28.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 34 32.38% 60.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 17 16.19% 77.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 10 9.52% 86.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 3.81% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 0.95% 91.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 1.90% 93.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 1.90% 95.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 4.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 105 # Bytes accessed per row activation +system.physmem.totQLat 5392000 # Total ticks spent queuing +system.physmem.totMemAccLat 14223250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2355000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11447.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30443.11 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1418.50 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30197.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1424.34 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1418.50 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1424.34 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.08 # Data bus utilization in percentage -system.physmem.busUtilRead 11.08 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.13 # Data bus utilization in percentage +system.physmem.busUtilRead 11.13 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.75 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 360 # Number of row buffer hits during reads +system.physmem.readRowHits 356 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.16 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 44965.55 # Average gap between requests -system.physmem.pageHitRate 75.16 # Row buffer hit rate, read and write combined +system.physmem.avgGap 44762.21 # Average gap between requests +system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 11000 # Time in different power states system.physmem.memoryStateTime::REF 520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states @@ -244,39 +245,39 @@ system.physmem.totalEnergy::0 12518970 # To system.physmem.totalEnergy::1 14949930 # Total energy per rank (pJ) system.physmem.averagePower::0 790.713406 # Core power per rank (mW) system.physmem.averagePower::1 944.255803 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 428 # Transaction distribution -system.membus.trans_dist::ReadResp 428 # Transaction distribution -system.membus.trans_dist::ReadExReq 51 # Transaction distribution -system.membus.trans_dist::ReadExResp 51 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 958 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 958 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30656 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 30656 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 421 # Transaction distribution +system.membus.trans_dist::ReadResp 421 # Transaction distribution +system.membus.trans_dist::ReadExReq 50 # Transaction distribution +system.membus.trans_dist::ReadExResp 50 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 942 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 942 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 479 # Request fanout histogram +system.membus.snoop_fanout::samples 471 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 479 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 471 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 479 # Request fanout histogram -system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 471 # Request fanout histogram +system.membus.reqLayer0.occupancy 594000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4492250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 20.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 4415500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 20.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 2196 # Number of BP lookups -system.cpu.branchPred.condPredicted 1454 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 435 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1700 # Number of BTB lookups -system.cpu.branchPred.BTBHits 564 # Number of BTB hits +system.cpu.branchPred.lookups 2146 # Number of BP lookups +system.cpu.branchPred.condPredicted 1406 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 427 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1636 # Number of BTB lookups +system.cpu.branchPred.BTBHits 528 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 33.176471 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 277 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 69 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 32.273839 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 284 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -295,495 +296,495 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 43224 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 7 # Number of system calls +system.cpu.numCycles 42328 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 9138 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13312 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2196 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 841 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4920 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 886 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 8967 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13064 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2146 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 812 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4771 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 872 # Number of cycles fetch has spent squashing system.cpu.fetch.PendingTrapStallCycles 202 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2068 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14703 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.905393 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.198604 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2037 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 262 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14376 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.908737 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.207470 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11282 76.73% 76.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1513 10.29% 87.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 130 0.88% 87.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 159 1.08% 88.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 291 1.98% 90.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 99 0.67% 91.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 152 1.03% 92.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 125 0.85% 93.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 952 6.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11035 76.76% 76.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1473 10.25% 87.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 126 0.88% 87.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 160 1.11% 89.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 283 1.97% 90.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 90 0.63% 91.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 137 0.95% 92.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 121 0.84% 93.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 951 6.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14703 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.050805 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.307977 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8679 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2634 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2860 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 400 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 179 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 47 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12297 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 180 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 400 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8850 # Number of cycles rename is idle +system.cpu.fetch.rateDist::total 14376 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.050699 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.308637 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8549 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2515 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2791 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 395 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 174 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12032 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 172 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 395 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8711 # Number of cycles rename is idle system.cpu.rename.BlockCycles 502 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 975 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2807 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1169 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11801 # Number of instructions processed by rename +system.cpu.rename.serializeStallCycles 944 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2743 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1081 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11544 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 281 # Number of times rename has blocked due to LQ full +system.cpu.rename.LQFullEvents 196 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 868 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 7107 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13927 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13678 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 6963 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13597 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13345 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3709 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 16 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 307 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2543 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1213 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.CommittedMaps 3282 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 3681 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 13 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 298 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2503 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1169 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9299 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8548 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 29 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3486 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1874 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 9029 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8280 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3419 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1838 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14703 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.581378 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.331585 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14376 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.575960 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.325471 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11282 76.73% 76.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1346 9.15% 85.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 761 5.18% 91.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 427 2.90% 93.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 364 2.48% 96.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 316 2.15% 98.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 114 0.78% 99.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 65 0.44% 99.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 28 0.19% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11054 76.89% 76.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1314 9.14% 86.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 739 5.14% 91.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 413 2.87% 94.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 345 2.40% 96.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 315 2.19% 98.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 104 0.72% 99.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 66 0.46% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 26 0.18% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14703 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14376 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8 3.96% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 135 66.83% 70.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 59 29.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 4.06% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 131 66.50% 70.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 58 29.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5034 58.89% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.06% 58.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2396 28.03% 87.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1109 12.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4865 58.76% 58.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2336 28.21% 87.05% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1072 12.95% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8548 # Type of FU issued -system.cpu.iq.rate 0.197761 # Inst issue rate -system.cpu.iq.fu_busy_cnt 202 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023631 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 32026 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12803 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7708 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8280 # Type of FU issued +system.cpu.iq.rate 0.195615 # Inst issue rate +system.cpu.iq.fu_busy_cnt 197 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023792 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31160 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12466 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7466 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8748 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8475 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 86 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 82 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1380 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1371 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 288 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 400 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 479 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10879 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 152 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2543 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1213 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 395 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 475 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10593 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 153 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2503 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1169 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 105 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 359 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 464 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8213 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2257 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 335 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 354 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 452 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7957 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2194 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 323 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1568 # number of nop insts executed -system.cpu.iew.exec_refs 3348 # number of memory reference insts executed -system.cpu.iew.exec_branches 1425 # Number of branches executed -system.cpu.iew.exec_stores 1091 # Number of stores executed -system.cpu.iew.exec_rate 0.190010 # Inst execution rate -system.cpu.iew.wb_sent 7817 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7710 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2989 # num instructions producing a value -system.cpu.iew.wb_consumers 4523 # num instructions consuming a value +system.cpu.iew.exec_nop 1553 # number of nop insts executed +system.cpu.iew.exec_refs 3252 # number of memory reference insts executed +system.cpu.iew.exec_branches 1379 # Number of branches executed +system.cpu.iew.exec_stores 1058 # Number of stores executed +system.cpu.iew.exec_rate 0.187984 # Inst execution rate +system.cpu.iew.wb_sent 7571 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7468 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2915 # num instructions producing a value +system.cpu.iew.wb_consumers 4399 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.178373 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660845 # average fanout of values written-back +system.cpu.iew.wb_rate 0.176432 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.662651 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5063 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 392 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13824 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.420501 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.238844 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 4969 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 386 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13506 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.416333 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.231872 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11590 83.84% 83.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 886 6.41% 90.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 537 3.88% 94.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 260 1.88% 96.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 148 1.07% 97.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 189 1.37% 98.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 68 0.49% 98.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 40 0.29% 99.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106 0.77% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11333 83.91% 83.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 875 6.48% 90.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 515 3.81% 94.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 250 1.85% 96.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 149 1.10% 97.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 177 1.31% 98.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 64 0.47% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.30% 99.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 102 0.76% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13824 # Number of insts commited each cycle -system.cpu.commit.committedInsts 5813 # Number of instructions committed -system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 13506 # Number of insts commited each cycle +system.cpu.commit.committedInsts 5623 # Number of instructions committed +system.cpu.commit.committedOps 5623 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 2088 # Number of memory references committed -system.cpu.commit.loads 1163 # Number of loads committed +system.cpu.commit.refs 2033 # Number of memory references committed +system.cpu.commit.loads 1132 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 915 # Number of branches committed +system.cpu.commit.branches 883 # Number of branches committed system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. -system.cpu.commit.int_insts 5111 # Number of committed integer instructions. -system.cpu.commit.function_calls 87 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 657 11.30% 11.30% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 3062 52.68% 63.98% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 3 0.05% 64.03% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 1 0.02% 64.05% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 2 0.03% 64.08% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.08% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.08% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.08% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.08% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.08% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.08% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.08% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.08% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.08% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.08% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.08% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.08% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.08% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.08% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.08% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.08% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.08% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.08% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.08% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.08% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.08% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 64.08% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.08% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.08% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.08% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 1163 20.01% 84.09% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 925 15.91% 100.00% # Class of committed instruction +system.cpu.commit.int_insts 4942 # Number of committed integer instructions. +system.cpu.commit.function_calls 85 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 637 11.33% 11.33% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 2949 52.45% 63.77% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2 0.04% 63.81% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.81% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 2 0.04% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.84% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1132 20.13% 83.98% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 901 16.02% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 5813 # Class of committed instruction -system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 5623 # Class of committed instruction +system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 24581 # The number of ROB reads -system.cpu.rob.rob_writes 22642 # The number of ROB writes -system.cpu.timesIdled 280 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 28521 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 5156 # Number of Instructions Simulated -system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.383243 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.383243 # CPI: Total CPI of All Threads -system.cpu.ipc 0.119286 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.119286 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11114 # number of integer regfile reads -system.cpu.int_regfile_writes 5412 # number of integer regfile writes +system.cpu.rob.rob_reads 23983 # The number of ROB reads +system.cpu.rob.rob_writes 22065 # The number of ROB writes +system.cpu.timesIdled 275 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27952 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 4986 # Number of Instructions Simulated +system.cpu.committedOps 4986 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 8.489370 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.489370 # CPI: Total CPI of All Threads +system.cpu.ipc 0.117794 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.117794 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10767 # number of integer regfile reads +system.cpu.int_regfile_writes 5247 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 164 # number of misc regfile reads -system.cpu.toL2Bus.trans_dist::ReadReq 431 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 431 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 680 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 964 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 666 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 948 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30336 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 482 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 474 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 482 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 474 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 482 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 474 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 237000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 575000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 562000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 228250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 227000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 161.371303 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1615 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 340 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.750000 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 158.344728 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1593 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 333 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.783784 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 161.371303 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078795 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078795 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 323 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.157715 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4476 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4476 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1615 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1615 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1615 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1615 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1615 # number of overall hits -system.cpu.icache.overall_hits::total 1615 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 453 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 453 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 453 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 453 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 453 # number of overall misses -system.cpu.icache.overall_misses::total 453 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31446500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31446500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31446500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31446500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31446500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31446500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2068 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2068 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2068 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.219052 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.219052 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.219052 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.219052 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.219052 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.219052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69418.322296 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69418.322296 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69418.322296 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69418.322296 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69418.322296 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69418.322296 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 158.344728 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077317 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077317 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 316 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.154297 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4407 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4407 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1593 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1593 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1593 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1593 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1593 # number of overall hits +system.cpu.icache.overall_hits::total 1593 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 444 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 444 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 444 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 444 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 444 # number of overall misses +system.cpu.icache.overall_misses::total 444 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30764750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30764750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30764750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30764750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30764750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30764750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2037 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2037 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2037 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2037 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2037 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2037 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.217968 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.217968 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.217968 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.217968 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.217968 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.217968 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69289.977477 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69289.977477 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69289.977477 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69289.977477 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69289.977477 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69289.977477 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 48 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 113 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 113 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 113 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 113 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 113 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 340 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 340 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 340 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 340 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 340 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 340 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24622500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24622500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24622500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24622500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24622500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24622500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.164410 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.164410 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.164410 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.164410 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.164410 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.164410 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72419.117647 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72419.117647 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72419.117647 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72419.117647 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72419.117647 # average overall mshr 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-system.cpu.dcache.tags.tag_accesses 6220 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 6220 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1945 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1945 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 563 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2508 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2508 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2508 # number of overall hits -system.cpu.dcache.overall_hits::total 2508 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 169 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 169 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 362 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 362 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 531 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 531 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 531 # number of overall misses -system.cpu.dcache.overall_misses::total 531 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11707000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11707000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23264249 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23264249 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34971249 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34971249 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34971249 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34971249 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2114 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2114 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 3039 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 3039 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 3039 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 3039 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079943 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.079943 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.391351 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.391351 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.174729 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.174729 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.174729 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.174729 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69272.189349 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 69272.189349 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64265.881215 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64265.881215 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65859.225989 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65859.225989 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65859.225989 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65859.225989 # average overall miss latency +system.cpu.dcache.tags.occ_blocks::cpu.data 91.168146 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022258 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022258 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1893 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1893 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 552 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 552 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2445 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2445 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2445 # number of overall hits +system.cpu.dcache.overall_hits::total 2445 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 349 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 349 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 515 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 515 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 515 # number of overall misses +system.cpu.dcache.overall_misses::total 515 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11320500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11320500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22383749 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22383749 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33704249 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33704249 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33704249 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33704249 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2059 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2059 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2960 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2960 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2960 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2960 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080622 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.080622 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.387347 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.387347 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.173986 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.173986 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.173986 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.173986 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68195.783133 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68195.783133 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64136.816619 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64136.816619 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65445.143689 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65445.143689 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked @@ -908,46 +909,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.090909 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 311 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 311 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 389 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 389 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 389 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 389 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 299 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 299 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7380750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7380750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4107999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4107999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11488749 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11488749 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11488749 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11488749 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.043046 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.043046 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.046726 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.046726 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046726 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.046726 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81107.142857 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81107.142857 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80549 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80549 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80906.683099 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80906.683099 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80906.683099 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80906.683099 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7311000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7311000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4032499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4032499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11343499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11343499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11343499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11343499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044196 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044196 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.047635 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.047635 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80340.659341 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80340.659341 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80649.980000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80649.980000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt index 49c05c732..87429446a 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2907000 # Number of ticks simulated -final_tick 2907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2812000 # Number of ticks simulated +final_tick 2812000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 972729 # Simulator instruction rate (inst/s) -host_op_rate 970456 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 484177215 # Simulator tick rate (ticks/s) -host_mem_usage 275596 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 5814 # Number of instructions simulated -sim_ops 5814 # Number of ops (including micro ops) simulated +host_inst_rate 65844 # Simulator instruction rate (inst/s) +host_op_rate 65830 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32908431 # Simulator tick rate (ticks/s) +host_mem_usage 267356 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +sim_insts 5624 # Number of instructions simulated +sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 23260 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 4374 # Number of bytes read from this memory -system.physmem.bytes_read::total 27634 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 23260 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 23260 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 3658 # Number of bytes written to this memory -system.physmem.bytes_written::total 3658 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5815 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1163 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6978 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 925 # Number of write requests responded to by this memory -system.physmem.num_writes::total 925 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 8001375989 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1504643963 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9506019952 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8001375989 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8001375989 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1258341933 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1258341933 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8001375989 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2762985896 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10764361885 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 6978 # Transaction distribution -system.membus.trans_dist::ReadResp 6978 # Transaction distribution -system.membus.trans_dist::WriteReq 925 # Transaction distribution -system.membus.trans_dist::WriteResp 925 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11630 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4176 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15806 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 23260 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8032 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 31292 # Cumulative packet size per connected master and slave (bytes) +system.physmem.bytes_read::cpu.inst 22500 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 4289 # Number of bytes read from this memory +system.physmem.bytes_read::total 26789 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 22500 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 22500 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 3601 # Number of bytes written to this memory +system.physmem.bytes_written::total 3601 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5625 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1132 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6757 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 901 # Number of write requests responded to by this memory +system.physmem.num_writes::total 901 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8001422475 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1525248933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9526671408 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8001422475 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8001422475 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1280583215 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1280583215 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8001422475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2805832148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10807254623 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 6757 # Transaction distribution +system.membus.trans_dist::ReadResp 6757 # Transaction distribution +system.membus.trans_dist::WriteReq 901 # Transaction distribution +system.membus.trans_dist::WriteResp 901 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11250 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4066 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15316 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 22500 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 7890 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30390 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7903 # Request fanout histogram -system.membus.snoop_fanout::mean 0.735797 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.440936 # Request fanout histogram +system.membus.snoop_fanout::samples 7658 # Request fanout histogram +system.membus.snoop_fanout::mean 0.734526 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.441614 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2088 26.42% 26.42% # Request fanout histogram -system.membus.snoop_fanout::1 5815 73.58% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2033 26.55% 26.55% # Request fanout histogram +system.membus.snoop_fanout::1 5625 73.45% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 7903 # Request fanout histogram +system.membus.snoop_fanout::total 7658 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -75,64 +75,64 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 5815 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 7 # Number of system calls +system.cpu.numCycles 5625 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5814 # Number of instructions committed -system.cpu.committedOps 5814 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 5113 # Number of integer alu accesses +system.cpu.committedInsts 5624 # Number of instructions committed +system.cpu.committedOps 5624 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses -system.cpu.num_func_calls 194 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 676 # number of instructions that are conditional controls -system.cpu.num_int_insts 5113 # number of integer instructions +system.cpu.num_func_calls 190 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls +system.cpu.num_int_insts 4944 # number of integer instructions system.cpu.num_fp_insts 2 # number of float instructions -system.cpu.num_int_register_reads 7284 # number of times the integer registers were read -system.cpu.num_int_register_writes 3397 # number of times the integer registers were written +system.cpu.num_int_register_reads 7054 # number of times the integer registers were read +system.cpu.num_int_register_writes 3281 # number of times the integer registers were written system.cpu.num_fp_register_reads 3 # number of times the floating registers were read system.cpu.num_fp_register_writes 1 # number of times the floating registers were written -system.cpu.num_mem_refs 2089 # number of memory refs -system.cpu.num_load_insts 1163 # Number of load instructions -system.cpu.num_store_insts 926 # Number of store instructions +system.cpu.num_mem_refs 2034 # number of memory refs +system.cpu.num_load_insts 1132 # Number of load instructions +system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5815 # Number of busy cycles +system.cpu.num_busy_cycles 5625 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 915 # Number of branches fetched -system.cpu.op_class::No_OpClass 657 11.30% 11.30% # Class of executed instruction -system.cpu.op_class::IntAlu 3063 52.67% 63.97% # Class of executed instruction -system.cpu.op_class::IntMult 3 0.05% 64.02% # Class of executed instruction -system.cpu.op_class::IntDiv 1 0.02% 64.04% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 64.08% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::MemRead 1163 20.00% 84.08% # Class of executed instruction -system.cpu.op_class::MemWrite 926 15.92% 100.00% # Class of executed instruction +system.cpu.Branches 883 # Number of branches fetched +system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction +system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction +system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction +system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5815 # Class of executed instruction +system.cpu.op_class::total 5625 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 88e0b5c68..e8e105f9d 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000125 # Number of seconds simulated -sim_ticks 125334 # Number of ticks simulated -final_tick 125334 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000123 # Number of seconds simulated +sim_ticks 122907 # Number of ticks simulated +final_tick 122907 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 56489 # Simulator instruction rate (inst/s) -host_op_rate 56481 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1217426 # Simulator tick rate (ticks/s) -host_mem_usage 162604 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -sim_insts 5814 # Number of instructions simulated -sim_ops 5814 # Number of ops (including micro ops) simulated +host_inst_rate 19204 # Simulator instruction rate (inst/s) +host_op_rate 19202 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 419624 # Simulator tick rate (ticks/s) +host_mem_usage 174296 # Number of bytes of host memory used +host_seconds 0.29 # Real time elapsed on the host +sim_insts 5624 # Number of instructions simulated +sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 2982 # delay histogram for all message -system.ruby.delayHist | 2982 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 2982 # delay histogram for all message +system.ruby.delayHist::samples 2936 # delay histogram for all message +system.ruby.delayHist | 2936 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 2936 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 7904 +system.ruby.outstanding_req_hist::samples 7659 system.ruby.outstanding_req_hist::mean 1 system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 7904 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 7904 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 7659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 7659 system.ruby.latency_hist::bucket_size 16 system.ruby.latency_hist::max_bucket 159 -system.ruby.latency_hist::samples 7903 -system.ruby.latency_hist::mean 14.859041 -system.ruby.latency_hist::gmean 5.372254 -system.ruby.latency_hist::stdev 24.716041 -system.ruby.latency_hist | 6410 81.11% 81.11% | 0 0.00% 81.11% | 0 0.00% 81.11% | 328 4.15% 85.26% | 1088 13.77% 99.03% | 74 0.94% 99.96% | 3 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 7903 +system.ruby.latency_hist::samples 7658 +system.ruby.latency_hist::mean 15.049491 +system.ruby.latency_hist::gmean 5.422767 +system.ruby.latency_hist::stdev 24.869733 +system.ruby.latency_hist | 6188 80.80% 80.80% | 0 0.00% 80.80% | 0 0.00% 80.80% | 330 4.31% 85.11% | 1061 13.85% 98.97% | 77 1.01% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 7658 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 6410 +system.ruby.hit_latency_hist::samples 6188 system.ruby.hit_latency_hist::mean 3 system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6410 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 6410 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6188 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 6188 system.ruby.miss_latency_hist::bucket_size 16 system.ruby.miss_latency_hist::max_bucket 159 -system.ruby.miss_latency_hist::samples 1493 -system.ruby.miss_latency_hist::mean 65.774280 -system.ruby.miss_latency_hist::gmean 65.543617 -system.ruby.miss_latency_hist::stdev 6.088981 -system.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 328 21.97% 21.97% | 1088 72.87% 94.84% | 74 4.96% 99.80% | 3 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 1493 -system.ruby.Directory.incomplete_times 1492 +system.ruby.miss_latency_hist::samples 1470 +system.ruby.miss_latency_hist::mean 65.772109 +system.ruby.miss_latency_hist::gmean 65.537231 +system.ruby.miss_latency_hist::stdev 6.143987 +system.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 330 22.45% 22.45% | 1061 72.18% 94.63% | 77 5.24% 99.86% | 2 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 1470 +system.ruby.Directory.incomplete_times 1469 system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.l1_cntrl0.cacheMemory.demand_hits 6410 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 1493 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7903 # Number of cache demand accesses -system.ruby.network.routers0.percent_links_utilized 5.948107 -system.ruby.network.routers0.msg_count.Control::2 1493 -system.ruby.network.routers0.msg_count.Data::2 1489 -system.ruby.network.routers0.msg_count.Response_Data::4 1493 -system.ruby.network.routers0.msg_count.Writeback_Control::3 1489 -system.ruby.network.routers0.msg_bytes.Control::2 11944 -system.ruby.network.routers0.msg_bytes.Data::2 107208 -system.ruby.network.routers0.msg_bytes.Response_Data::4 107496 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11912 -system.ruby.dir_cntrl0.memBuffer.memReq 2982 # Total number of memory requests -system.ruby.dir_cntrl0.memBuffer.memRead 1493 # Number of memory reads -system.ruby.dir_cntrl0.memBuffer.memWrite 1489 # Number of memory writes -system.ruby.dir_cntrl0.memBuffer.memRefresh 871 # Number of memory refreshes -system.ruby.dir_cntrl0.memBuffer.memWaitCycles 2125 # Delay stalled at the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.memBankQ 5 # Delay behind the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.totalStalls 2130 # Total number of stall cycles -system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.714286 # Expected number of stall cycles per request -system.ruby.dir_cntrl0.memBuffer.memBankBusy 839 # memory stalls due to busy bank -system.ruby.dir_cntrl0.memBuffer.memBusBusy 1172 # memory stalls due to busy bus -system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 34 # memory stalls due to read write turnaround -system.ruby.dir_cntrl0.memBuffer.memArbWait 80 # memory stalls due to arbitration -system.ruby.dir_cntrl0.memBuffer.memBankCount | 236 7.91% 7.91% | 108 3.62% 11.54% | 74 2.48% 14.02% | 51 1.71% 15.73% | 26 0.87% 16.60% | 104 3.49% 20.09% | 18 0.60% 20.69% | 38 1.27% 21.97% | 16 0.54% 22.50% | 52 1.74% 24.25% | 154 5.16% 29.41% | 50 1.68% 31.09% | 22 0.74% 31.82% | 70 2.35% 34.17% | 30 1.01% 35.18% | 220 7.38% 42.56% | 80 2.68% 45.24% | 58 1.95% 47.18% | 80 2.68% 49.87% | 118 3.96% 53.82% | 42 1.41% 55.23% | 52 1.74% 56.98% | 82 2.75% 59.73% | 168 5.63% 65.36% | 116 3.89% 69.25% | 80 2.68% 71.93% | 138 4.63% 76.56% | 110 3.69% 80.25% | 208 6.98% 87.22% | 273 9.15% 96.38% | 40 1.34% 97.72% | 68 2.28% 100.00% # Number of accesses per bank -system.ruby.dir_cntrl0.memBuffer.memBankCount::total 2982 # Number of accesses per bank -system.ruby.network.routers1.percent_links_utilized 5.948107 -system.ruby.network.routers1.msg_count.Control::2 1493 -system.ruby.network.routers1.msg_count.Data::2 1489 -system.ruby.network.routers1.msg_count.Response_Data::4 1493 -system.ruby.network.routers1.msg_count.Writeback_Control::3 1489 -system.ruby.network.routers1.msg_bytes.Control::2 11944 -system.ruby.network.routers1.msg_bytes.Data::2 107208 -system.ruby.network.routers1.msg_bytes.Response_Data::4 107496 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11912 -system.ruby.network.routers2.percent_links_utilized 5.948107 -system.ruby.network.routers2.msg_count.Control::2 1493 -system.ruby.network.routers2.msg_count.Data::2 1489 -system.ruby.network.routers2.msg_count.Response_Data::4 1493 -system.ruby.network.routers2.msg_count.Writeback_Control::3 1489 -system.ruby.network.routers2.msg_bytes.Control::2 11944 -system.ruby.network.routers2.msg_bytes.Data::2 107208 -system.ruby.network.routers2.msg_bytes.Response_Data::4 107496 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11912 -system.ruby.network.msg_count.Control 4479 -system.ruby.network.msg_count.Data 4467 -system.ruby.network.msg_count.Response_Data 4479 -system.ruby.network.msg_count.Writeback_Control 4467 -system.ruby.network.msg_byte.Control 35832 -system.ruby.network.msg_byte.Data 321624 -system.ruby.network.msg_byte.Response_Data 322488 -system.ruby.network.msg_byte.Writeback_Control 35736 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 6188 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 1470 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7658 # Number of cache demand accesses system.cpu.clk_domain.clock 1 # Clock period in ticks +system.ruby.network.routers0.percent_links_utilized 5.971995 +system.ruby.network.routers0.msg_count.Control::2 1470 +system.ruby.network.routers0.msg_count.Data::2 1466 +system.ruby.network.routers0.msg_count.Response_Data::4 1470 +system.ruby.network.routers0.msg_count.Writeback_Control::3 1466 +system.ruby.network.routers0.msg_bytes.Control::2 11760 +system.ruby.network.routers0.msg_bytes.Data::2 105552 +system.ruby.network.routers0.msg_bytes.Response_Data::4 105840 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11728 +system.ruby.dir_cntrl0.memBuffer.memReq 2936 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 1470 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 1466 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 854 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 2108 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memBankQ 2 # Delay behind the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 2110 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.718665 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 845 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 1147 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 40 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 76 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 232 7.90% 7.90% | 108 3.68% 11.58% | 64 2.18% 13.76% | 51 1.74% 15.50% | 26 0.89% 16.38% | 106 3.61% 19.99% | 20 0.68% 20.67% | 38 1.29% 21.97% | 16 0.54% 22.51% | 52 1.77% 24.28% | 138 4.70% 28.99% | 48 1.63% 30.62% | 16 0.54% 31.16% | 70 2.38% 33.55% | 30 1.02% 34.57% | 220 7.49% 42.06% | 80 2.72% 44.79% | 60 2.04% 46.83% | 80 2.72% 49.56% | 118 4.02% 53.58% | 46 1.57% 55.14% | 52 1.77% 56.91% | 84 2.86% 59.78% | 180 6.13% 65.91% | 108 3.68% 69.58% | 74 2.52% 72.10% | 140 4.77% 76.87% | 112 3.81% 80.69% | 198 6.74% 87.43% | 261 8.89% 96.32% | 40 1.36% 97.68% | 68 2.32% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 2936 # Number of accesses per bank +system.ruby.network.routers1.percent_links_utilized 5.971995 +system.ruby.network.routers1.msg_count.Control::2 1470 +system.ruby.network.routers1.msg_count.Data::2 1466 +system.ruby.network.routers1.msg_count.Response_Data::4 1470 +system.ruby.network.routers1.msg_count.Writeback_Control::3 1466 +system.ruby.network.routers1.msg_bytes.Control::2 11760 +system.ruby.network.routers1.msg_bytes.Data::2 105552 +system.ruby.network.routers1.msg_bytes.Response_Data::4 105840 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11728 +system.ruby.network.routers2.percent_links_utilized 5.971995 +system.ruby.network.routers2.msg_count.Control::2 1470 +system.ruby.network.routers2.msg_count.Data::2 1466 +system.ruby.network.routers2.msg_count.Response_Data::4 1470 +system.ruby.network.routers2.msg_count.Writeback_Control::3 1466 +system.ruby.network.routers2.msg_bytes.Control::2 11760 +system.ruby.network.routers2.msg_bytes.Data::2 105552 +system.ruby.network.routers2.msg_bytes.Response_Data::4 105840 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11728 +system.ruby.network.msg_count.Control 4410 +system.ruby.network.msg_count.Data 4398 +system.ruby.network.msg_count.Response_Data 4410 +system.ruby.network.msg_count.Writeback_Control 4398 +system.ruby.network.msg_byte.Control 35280 +system.ruby.network.msg_byte.Data 316656 +system.ruby.network.msg_byte.Response_Data 317520 +system.ruby.network.msg_byte.Writeback_Control 35184 system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -122,182 +122,182 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 125334 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 7 # Number of system calls +system.cpu.numCycles 122907 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5814 # Number of instructions committed -system.cpu.committedOps 5814 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 5113 # Number of integer alu accesses +system.cpu.committedInsts 5624 # Number of instructions committed +system.cpu.committedOps 5624 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses -system.cpu.num_func_calls 194 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 676 # number of instructions that are conditional controls -system.cpu.num_int_insts 5113 # number of integer instructions +system.cpu.num_func_calls 190 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls +system.cpu.num_int_insts 4944 # number of integer instructions system.cpu.num_fp_insts 2 # number of float instructions -system.cpu.num_int_register_reads 7284 # number of times the integer registers were read -system.cpu.num_int_register_writes 3397 # number of times the integer registers were written +system.cpu.num_int_register_reads 7054 # number of times the integer registers were read +system.cpu.num_int_register_writes 3281 # number of times the integer registers were written system.cpu.num_fp_register_reads 3 # number of times the floating registers were read system.cpu.num_fp_register_writes 1 # number of times the floating registers were written -system.cpu.num_mem_refs 2089 # number of memory refs -system.cpu.num_load_insts 1163 # Number of load instructions -system.cpu.num_store_insts 926 # Number of store instructions +system.cpu.num_mem_refs 2034 # number of memory refs +system.cpu.num_load_insts 1132 # Number of load instructions +system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 125334 # Number of busy cycles +system.cpu.num_busy_cycles 122907 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 915 # Number of branches fetched -system.cpu.op_class::No_OpClass 657 11.30% 11.30% # Class of executed instruction -system.cpu.op_class::IntAlu 3063 52.67% 63.97% # Class of executed instruction -system.cpu.op_class::IntMult 3 0.05% 64.02% # Class of executed instruction -system.cpu.op_class::IntDiv 1 0.02% 64.04% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 64.08% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::MemRead 1163 20.00% 84.08% # Class of executed instruction -system.cpu.op_class::MemWrite 926 15.92% 100.00% # Class of executed instruction +system.cpu.Branches 883 # Number of branches fetched +system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction +system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction +system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction +system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5815 # Class of executed instruction -system.ruby.network.routers0.throttle0.link_utilization 5.954490 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1493 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1489 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 107496 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11912 -system.ruby.network.routers0.throttle1.link_utilization 5.941724 -system.ruby.network.routers0.throttle1.msg_count.Control::2 1493 -system.ruby.network.routers0.throttle1.msg_count.Data::2 1489 -system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11944 -system.ruby.network.routers0.throttle1.msg_bytes.Data::2 107208 -system.ruby.network.routers1.throttle0.link_utilization 5.941724 -system.ruby.network.routers1.throttle0.msg_count.Control::2 1493 -system.ruby.network.routers1.throttle0.msg_count.Data::2 1489 -system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11944 -system.ruby.network.routers1.throttle0.msg_bytes.Data::2 107208 -system.ruby.network.routers1.throttle1.link_utilization 5.954490 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1493 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1489 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 107496 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11912 -system.ruby.network.routers2.throttle0.link_utilization 5.954490 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1493 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1489 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 107496 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11912 -system.ruby.network.routers2.throttle1.link_utilization 5.941724 -system.ruby.network.routers2.throttle1.msg_count.Control::2 1493 -system.ruby.network.routers2.throttle1.msg_count.Data::2 1489 -system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11944 -system.ruby.network.routers2.throttle1.msg_bytes.Data::2 107208 +system.cpu.op_class::total 5625 # Class of executed instruction +system.ruby.network.routers0.throttle0.link_utilization 5.978504 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1470 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1466 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 105840 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11728 +system.ruby.network.routers0.throttle1.link_utilization 5.965486 +system.ruby.network.routers0.throttle1.msg_count.Control::2 1470 +system.ruby.network.routers0.throttle1.msg_count.Data::2 1466 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11760 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 105552 +system.ruby.network.routers1.throttle0.link_utilization 5.965486 +system.ruby.network.routers1.throttle0.msg_count.Control::2 1470 +system.ruby.network.routers1.throttle0.msg_count.Data::2 1466 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11760 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 105552 +system.ruby.network.routers1.throttle1.link_utilization 5.978504 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1470 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1466 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 105840 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11728 +system.ruby.network.routers2.throttle0.link_utilization 5.978504 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1470 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1466 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 105840 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11728 +system.ruby.network.routers2.throttle1.link_utilization 5.965486 +system.ruby.network.routers2.throttle1.msg_count.Control::2 1470 +system.ruby.network.routers2.throttle1.msg_count.Data::2 1466 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11760 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 105552 system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 1493 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 1493 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 1493 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 1470 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 1470 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 1470 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 1489 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 1489 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 1489 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 1466 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 1466 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 1466 # delay histogram for vnet_2 system.ruby.LD.latency_hist::bucket_size 16 system.ruby.LD.latency_hist::max_bucket 159 -system.ruby.LD.latency_hist::samples 1163 -system.ruby.LD.latency_hist::mean 39.248495 -system.ruby.LD.latency_hist::gmean 17.996261 -system.ruby.LD.latency_hist::stdev 30.948505 -system.ruby.LD.latency_hist | 486 41.79% 41.79% | 0 0.00% 41.79% | 0 0.00% 41.79% | 147 12.64% 54.43% | 509 43.77% 98.19% | 19 1.63% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 1163 +system.ruby.LD.latency_hist::samples 1132 +system.ruby.LD.latency_hist::mean 39.690813 +system.ruby.LD.latency_hist::gmean 18.392553 +system.ruby.LD.latency_hist::stdev 30.890580 +system.ruby.LD.latency_hist | 465 41.08% 41.08% | 0 0.00% 41.08% | 0 0.00% 41.08% | 147 12.99% 54.06% | 497 43.90% 97.97% | 22 1.94% 99.91% | 1 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 1132 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 486 +system.ruby.LD.hit_latency_hist::samples 465 system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 486 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 486 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 465 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 465 system.ruby.LD.miss_latency_hist::bucket_size 16 system.ruby.LD.miss_latency_hist::max_bucket 159 -system.ruby.LD.miss_latency_hist::samples 677 -system.ruby.LD.miss_latency_hist::mean 65.270310 -system.ruby.LD.miss_latency_hist::gmean 65.122528 -system.ruby.LD.miss_latency_hist::stdev 4.861017 -system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 147 21.71% 21.71% | 509 75.18% 96.90% | 19 2.81% 99.70% | 2 0.30% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 677 +system.ruby.LD.miss_latency_hist::samples 667 +system.ruby.LD.miss_latency_hist::mean 65.269865 +system.ruby.LD.miss_latency_hist::gmean 65.112332 +system.ruby.LD.miss_latency_hist::stdev 5.027167 +system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 147 22.04% 22.04% | 497 74.51% 96.55% | 22 3.30% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 667 system.ruby.ST.latency_hist::bucket_size 16 system.ruby.ST.latency_hist::max_bucket 159 -system.ruby.ST.latency_hist::samples 925 -system.ruby.ST.latency_hist::mean 17.897297 -system.ruby.ST.latency_hist::gmean 6.243616 -system.ruby.ST.latency_hist::stdev 26.860092 -system.ruby.ST.latency_hist | 705 76.22% 76.22% | 0 0.00% 76.22% | 0 0.00% 76.22% | 49 5.30% 81.51% | 158 17.08% 98.59% | 13 1.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 925 +system.ruby.ST.latency_hist::samples 901 +system.ruby.ST.latency_hist::mean 18.103219 +system.ruby.ST.latency_hist::gmean 6.303338 +system.ruby.ST.latency_hist::stdev 27.010521 +system.ruby.ST.latency_hist | 684 75.92% 75.92% | 0 0.00% 75.92% | 0 0.00% 75.92% | 46 5.11% 81.02% | 158 17.54% 98.56% | 13 1.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 901 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 705 +system.ruby.ST.hit_latency_hist::samples 684 system.ruby.ST.hit_latency_hist::mean 3 system.ruby.ST.hit_latency_hist::gmean 3.000000 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 705 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 705 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 684 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 684 system.ruby.ST.miss_latency_hist::bucket_size 16 system.ruby.ST.miss_latency_hist::max_bucket 159 -system.ruby.ST.miss_latency_hist::samples 220 -system.ruby.ST.miss_latency_hist::mean 65.636364 -system.ruby.ST.miss_latency_hist::gmean 65.386932 -system.ruby.ST.miss_latency_hist::stdev 6.334983 -system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 49 22.27% 22.27% | 158 71.82% 94.09% | 13 5.91% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 220 +system.ruby.ST.miss_latency_hist::samples 217 +system.ruby.ST.miss_latency_hist::mean 65.709677 +system.ruby.ST.miss_latency_hist::gmean 65.456791 +system.ruby.ST.miss_latency_hist::stdev 6.376574 +system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 46 21.20% 21.20% | 158 72.81% 94.01% | 13 5.99% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 217 system.ruby.IFETCH.latency_hist::bucket_size 16 system.ruby.IFETCH.latency_hist::max_bucket 159 -system.ruby.IFETCH.latency_hist::samples 5815 -system.ruby.IFETCH.latency_hist::mean 9.497850 -system.ruby.IFETCH.latency_hist::gmean 4.118767 -system.ruby.IFETCH.latency_hist::stdev 19.364276 -system.ruby.IFETCH.latency_hist | 5219 89.75% 89.75% | 0 0.00% 89.75% | 0 0.00% 89.75% | 132 2.27% 92.02% | 421 7.24% 99.26% | 42 0.72% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 5815 +system.ruby.IFETCH.latency_hist::samples 5625 +system.ruby.IFETCH.latency_hist::mean 9.601422 +system.ruby.IFETCH.latency_hist::gmean 4.140083 +system.ruby.IFETCH.latency_hist::stdev 19.494566 +system.ruby.IFETCH.latency_hist | 5039 89.58% 89.58% | 0 0.00% 89.58% | 0 0.00% 89.58% | 137 2.44% 92.02% | 406 7.22% 99.24% | 42 0.75% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 5625 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 5219 +system.ruby.IFETCH.hit_latency_hist::samples 5039 system.ruby.IFETCH.hit_latency_hist::mean 3 system.ruby.IFETCH.hit_latency_hist::gmean 3.000000 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5219 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 5219 +system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5039 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::total 5039 system.ruby.IFETCH.miss_latency_hist::bucket_size 16 system.ruby.IFETCH.miss_latency_hist::max_bucket 159 -system.ruby.IFETCH.miss_latency_hist::samples 596 -system.ruby.IFETCH.miss_latency_hist::mean 66.397651 -system.ruby.IFETCH.miss_latency_hist::gmean 66.083596 -system.ruby.IFETCH.miss_latency_hist::stdev 7.118063 -system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 132 22.15% 22.15% | 421 70.64% 92.79% | 42 7.05% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 596 +system.ruby.IFETCH.miss_latency_hist::samples 586 +system.ruby.IFETCH.miss_latency_hist::mean 66.366894 +system.ruby.IFETCH.miss_latency_hist::gmean 66.054272 +system.ruby.IFETCH.miss_latency_hist::stdev 7.096661 +system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 137 23.38% 23.38% | 406 69.28% 92.66% | 42 7.17% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 586 system.ruby.Directory.miss_mach_latency_hist::bucket_size 16 system.ruby.Directory.miss_mach_latency_hist::max_bucket 159 -system.ruby.Directory.miss_mach_latency_hist::samples 1493 -system.ruby.Directory.miss_mach_latency_hist::mean 65.774280 -system.ruby.Directory.miss_mach_latency_hist::gmean 65.543617 -system.ruby.Directory.miss_mach_latency_hist::stdev 6.088981 -system.ruby.Directory.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 328 21.97% 21.97% | 1088 72.87% 94.84% | 74 4.96% 99.80% | 3 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 1493 +system.ruby.Directory.miss_mach_latency_hist::samples 1470 +system.ruby.Directory.miss_mach_latency_hist::mean 65.772109 +system.ruby.Directory.miss_mach_latency_hist::gmean 65.537231 +system.ruby.Directory.miss_mach_latency_hist::stdev 6.143987 +system.ruby.Directory.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 330 22.45% 22.45% | 1061 72.18% 94.63% | 77 5.24% 99.86% | 2 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::total 1470 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1 @@ -326,51 +326,51 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion | system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 16 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 159 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 677 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 65.270310 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 65.122528 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 4.861017 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 147 21.71% 21.71% | 509 75.18% 96.90% | 19 2.81% 99.70% | 2 0.30% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 677 +system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 667 +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 65.269865 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 65.112332 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 5.027167 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 147 22.04% 22.04% | 497 74.51% 96.55% | 22 3.30% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::total 667 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 16 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 159 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 220 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 65.636364 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 65.386932 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 6.334983 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 49 22.27% 22.27% | 158 71.82% 94.09% | 13 5.91% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 220 +system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 217 +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 65.709677 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 65.456791 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 6.376574 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 46 21.20% 21.20% | 158 72.81% 94.01% | 13 5.99% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::total 217 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 16 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 159 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 596 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 66.397651 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 66.083596 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 7.118063 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 132 22.15% 22.15% | 421 70.64% 92.79% | 42 7.05% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 596 -system.ruby.L1Cache_Controller.Load 1163 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 5815 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 925 0.00% 0.00% -system.ruby.L1Cache_Controller.Data 1493 0.00% 0.00% -system.ruby.L1Cache_Controller.Replacement 1489 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 1489 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 677 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 596 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 220 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 486 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 5219 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 705 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Replacement 1489 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack 1489 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data 1273 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data 220 0.00% 0.00% -system.ruby.Directory_Controller.GETX 1493 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 1489 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1493 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 1489 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 1493 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 1489 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 1493 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 1489 0.00% 0.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 586 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 66.366894 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 66.054272 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 7.096661 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 137 23.38% 23.38% | 406 69.28% 92.66% | 42 7.17% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 586 +system.ruby.L1Cache_Controller.Load 1132 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 5625 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 901 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 1470 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 1466 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 1466 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 667 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 586 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 217 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 465 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 5039 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 684 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 1466 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 1466 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 1253 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 217 0.00% 0.00% +system.ruby.Directory_Controller.GETX 1470 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 1466 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1470 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 1466 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 1470 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 1466 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 1470 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 1466 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index a40ed7ca5..84d2a731d 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,56 +1,56 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000032 # Number of seconds simulated -sim_ticks 31633000 # Number of ticks simulated -final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000031 # Number of seconds simulated +sim_ticks 30902000 # Number of ticks simulated +final_tick 30902000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 442331 # Simulator instruction rate (inst/s) -host_op_rate 441894 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2401898254 # Simulator tick rate (ticks/s) -host_mem_usage 285092 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 5814 # Number of instructions simulated -sim_ops 5814 # Number of ops (including micro ops) simulated +host_inst_rate 104539 # Simulator instruction rate (inst/s) +host_op_rate 104503 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 574021463 # Simulator tick rate (ticks/s) +host_mem_usage 276192 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +sim_insts 5624 # Number of instructions simulated +sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory -system.physmem.bytes_read::total 28096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory -system.physmem.num_reads::total 439 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 608984289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 279202099 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 888186388 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 608984289 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 608984289 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 608984289 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 279202099 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 888186388 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 388 # Transaction distribution -system.membus.trans_dist::ReadResp 388 # Transaction distribution -system.membus.trans_dist::ReadExReq 51 # Transaction distribution -system.membus.trans_dist::ReadExResp 51 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 878 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28096 # Cumulative packet size per connected master and slave (bytes) +system.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8768 # Number of bytes read from this memory +system.physmem.bytes_read::total 27520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 18752 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory +system.physmem.num_reads::total 430 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 606821565 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 283735681 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 890557245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 606821565 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 606821565 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 606821565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 283735681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 890557245 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 380 # Transaction distribution +system.membus.trans_dist::ReadResp 380 # Transaction distribution +system.membus.trans_dist::ReadExReq 50 # Transaction distribution +system.membus.trans_dist::ReadExResp 50 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 439 # Request fanout histogram +system.membus.snoop_fanout::samples 430 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 439 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 439 # Request fanout histogram -system.membus.reqLayer0.occupancy 439000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 430 # Request fanout histogram +system.membus.reqLayer0.occupancy 430000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3951000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3870000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 12.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits @@ -71,116 +71,116 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 63266 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 7 # Number of system calls +system.cpu.numCycles 61804 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5814 # Number of instructions committed -system.cpu.committedOps 5814 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 5113 # Number of integer alu accesses +system.cpu.committedInsts 5624 # Number of instructions committed +system.cpu.committedOps 5624 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses -system.cpu.num_func_calls 194 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 676 # number of instructions that are conditional controls -system.cpu.num_int_insts 5113 # number of integer instructions +system.cpu.num_func_calls 190 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls +system.cpu.num_int_insts 4944 # number of integer instructions system.cpu.num_fp_insts 2 # number of float instructions -system.cpu.num_int_register_reads 7284 # number of times the integer registers were read -system.cpu.num_int_register_writes 3397 # number of times the integer registers were written +system.cpu.num_int_register_reads 7054 # number of times the integer registers were read +system.cpu.num_int_register_writes 3281 # number of times the integer registers were written system.cpu.num_fp_register_reads 3 # number of times the floating registers were read system.cpu.num_fp_register_writes 1 # number of times the floating registers were written -system.cpu.num_mem_refs 2089 # number of memory refs -system.cpu.num_load_insts 1163 # Number of load instructions -system.cpu.num_store_insts 926 # Number of store instructions +system.cpu.num_mem_refs 2034 # number of memory refs +system.cpu.num_load_insts 1132 # Number of load instructions +system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 63266 # Number of busy cycles +system.cpu.num_busy_cycles 61804 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 915 # Number of branches fetched -system.cpu.op_class::No_OpClass 657 11.30% 11.30% # Class of executed instruction -system.cpu.op_class::IntAlu 3063 52.67% 63.97% # Class of executed instruction -system.cpu.op_class::IntMult 3 0.05% 64.02% # Class of executed instruction -system.cpu.op_class::IntDiv 1 0.02% 64.04% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 64.08% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.08% # Class of executed instruction -system.cpu.op_class::MemRead 1163 20.00% 84.08% # Class of executed instruction -system.cpu.op_class::MemWrite 926 15.92% 100.00% # Class of executed instruction +system.cpu.Branches 883 # Number of branches fetched +system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction +system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction +system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction +system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5815 # Class of executed instruction +system.cpu.op_class::total 5625 # Class of executed instruction system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 132.545353 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 5513 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 303 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.194719 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 129.108186 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 5331 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.071186 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 132.545353 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.064719 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.064719 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 290 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.141602 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 11935 # Number of tag accesses -system.cpu.icache.tags.data_accesses 11935 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 5513 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5513 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 5513 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5513 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 5513 # number of overall hits -system.cpu.icache.overall_hits::total 5513 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 303 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 303 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 303 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 303 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 303 # number of overall misses -system.cpu.icache.overall_misses::total 303 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16581000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16581000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16581000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16581000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16581000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16581000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5816 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5816 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5816 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5816 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5816 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5816 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052098 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.052098 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.052098 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.052098 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.052098 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.052098 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54722.772277 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54722.772277 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54722.772277 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54722.772277 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54722.772277 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54722.772277 # average overall miss latency +system.cpu.icache.tags.occ_blocks::cpu.inst 129.108186 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.063041 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063041 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 11547 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11547 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 5331 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5331 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 5331 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5331 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 5331 # number of overall hits +system.cpu.icache.overall_hits::total 5331 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 295 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 295 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 295 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 295 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 295 # number of overall misses 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-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994872 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994764 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.995465 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995370 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.995465 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995370 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency @@ -346,60 +346,60 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.492114 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1950 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.130435 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 86.158665 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.492114 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021360 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021360 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 114 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4314 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4314 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1076 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1076 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 874 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1950 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1950 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1950 # number of overall hits -system.cpu.dcache.overall_hits::total 1950 # number of overall hits +system.cpu.dcache.tags.occ_blocks::cpu.data 86.158665 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021035 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021035 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1045 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1045 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits +system.cpu.dcache.overall_hits::total 1896 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 51 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 51 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses -system.cpu.dcache.overall_misses::total 138 # number of overall misses +system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses +system.cpu.dcache.overall_misses::total 137 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2805000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2805000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2088 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074807 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.074807 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055135 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.055135 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.066092 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.066092 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.066092 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.066092 # miss rate for overall accesses +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2750000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2750000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7535000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7535000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7535000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7535000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076855 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076855 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency @@ -418,28 +418,28 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4611000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 4611000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2703000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2703000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2650000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2650000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7261000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7261000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7261000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7261000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency @@ -449,33 +449,33 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 390 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 390 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 606 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 882 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 382 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 590 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 864 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 27648 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 432 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 441 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 432 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 432 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 216000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 454500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 442500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 8d84a5cfe..b652069ee 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -305,7 +305,7 @@ system.cpu.fetch.Insts 13500 # Nu system.cpu.fetch.Branches 2332 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 880 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 3710 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 864 # Number of cycles fetch has spent squashing +system.cpu.fetch.SquashCycles 865 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 159 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR @@ -511,13 +511,13 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 4587 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 277 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11593 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.499612 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.370164 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11592 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.499655 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.370216 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9440 81.43% 81.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 839 7.24% 88.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 524 4.52% 93.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9439 81.43% 81.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 839 7.24% 88.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 524 4.52% 93.18% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 224 1.93% 95.12% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 167 1.44% 96.56% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 112 0.97% 97.52% # Number of insts commited each cycle @@ -527,7 +527,7 @@ system.cpu.commit.committed_per_cycle::8 111 0.96% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11593 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11592 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -575,8 +575,8 @@ system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # system.cpu.commit.op_class_0::total 5792 # Class of committed instruction system.cpu.commit.bw_lim_events 111 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21861 # The number of ROB reads -system.cpu.rob.rob_writes 21469 # The number of ROB writes +system.cpu.rob.rob_reads 21860 # The number of ROB reads +system.cpu.rob.rob_writes 21470 # The number of ROB writes system.cpu.timesIdled 245 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 25413 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated @@ -585,7 +585,7 @@ system.cpu.cpi 6.511740 # CP system.cpu.cpi_total 6.511740 # CPI: Total CPI of All Threads system.cpu.ipc 0.153569 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.153569 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13743 # number of integer regfile reads +system.cpu.int_regfile_reads 13744 # number of integer regfile reads system.cpu.int_regfile_writes 7176 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt index 080dd7c2e..d419dc80f 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -94,10 +94,10 @@ system.cpu.num_fp_register_writes 2 # nu system.cpu.num_mem_refs 2007 # number of memory refs system.cpu.num_load_insts 961 # Number of load instructions system.cpu.num_store_insts 1046 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5793 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 5792.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1037 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction system.cpu.op_class::IntAlu 3784 65.32% 65.32% # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt index e454f5068..b7a6e558a 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -76,10 +76,10 @@ system.cpu.num_fp_register_writes 0 # nu system.cpu.num_mem_refs 1401 # number of memory refs system.cpu.num_load_insts 723 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5390 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 5389.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1121 # Number of branches fetched system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index 0f04f9760..88154b71d 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -123,10 +123,10 @@ system.cpu.num_fp_register_writes 0 # nu system.cpu.num_mem_refs 1401 # number of memory refs system.cpu.num_load_insts 723 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 107952 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.num_idle_cycles 0.999991 # Number of idle cycles +system.cpu.num_busy_cycles 107951.000009 # Number of busy cycles +system.cpu.not_idle_fraction 0.999991 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000009 # Percentage of idle cycles system.cpu.Branches 1121 # Number of branches fetched system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index 706af6d1d..52edf7aee 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -72,10 +72,10 @@ system.cpu.num_fp_register_writes 0 # nu system.cpu.num_mem_refs 1401 # number of memory refs system.cpu.num_load_insts 723 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 55600 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 55599.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1121 # Number of branches fetched system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index a38f35e7a..83799ecfd 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -288,7 +288,7 @@ system.cpu.fetch.Insts 15528 # Nu system.cpu.fetch.Branches 3423 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 1111 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 9222 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1202 # Number of cycles fetch has spent squashing +system.cpu.fetch.SquashCycles 1203 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 54 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1088 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions @@ -491,11 +491,11 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 11720 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 588 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 19925 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.489184 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.394250 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 19924 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.489209 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.394281 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16685 83.74% 83.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16684 83.74% 83.74% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 1003 5.03% 88.77% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 547 2.75% 91.52% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 737 3.70% 95.22% # Number of insts commited each cycle @@ -507,7 +507,7 @@ system.cpu.commit.committed_per_cycle::8 260 1.30% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 19925 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 19924 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -555,8 +555,8 @@ system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # system.cpu.commit.op_class_0::total 9747 # Class of committed instruction system.cpu.commit.bw_lim_events 260 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 41132 # The number of ROB reads -system.cpu.rob.rob_writes 44928 # The number of ROB writes +system.cpu.rob.rob_reads 41131 # The number of ROB reads +system.cpu.rob.rob_writes 44929 # The number of ROB writes system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 17464 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated @@ -565,7 +565,7 @@ system.cpu.cpi 7.315428 # CP system.cpu.cpi_total 7.315428 # CPI: Total CPI of All Threads system.cpu.ipc 0.136697 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.136697 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 21340 # number of integer regfile reads +system.cpu.int_regfile_reads 21341 # number of integer regfile reads system.cpu.int_regfile_writes 13120 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads system.cpu.cc_regfile_reads 8069 # number of cc regfile reads diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index baff57318..3bcc97a18 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -85,10 +85,10 @@ system.cpu.num_cc_register_writes 3536 # nu system.cpu.num_mem_refs 1988 # number of memory refs system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 11231 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 11230.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index be3906efe..cdd2719ec 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -21,11 +21,11 @@ system.ruby.delayHist | 2750 100.00% 100.00% | system.ruby.delayHist::total 2750 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 8853 +system.ruby.outstanding_req_hist::samples 8852 system.ruby.outstanding_req_hist::mean 1 system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8853 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 8853 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8852 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 8852 system.ruby.latency_hist::bucket_size 16 system.ruby.latency_hist::max_bucket 159 system.ruby.latency_hist::samples 8852 @@ -126,10 +126,10 @@ system.cpu.num_cc_register_writes 3536 # nu system.cpu.num_mem_refs 1988 # number of memory refs system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 121759 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.num_idle_cycles 0.999992 # Number of idle cycles +system.cpu.num_busy_cycles 121758.000008 # Number of busy cycles +system.cpu.not_idle_fraction 0.999992 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000008 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 8118efe8c..b43d6cab2 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -77,10 +77,10 @@ system.cpu.num_cc_register_writes 3536 # nu system.cpu.num_mem_refs 1988 # number of memory refs system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 56716 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 56715.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction @@ -119,9 +119,9 @@ system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class::total 9748 # Class of executed instruction system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 105.550219 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 6637 # Total number of references to valid blocks. +system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 29.109649 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy @@ -130,14 +130,14 @@ system.cpu.icache.tags.occ_task_id_blocks::1024 228 system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 13958 # Number of tag accesses -system.cpu.icache.tags.data_accesses 13958 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6637 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 6637 # number of overall hits -system.cpu.icache.overall_hits::total 6637 # number of overall hits +system.cpu.icache.tags.tag_accesses 13956 # Number of tag accesses +system.cpu.icache.tags.data_accesses 13956 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 6636 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 6636 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 6636 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 6636 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 6636 # number of overall hits +system.cpu.icache.overall_hits::total 6636 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses @@ -150,18 +150,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 12498000 system.cpu.icache.demand_miss_latency::total 12498000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 12498000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 12498000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 6865 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6865 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 6865 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6865 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 6865 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6865 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.033212 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.033212 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.033212 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.033212 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.033212 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.033212 # miss rate for overall accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 6864 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 6864 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 6864 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.033217 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.033217 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.033217 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54815.789474 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 54815.789474 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency @@ -188,12 +188,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042000 system.cpu.icache.demand_mshr_miss_latency::total 12042000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033212 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.033212 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.033212 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency |