diff options
| author | Jason Lowe-Power <jason@lowepower.com> | 2016-11-30 17:12:59 -0500 |
|---|---|---|
| committer | Jason Lowe-Power <jason@lowepower.com> | 2016-11-30 17:12:59 -0500 |
| commit | 752033140228c790e51954bd8ccd3728f4dd7e08 (patch) | |
| tree | 3e3858dd900fed04d38cd331feadc140bec2e530 /tests/quick/se/00.hello/ref | |
| parent | 33683bd087c2009db588844e8fa89b454a5c3d77 (diff) | |
| download | gem5-752033140228c790e51954bd8ccd3728f4dd7e08.tar.xz | |
tests: Regression stats updated for recent patches
Diffstat (limited to 'tests/quick/se/00.hello/ref')
40 files changed, 12882 insertions, 981 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini index dc66b2c5c..2a35cf845 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -177,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -194,6 +194,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -206,15 +207,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=AlphaTLB @@ -292,10 +294,10 @@ pipelined=true [system.cpu.fuPool.FUList3] type=FUDesc -children=opList0 opList1 opList2 +children=opList0 opList1 opList2 opList3 opList4 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 [system.cpu.fuPool.FUList3.opList0] type=OpDesc @@ -307,11 +309,25 @@ pipelined=true [system.cpu.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 opClass=FloatDiv opLat=12 pipelined=false -[system.cpu.fuPool.FUList3.opList2] +[system.cpu.fuPool.FUList3.opList4] type=OpDesc eventq_index=0 opClass=FloatSqrt @@ -320,18 +336,25 @@ pipelined=false [system.cpu.fuPool.FUList4] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 -[system.cpu.fuPool.FUList4.opList] +[system.cpu.fuPool.FUList4.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 @@ -481,24 +504,31 @@ pipelined=true [system.cpu.fuPool.FUList6] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -[system.cpu.fuPool.FUList6.opList] +[system.cpu.fuPool.FUList6.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList7] type=FUDesc -children=opList0 opList1 +children=opList0 opList1 opList2 opList3 count=4 eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 [system.cpu.fuPool.FUList7.opList0] type=OpDesc @@ -514,6 +544,20 @@ opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList8] type=FUDesc children=opList @@ -535,10 +579,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -552,6 +596,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -564,15 +609,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=AlphaInterrupts @@ -595,10 +641,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -612,6 +658,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -624,15 +671,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -677,7 +725,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin kvmInSE=false diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index 27b942df1..06bbc9f54 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:49 -gem5 executing on e108600-lin, pid 28099 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/o3-timing +gem5 compiled Nov 29 2016 18:06:09 +gem5 started Nov 29 2016 18:06:29 +gem5 executing on zizzer, pid 27582 +command line: /z/powerjg/gem5-upstream/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 6cc52ba2c..3af1cbc4b 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000024 # Nu sim_ticks 23776000 # Number of ticks simulated final_tick 23776000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139405 # Simulator instruction rate (inst/s) -host_op_rate 139373 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 518883929 # Simulator tick rate (ticks/s) -host_mem_usage 254032 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 4743 # Simulator instruction rate (inst/s) +host_op_rate 4743 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17659718 # Simulator tick rate (ticks/s) +host_mem_usage 236044 # Number of bytes of host memory used +host_seconds 1.35 # Real time elapsed on the host sim_insts 6385 # Number of instructions simulated sim_ops 6385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 2 2.25% 87.64% # By system.physmem.bytesPerActivate::896-1023 1 1.12% 88.76% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 11.24% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 89 # Bytes accessed per row activation -system.physmem.totQLat 8009750 # Total ticks spent queuing -system.physmem.totMemAccLat 17103500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 8008750 # Total ticks spent queuing +system.physmem.totMemAccLat 17102500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2425000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16514.95 # Average queueing delay per DRAM burst +system.physmem.avgQLat 16512.89 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 35264.95 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 35262.89 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1305.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1305.52 # Average system read bandwidth in MiByte/s @@ -228,20 +228,20 @@ system.physmem_0.preEnergy 125235 # En system.physmem_0.readEnergy 1763580 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3005040 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 3004470 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 47520 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 7623180 # Energy for active power-down per rank (pJ) +system.physmem_0.actPowerDownEnergy 7623750 # Energy for active power-down per rank (pJ) system.physmem_0.prePowerDownEnergy 132480 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.physmem_0.totalEnergy 14783715 # Total energy per rank (pJ) system.physmem_0.averagePower 621.784975 # Core power per rank (mW) -system.physmem_0.totalIdleTime 16957250 # Total Idle time Per DRAM Rank +system.physmem_0.totalIdleTime 16958250 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 344500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5900500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 16710500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 5899500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 16711500 # Time in different power states system.physmem_1.actEnergy 399840 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 212520 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1699320 # Energy for read commands per rank (pJ) @@ -313,7 +313,7 @@ system.cpu.pwrStateResidencyTicks::ON 23776000 # Cu system.cpu.numCycles 47553 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8496 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 8498 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 16559 # Number of instructions fetch has processed system.cpu.fetch.Branches 2854 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken @@ -323,11 +323,11 @@ system.cpu.fetch.MiscStallCycles 22 # Nu system.cpu.fetch.PendingTrapStallCycles 656 # Number of stall cycles due to pending traps system.cpu.fetch.CacheLines 2295 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 335 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15456 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.071364 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.458774 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 15458 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.071225 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.458645 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 12470 80.68% 80.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 12472 80.68% 80.68% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 297 1.92% 82.60% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 230 1.49% 84.09% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 258 1.67% 85.76% # Number of instructions fetched each cycle (Total) @@ -339,10 +339,10 @@ system.cpu.fetch.rateDist::8 1247 8.07% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15456 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 15458 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.060017 # Number of branch fetches per cycle system.cpu.fetch.rate 0.348222 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8339 # Number of cycles decode is idle +system.cpu.decode.IdleCycles 8341 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 4008 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2446 # Number of cycles decode is running system.cpu.decode.UnblockCycles 214 # Number of cycles decode is unblocking @@ -352,7 +352,7 @@ system.cpu.decode.BranchMispred 75 # Nu system.cpu.decode.DecodedInsts 15004 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 221 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 449 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8498 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 8500 # Number of cycles rename is idle system.cpu.rename.BlockCycles 1841 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 655 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2476 # Number of cycles rename is running @@ -382,23 +382,23 @@ system.cpu.iq.iqSquashedInstsIssued 17 # Nu system.cpu.iq.iqSquashedInstsExamined 6695 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 3669 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15456 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.697205 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.442232 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15458 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.697115 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.442161 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11416 73.86% 73.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1297 8.39% 82.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11418 73.86% 73.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1297 8.39% 82.26% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 916 5.93% 88.18% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 681 4.41% 92.59% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 517 3.34% 95.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 347 2.25% 98.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 347 2.24% 98.18% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 200 1.29% 99.47% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 55 0.36% 99.83% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 27 0.17% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15456 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15458 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 21 14.89% 14.89% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 14.89% # attempts to use FU when none available @@ -479,7 +479,7 @@ system.cpu.iq.FU_type_0::total 10776 # Ty system.cpu.iq.rate 0.226610 # Inst issue rate system.cpu.iq.fu_busy_cnt 141 # FU busy when requested system.cpu.iq.fu_busy_rate 0.013085 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 37145 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 37147 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 19787 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 9745 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads @@ -530,11 +530,11 @@ system.cpu.iew.wb_fanout 0.733808 # av system.cpu.commit.commitSquashedInsts 6712 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 408 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14219 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.450243 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.361136 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 14221 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.450179 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.361050 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11792 82.93% 82.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11794 82.93% 82.93% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 1158 8.14% 91.08% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 469 3.30% 94.37% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 205 1.44% 95.82% # Number of insts commited each cycle @@ -546,7 +546,7 @@ system.cpu.commit.committed_per_cycle::8 192 1.35% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14219 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14221 # Number of insts commited each cycle system.cpu.commit.committedInsts 6402 # Number of instructions committed system.cpu.commit.committedOps 6402 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -597,10 +597,10 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 6402 # Class of committed instruction system.cpu.commit.bw_lim_events 192 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 26790 # The number of ROB reads +system.cpu.rob.rob_reads 26792 # The number of ROB reads system.cpu.rob.rob_writes 27482 # The number of ROB writes system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 32097 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 32095 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6385 # Number of Instructions Simulated system.cpu.committedOps 6385 # Number of Ops (including micro ops) Simulated system.cpu.cpi 7.447612 # CPI: Cycles Per Instruction @@ -753,12 +753,12 @@ system.cpu.icache.demand_misses::cpu.inst 458 # n system.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses system.cpu.icache.overall_misses::total 458 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 35507500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 35507500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 35507500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 35507500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 35507500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 35507500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 35506500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 35506500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 35506500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 35506500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 35506500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 35506500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2295 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2295 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2295 # number of demand (read+write) accesses @@ -771,12 +771,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.199564 system.cpu.icache.demand_miss_rate::total 0.199564 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.199564 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.199564 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77527.292576 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77527.292576 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77527.292576 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77527.292576 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77527.292576 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77527.292576 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77525.109170 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77525.109170 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77525.109170 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77525.109170 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77525.109170 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77525.109170 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 67 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -795,24 +795,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 313 system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26275500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26275500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26275500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26275500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26275500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 26275500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26274500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26274500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26274500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26274500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26274500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26274500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136383 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.136383 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.136383 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83947.284345 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83947.284345 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83947.284345 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 83947.284345 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83947.284345 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 83947.284345 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83944.089457 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83944.089457 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83944.089457 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 83944.089457 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83944.089457 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 83944.089457 # average overall mshr miss latency system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 270.818986 # Cycle average of tags in use @@ -852,16 +852,16 @@ system.cpu.l2cache.overall_misses::cpu.data 173 # system.cpu.l2cache.overall_misses::total 485 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6902500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 6902500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25792500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 25792500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25791500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 25791500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9241500 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 9241500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 25792500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 25791500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 16144000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 41936500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 25792500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 41935500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 25791500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 16144000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 41936500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 41935500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 313 # number of ReadCleanReq accesses(hits+misses) @@ -888,16 +888,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1 system.cpu.l2cache.overall_miss_rate::total 0.997942 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95868.055556 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95868.055556 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82668.269231 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82668.269231 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82665.064103 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82665.064103 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91500 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82668.269231 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82665.064103 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 86467.010309 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82668.269231 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86464.948454 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82665.064103 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 86467.010309 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86464.948454 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -918,16 +918,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 173 system.cpu.l2cache.overall_mshr_misses::total 485 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6182500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6182500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22672500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22672500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22671500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22671500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8231500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8231500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22672500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22671500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14414000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 37086500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22672500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 37085500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22671500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14414000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 37086500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 37085500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadCleanReq accesses @@ -942,16 +942,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85868.055556 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85868.055556 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72668.269231 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72668.269231 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72665.064103 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72665.064103 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81500 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72668.269231 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72665.064103 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76467.010309 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72668.269231 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76464.948454 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72665.064103 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76467.010309 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76464.948454 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 486 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index 4a82d75c8..3cdf3afd3 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -176,10 +176,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 @@ -193,6 +193,7 @@ response_latency=2 sequential_access=false size=32768 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=8 write_buffers=16 @@ -205,15 +206,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -316,38 +318,52 @@ pipelined=true [system.cpu.fuPool.FUList2] type=FUDesc -children=opList +children=opList0 opList1 count=1 eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 -[system.cpu.fuPool.FUList2.opList] +[system.cpu.fuPool.FUList2.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=2 pipelined=true +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=2 +pipelined=true + [system.cpu.fuPool.FUList3] type=FUDesc -children=opList +children=opList0 opList1 count=1 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 -[system.cpu.fuPool.FUList3.opList] +[system.cpu.fuPool.FUList3.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=2 pipelined=true +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=2 +pipelined=true + [system.cpu.fuPool.FUList4] type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 +opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27 [system.cpu.fuPool.FUList4.opList00] type=OpDesc @@ -479,7 +495,7 @@ pipelined=true type=OpDesc eventq_index=0 opClass=SimdFloatMultAcc -opLat=1 +opLat=5 pipelined=true [system.cpu.fuPool.FUList4.opList19] @@ -531,6 +547,20 @@ opClass=FloatMult opLat=4 pipelined=true +[system.cpu.fuPool.FUList4.opList26] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList4.opList27] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + [system.cpu.icache] type=Cache children=tags @@ -538,10 +568,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=1 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 @@ -555,6 +585,7 @@ response_latency=1 sequential_access=false size=32768 system=system +tag_latency=1 tags=system.cpu.icache.tags tgts_per_mshr=8 write_buffers=8 @@ -567,15 +598,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=1 default_p_state=UNDEFINED eventq_index=0 -hit_latency=1 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=32768 +tag_latency=1 [system.cpu.interrupts] type=ArmInterrupts @@ -670,10 +702,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +data_latency=12 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 @@ -687,6 +719,7 @@ response_latency=12 sequential_access=false size=1048576 system=system +tag_latency=12 tags=system.cpu.l2cache.tags tgts_per_mshr=8 write_buffers=8 @@ -729,15 +762,16 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=12 default_p_state=UNDEFINED eventq_index=0 -hit_latency=12 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=1048576 +tag_latency=12 [system.cpu.toL2Bus] type=CoherentXBar @@ -782,7 +816,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index 81299f400..d64ac9ed3 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:52:56 -gem5 executing on e108600-lin, pid 17478 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing +gem5 compiled Nov 29 2016 19:03:48 +gem5 started Nov 29 2016 19:06:55 +gem5 executing on zizzer, pid 5766 +command line: /z/powerjg/gem5-upstream/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 20299000 because target called exit() +Exiting @ tick 20302000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 613bc274a..307f14079 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20299000 # Number of ticks simulated -final_tick 20299000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20302000 # Number of ticks simulated +final_tick 20302000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 98455 # Simulator instruction rate (inst/s) -host_op_rate 115276 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 434998330 # Simulator tick rate (ticks/s) -host_mem_usage 266116 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 10367 # Simulator instruction rate (inst/s) +host_op_rate 12141 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45828431 # Simulator tick rate (ticks/s) +host_mem_usage 248616 # Number of bytes of host memory used +host_seconds 0.44 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 18560 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory @@ -24,16 +24,16 @@ system.physmem.num_reads::cpu.inst 290 # Nu system.physmem.num_reads::cpu.data 127 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory system.physmem.num_reads::total 444 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 914330755 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 400413813 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 85127346 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1399871915 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 914330755 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 914330755 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 914330755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 400413813 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 85127346 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1399871915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 914195646 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 400354645 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 85114767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1399665058 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 914195646 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 914195646 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 914195646 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 400354645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 85114767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1399665058 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 445 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 445 # Number of DRAM read bursts, including those serviced by the write queue @@ -80,7 +80,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20257500 # Total gap between requests +system.physmem.totGap 20260500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -96,9 +96,9 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see @@ -193,8 +193,8 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 435.612903 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 295.342416 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 353.563376 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 295.844737 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 352.802892 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 16 25.81% 38.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 10 16.13% 54.84% # Bytes accessed per row activation @@ -205,74 +205,74 @@ system.physmem.bytesPerActivate::768-895 2 3.23% 77.42% # By system.physmem.bytesPerActivate::896-1023 4 6.45% 83.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 16.13% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation -system.physmem.totQLat 6110750 # Total ticks spent queuing -system.physmem.totMemAccLat 14454500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 6124000 # Total ticks spent queuing +system.physmem.totMemAccLat 14467750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13732.02 # Average queueing delay per DRAM burst +system.physmem.avgQLat 13761.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32482.02 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1403.02 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32511.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1402.82 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1403.02 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1402.82 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 10.96 # Data bus utilization in percentage system.physmem.busUtilRead 10.96 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.84 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 373 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45522.47 # Average gap between requests +system.physmem.avgGap 45529.21 # Average gap between requests system.physmem.pageHitRate 83.82 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 349860 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 170775 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2334780 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3572760 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 3561360 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 28800 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5648700 # Energy for active power-down per rank (pJ) +system.physmem_0.actPowerDownEnergy 5661240 # Energy for active power-down per rank (pJ) system.physmem_0.prePowerDownEnergy 960 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 13335915 # Total energy per rank (pJ) -system.physmem_0.averagePower 656.941626 # Core power per rank (mW) -system.physmem_0.totalIdleTime 12232500 # Total Idle time Per DRAM Rank +system.physmem_0.totalEnergy 13337055 # Total energy per rank (pJ) +system.physmem_0.averagePower 656.916882 # Core power per rank (mW) +system.physmem_0.totalIdleTime 12272000 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 19000 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 2500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7376750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 12380750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7340250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 12420250 # Time in different power states system.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 64515 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 842520 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1468320 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 69120 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 7424250 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 237600 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actBackEnergy 1479720 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 68640 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 7413420 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 238560 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 11499825 # Total energy per rank (pJ) -system.physmem_1.averagePower 566.493842 # Core power per rank (mW) -system.physmem_1.totalIdleTime 16895250 # Total Idle time Per DRAM Rank +system.physmem_1.totalEnergy 11500875 # Total energy per rank (pJ) +system.physmem_1.averagePower 566.475803 # Core power per rank (mW) +system.physmem_1.totalIdleTime 16880000 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 110000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 618500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2773750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 16276750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2441 # Number of BP lookups -system.cpu.branchPred.condPredicted 1444 # Number of conditional branches predicted +system.physmem_1.memoryStateTime::PRE_PDN 620500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2792000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 16259500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 2438 # Number of BP lookups +system.cpu.branchPred.condPredicted 1442 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 522 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 916 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 915 # Number of BTB lookups system.cpu.branchPred.BTBHits 449 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 49.017467 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 49.071038 # BTB Hit Percentage system.cpu.branchPred.usedRAS 286 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 163 # Number of indirect predictor lookups. @@ -280,7 +280,7 @@ system.cpu.branchPred.indirectHits 13 # Nu system.cpu.branchPred.indirectMisses 150 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 59 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -310,7 +310,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -340,7 +340,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -370,7 +370,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -401,85 +401,85 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 20299000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 40599 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 20302000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 40605 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6170 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11468 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2441 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 6160 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11461 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2438 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 748 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 8322 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 8317 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1087 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 161 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.MiscStallCycles 162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 286 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 434 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3907 # Number of cache lines fetched +system.cpu.fetch.IcacheWaitRetryStallCycles 447 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 3903 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 179 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15916 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.856748 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.206522 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 15915 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.856236 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.206395 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9525 59.85% 59.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2508 15.76% 75.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 521 3.27% 78.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3362 21.12% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9529 59.87% 59.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2505 15.74% 75.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 521 3.27% 78.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3360 21.11% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15916 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.060125 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.282470 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5812 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4409 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5179 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 15915 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.060042 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.282256 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5815 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4410 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5174 # Number of cycles decode is running system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 384 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 374 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 10178 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1683 # Number of squashed instructions handled by decode +system.cpu.decode.DecodedInsts 10174 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1674 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 384 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6925 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 6926 # Number of cycles rename is idle system.cpu.rename.BlockCycles 1165 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 2515 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4188 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 739 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 9100 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 467 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 24 # Number of times rename has blocked due to ROB full +system.cpu.rename.RunCycles 4185 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 740 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 9093 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 464 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 25 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 631 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9458 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 41150 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10006 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 9451 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 41117 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9997 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3964 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3957 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 29 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 330 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1823 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1289 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 332 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1821 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1286 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8513 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8508 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7228 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 182 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3173 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8254 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 7222 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 185 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3168 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8232 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15916 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.454134 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.844472 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.453786 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.844098 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11653 73.22% 73.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1992 12.52% 85.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1620 10.18% 95.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 608 3.82% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 43 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11657 73.25% 73.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1985 12.47% 85.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1624 10.20% 95.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 607 3.81% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 42 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -487,101 +487,101 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15916 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15915 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 416 28.75% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 475 32.83% 61.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 539 37.25% 98.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 98.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 17 1.17% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 415 28.86% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 468 32.55% 61.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 538 37.41% 98.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 98.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 17 1.18% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4533 62.71% 62.71% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1605 22.21% 85.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1066 14.75% 99.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4533 62.77% 62.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1600 22.15% 85.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1065 14.75% 99.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 16 0.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7228 # Type of FU issued -system.cpu.iq.rate 0.178034 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1447 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.200194 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31952 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11715 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6617 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 7222 # Type of FU issued +system.cpu.iq.rate 0.177860 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1438 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.199114 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31933 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11705 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 6615 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 49 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8642 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8627 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 33 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 12 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 796 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 794 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 351 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 348 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled @@ -590,10 +590,10 @@ system.cpu.iew.iewIdleCycles 0 # Nu system.cpu.iew.iewSquashCycles 384 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 345 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 8564 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 8559 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1823 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1289 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 1821 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1286 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall @@ -601,41 +601,41 @@ system.cpu.iew.memOrderViolationEvents 7 # Nu system.cpu.iew.predictedTakenIncorrect 60 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 318 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6821 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1422 # Number of load instructions executed +system.cpu.iew.iewExecutedInsts 6815 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1418 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 407 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 13 # number of nop insts executed -system.cpu.iew.exec_refs 2447 # number of memory reference insts executed -system.cpu.iew.exec_branches 1298 # Number of branches executed -system.cpu.iew.exec_stores 1025 # Number of stores executed -system.cpu.iew.exec_rate 0.168009 # Inst execution rate -system.cpu.iew.wb_sent 6677 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6633 # cumulative count of insts written-back +system.cpu.iew.exec_refs 2442 # number of memory reference insts executed +system.cpu.iew.exec_branches 1297 # Number of branches executed +system.cpu.iew.exec_stores 1024 # Number of stores executed +system.cpu.iew.exec_rate 0.167836 # Inst execution rate +system.cpu.iew.wb_sent 6675 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6631 # cumulative count of insts written-back system.cpu.iew.wb_producers 2981 # num instructions producing a value -system.cpu.iew.wb_consumers 5419 # num instructions consuming a value -system.cpu.iew.wb_rate 0.163378 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.550101 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 2706 # The number of squashed insts skipped by commit +system.cpu.iew.wb_consumers 5426 # num instructions consuming a value +system.cpu.iew.wb_rate 0.163305 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.549392 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 2701 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 363 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 15349 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.350381 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 0.988718 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 15348 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.350404 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.989339 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 12681 82.62% 82.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1407 9.17% 91.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 599 3.90% 95.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 298 1.94% 97.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 170 1.11% 98.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 79 0.51% 99.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 44 0.29% 99.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 28 0.18% 99.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 43 0.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 12680 82.62% 82.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1404 9.15% 91.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 606 3.95% 95.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 298 1.94% 97.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 164 1.07% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 80 0.52% 99.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 44 0.29% 99.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 28 0.18% 99.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 44 0.29% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 15349 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 15348 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -685,53 +685,53 @@ system.cpu.commit.op_class_0::FloatMemWrite 16 0.30% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction -system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 23233 # The number of ROB reads -system.cpu.rob.rob_writes 16740 # The number of ROB writes -system.cpu.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24683 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 44 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 23226 # The number of ROB reads +system.cpu.rob.rob_writes 16730 # The number of ROB writes +system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 24690 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.841246 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.841246 # CPI: Total CPI of All Threads -system.cpu.ipc 0.113106 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.113106 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6772 # number of integer regfile reads -system.cpu.int_regfile_writes 3788 # number of integer regfile writes +system.cpu.cpi 8.842552 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.842552 # CPI: Total CPI of All Threads +system.cpu.ipc 0.113090 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.113090 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 6765 # number of integer regfile reads +system.cpu.int_regfile_writes 3787 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 24220 # number of cc regfile reads +system.cpu.cc_regfile_reads 24202 # number of cc regfile reads system.cpu.cc_regfile_writes 2924 # number of cc regfile writes -system.cpu.misc_regfile_reads 2559 # number of misc regfile reads +system.cpu.misc_regfile_reads 2558 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.063183 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1930 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 84.060908 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1926 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.496503 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.468531 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.063183 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.164186 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.164186 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.060908 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.164181 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.164181 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4723 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4723 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1188 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1188 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4715 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4715 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 1184 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1184 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1910 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1910 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1910 # number of overall hits -system.cpu.dcache.overall_hits::total 1910 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1906 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1906 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1906 # number of overall hits +system.cpu.dcache.overall_hits::total 1906 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses @@ -742,48 +742,48 @@ system.cpu.dcache.demand_misses::cpu.data 358 # n system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses system.cpu.dcache.overall_misses::total 358 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12032500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12032500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8019500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8019500 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12046500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12046500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8016500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8016500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 139000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 139000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20052000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20052000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20052000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20052000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1355 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1355 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 20063000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20063000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20063000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20063000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1351 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1351 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2268 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2268 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2268 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2268 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123247 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.123247 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2264 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2264 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2264 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2264 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123612 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.123612 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.157848 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.157848 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.157848 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.157848 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72050.898204 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72050.898204 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41986.910995 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41986.910995 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.158127 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.158127 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.158127 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.158127 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72134.730539 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72134.730539 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41971.204188 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41971.204188 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56011.173184 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56011.173184 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56011.173184 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56011.173184 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56041.899441 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56041.899441 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56041.899441 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56041.899441 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 853 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -810,88 +810,88 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 144 system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7984500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7984500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2595500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2595500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10580000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10580000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10580000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10580000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076015 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076015 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7999500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7999500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2594500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2594500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10594000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10594000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10594000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10594000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076240 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076240 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063492 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063492 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77519.417476 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77519.417476 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63304.878049 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63304.878049 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73472.222222 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73472.222222 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73472.222222 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73472.222222 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063604 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063604 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063604 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063604 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77665.048544 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77665.048544 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63280.487805 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63280.487805 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73569.444444 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73569.444444 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73569.444444 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73569.444444 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 44 # number of replacements -system.cpu.icache.tags.tagsinuse 137.515573 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3540 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 137.464664 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3536 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.839465 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.826087 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 137.515573 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.268585 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.268585 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 137.464664 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.268486 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.268486 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 255 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 8109 # Number of tag accesses -system.cpu.icache.tags.data_accesses 8109 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 3540 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3540 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3540 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3540 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3540 # number of overall hits -system.cpu.icache.overall_hits::total 3540 # number of overall hits +system.cpu.icache.tags.tag_accesses 8101 # Number of tag accesses +system.cpu.icache.tags.data_accesses 8101 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 3536 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3536 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3536 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3536 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3536 # number of overall hits +system.cpu.icache.overall_hits::total 3536 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25051490 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25051490 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25051490 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25051490 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25051490 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25051490 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3905 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3905 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3905 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3905 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3905 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3905 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093470 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.093470 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.093470 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.093470 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.093470 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.093470 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68634.219178 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68634.219178 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68634.219178 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68634.219178 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68634.219178 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68634.219178 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 9850 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25043490 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25043490 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25043490 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25043490 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25043490 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25043490 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 3901 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 3901 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 3901 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 3901 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 3901 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093566 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.093566 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.093566 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.093566 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.093566 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.093566 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68612.301370 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68612.301370 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68612.301370 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68612.301370 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68612.301370 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68612.301370 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 9833 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 47 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 96 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 97 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 102.604167 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 101.371134 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 44 # number of writebacks system.cpu.icache.writebacks::total 44 # number of writebacks @@ -907,40 +907,40 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 299 system.cpu.icache.demand_mshr_misses::total 299 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 299 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22011990 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22011990 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22011990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22011990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22011990 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22011990 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076569 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076569 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076569 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.076569 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076569 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.076569 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73618.695652 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73618.695652 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73618.695652 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73618.695652 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73618.695652 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73618.695652 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22004990 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22004990 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22004990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22004990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22004990 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22004990 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076647 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.076647 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.076647 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73595.284281 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73595.284281 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73595.284281 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73595.284281 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73595.284281 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73595.284281 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 17.353048 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 17.355508 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 41 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.073171 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9.225603 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.127445 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 9.226998 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.128510 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000563 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000496 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.001059 # Average percentage of cache occupancy @@ -954,7 +954,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000793 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.001709 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 7676 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 7676 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits @@ -979,18 +979,18 @@ system.cpu.l2cache.demand_misses::total 424 # nu system.cpu.l2cache.overall_misses::cpu.inst 291 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 133 # number of overall misses system.cpu.l2cache.overall_misses::total 424 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2461000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2461000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21652500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 21652500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7825000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7825000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21652500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10286000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31938500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21652500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10286000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31938500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2460000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2460000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21645500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 21645500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7838000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7838000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21645500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10298000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31943500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21645500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10298000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31943500 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) @@ -1017,18 +1017,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.957111 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.973244 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.923611 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.957111 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82033.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82033.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74407.216495 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74407.216495 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75970.873786 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75970.873786 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74407.216495 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77338.345865 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75326.650943 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74407.216495 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77338.345865 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75326.650943 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82000 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74383.161512 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74383.161512 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76097.087379 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76097.087379 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74383.161512 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77428.571429 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75338.443396 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74383.161512 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77428.571429 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75338.443396 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1062,19 +1062,19 @@ system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 53 system.cpu.l2cache.overall_mshr_misses::total 471 # number of overall MSHR misses system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1766926 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1766926 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2281000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2281000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19850000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19850000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6909500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6909500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19850000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9190500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29040500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19850000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9190500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2280000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2280000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19843000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19843000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6922500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6922500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19843000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9202500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29045500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19843000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9202500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1766926 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30807426 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30812426 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses @@ -1092,26 +1092,26 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf system.cpu.l2cache.overall_mshr_miss_rate::total 1.063205 # mshr miss rate for overall accesses system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415 # average HardPFReq mshr miss latency system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33338.226415 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76033.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76033.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68448.275862 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68448.275862 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70505.102041 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70505.102041 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68448.275862 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71800.781250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69474.880383 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68448.275862 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71800.781250 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68424.137931 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68424.137931 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70637.755102 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70637.755102 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68424.137931 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71894.531250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69486.842105 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68424.137931 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71894.531250 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65408.547771 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65419.163482 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 26 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 24 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 45 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution @@ -1150,7 +1150,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 414 # Transaction distribution system.membus.trans_dist::ReadExReq 30 # Transaction distribution system.membus.trans_dist::ReadExResp 30 # Transaction distribution @@ -1171,9 +1171,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 445 # Request fanout histogram -system.membus.reqLayer0.occupancy 564444 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 2334750 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 554444 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 2338000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 11.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini index 1e3a930b1..8fa043fc0 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini @@ -177,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -194,6 +194,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -206,15 +207,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=MipsTLB @@ -292,10 +294,10 @@ pipelined=true [system.cpu.fuPool.FUList3] type=FUDesc -children=opList0 opList1 opList2 +children=opList0 opList1 opList2 opList3 opList4 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 [system.cpu.fuPool.FUList3.opList0] type=OpDesc @@ -307,11 +309,25 @@ pipelined=true [system.cpu.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 opClass=FloatDiv opLat=12 pipelined=false -[system.cpu.fuPool.FUList3.opList2] +[system.cpu.fuPool.FUList3.opList4] type=OpDesc eventq_index=0 opClass=FloatSqrt @@ -320,18 +336,25 @@ pipelined=false [system.cpu.fuPool.FUList4] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 -[system.cpu.fuPool.FUList4.opList] +[system.cpu.fuPool.FUList4.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 @@ -481,24 +504,31 @@ pipelined=true [system.cpu.fuPool.FUList6] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -[system.cpu.fuPool.FUList6.opList] +[system.cpu.fuPool.FUList6.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList7] type=FUDesc -children=opList0 opList1 +children=opList0 opList1 opList2 opList3 count=4 eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 [system.cpu.fuPool.FUList7.opList0] type=OpDesc @@ -514,6 +544,20 @@ opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList8] type=FUDesc children=opList @@ -535,10 +579,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -552,6 +596,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -564,15 +609,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=MipsInterrupts @@ -597,10 +643,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -614,6 +660,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -626,15 +673,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -679,7 +727,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/mips/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin kvmInSE=false diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index fa28c822f..b75343836 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timin gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 13 2016 20:36:34 -gem5 started Oct 13 2016 20:36:59 -gem5 executing on e108600-lin, pid 36840 -command line: /work/curdun01/gem5-external.hg/build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/mips/linux/o3-timing +gem5 compiled Nov 29 2016 18:13:44 +gem5 started Nov 29 2016 18:14:01 +gem5 executing on zizzer, pid 32698 +command line: /z/powerjg/gem5-upstream/build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 10245d965..888fdd0d2 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000024 # Nu sim_ticks 24405000 # Number of ticks simulated final_tick 24405000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123007 # Simulator instruction rate (inst/s) -host_op_rate 122970 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 600170719 # Simulator tick rate (ticks/s) -host_mem_usage 251144 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 38911 # Simulator instruction rate (inst/s) +host_op_rate 38904 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 189891987 # Simulator tick rate (ticks/s) +host_mem_usage 234100 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 4999 # Number of instructions simulated sim_ops 4999 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 4 3.51% 93.86% # By system.physmem.bytesPerActivate::896-1023 3 2.63% 96.49% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 4 3.51% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 114 # Bytes accessed per row activation -system.physmem.totQLat 7578250 # Total ticks spent queuing -system.physmem.totMemAccLat 16372000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 7577250 # Total ticks spent queuing +system.physmem.totMemAccLat 16371000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16158.32 # Average queueing delay per DRAM burst +system.physmem.avgQLat 16156.18 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34908.32 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 34906.18 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1229.91 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1229.91 # Average system read bandwidth in MiByte/s @@ -229,9 +229,9 @@ system.physmem_0.readEnergy 756840 # En system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 1602840 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 46080 # Energy for precharge background per rank (pJ) +system.physmem_0.preBackEnergy 46560 # Energy for precharge background per rank (pJ) system.physmem_0.actPowerDownEnergy 8339100 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 953280 # Energy for precharge power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 952800 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.physmem_0.totalEnergy 13833510 # Total energy per rank (pJ) system.physmem_0.averagePower 566.830977 # Core power per rank (mW) @@ -239,9 +239,9 @@ system.physmem_0.totalIdleTime 20709000 # To system.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 2481750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 2481250 # Time in different power states system.physmem_0.memoryStateTime::ACT 2828750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 18291000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 18291500 # Time in different power states system.physmem_1.actEnergy 642600 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 333960 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 2591820 # Energy for read commands per rank (pJ) @@ -299,7 +299,7 @@ system.cpu.pwrStateResidencyTicks::ON 24405000 # Cu system.cpu.numCycles 48811 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 9089 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 9088 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 13001 # Number of instructions fetch has processed system.cpu.fetch.Branches 2188 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 841 # Number of branches that fetch has predicted taken @@ -308,11 +308,11 @@ system.cpu.fetch.SquashCycles 868 # Nu system.cpu.fetch.PendingTrapStallCycles 205 # Number of stall cycles due to pending traps system.cpu.fetch.CacheLines 2050 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15175 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.856738 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.144886 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 15174 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.856795 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.144946 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11815 77.86% 77.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11814 77.86% 77.86% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 1507 9.93% 87.79% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 111 0.73% 88.52% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 162 1.07% 89.59% # Number of instructions fetched each cycle (Total) @@ -324,11 +324,11 @@ system.cpu.fetch.rateDist::8 903 5.95% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15175 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 15174 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.044826 # Number of branch fetches per cycle system.cpu.fetch.rate 0.266354 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 8420 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3451 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 3450 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2768 # Number of cycles decode is running system.cpu.decode.UnblockCycles 142 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 394 # Number of cycles decode is squashing @@ -338,7 +338,7 @@ system.cpu.decode.DecodedInsts 12000 # Nu system.cpu.decode.SquashedInsts 160 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 394 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 8571 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 621 # Number of cycles rename is blocking +system.cpu.rename.BlockCycles 620 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 1023 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2740 # Number of cycles rename is running system.cpu.rename.UnblockCycles 1826 # Number of cycles rename is unblocking @@ -356,25 +356,25 @@ system.cpu.rename.UndoneMaps 3635 # Nu system.cpu.rename.serializingInsts 13 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 323 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2470 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1160 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2468 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9019 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9014 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8119 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8118 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4030 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2019 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 4025 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2012 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15175 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.535025 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.265920 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15174 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.534994 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.265800 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11852 78.10% 78.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1334 8.79% 86.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 728 4.80% 91.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 454 2.99% 94.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11850 78.09% 78.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1336 8.80% 86.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 728 4.80% 91.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 453 2.99% 94.68% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 341 2.25% 96.93% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 284 1.87% 98.80% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 110 0.72% 99.53% # Number of insts issued each cycle @@ -383,7 +383,7 @@ system.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15175 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15174 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 6 3.33% 3.33% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.33% # attempts to use FU when none available @@ -423,73 +423,73 @@ system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4775 58.81% 58.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2274 28.01% 86.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4775 58.82% 58.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2273 28.00% 86.91% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1063 13.09% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8119 # Type of FU issued -system.cpu.iq.rate 0.166335 # Inst issue rate +system.cpu.iq.FU_type_0::total 8118 # Type of FU issued +system.cpu.iq.rate 0.166315 # Inst issue rate system.cpu.iq.fu_busy_cnt 180 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022170 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31608 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 13067 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7338 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.022173 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31605 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 13057 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7337 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8297 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8296 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1335 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1333 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 259 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 257 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 394 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 491 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 490 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 74 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10629 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 10621 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 154 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2470 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1160 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2468 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 75 # Number of times the LSQ has become full, causing a stall @@ -497,22 +497,22 @@ system.cpu.iew.memOrderViolationEvents 10 # Nu system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 338 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 439 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7792 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2130 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 327 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7790 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2129 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 328 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1599 # number of nop insts executed -system.cpu.iew.exec_refs 3179 # number of memory reference insts executed -system.cpu.iew.exec_branches 1364 # Number of branches executed +system.cpu.iew.exec_nop 1596 # number of nop insts executed +system.cpu.iew.exec_refs 3178 # number of memory reference insts executed +system.cpu.iew.exec_branches 1363 # Number of branches executed system.cpu.iew.exec_stores 1049 # Number of stores executed -system.cpu.iew.exec_rate 0.159636 # Inst execution rate -system.cpu.iew.wb_sent 7433 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7340 # cumulative count of insts written-back +system.cpu.iew.exec_rate 0.159595 # Inst execution rate +system.cpu.iew.wb_sent 7432 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7339 # cumulative count of insts written-back system.cpu.iew.wb_producers 2867 # num instructions producing a value -system.cpu.iew.wb_consumers 4275 # num instructions consuming a value -system.cpu.iew.wb_rate 0.150376 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.670643 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4990 # The number of squashed insts skipped by commit +system.cpu.iew.wb_consumers 4274 # num instructions consuming a value +system.cpu.iew.wb_rate 0.150355 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.670800 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 4982 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 384 # The number of times a branch was mispredicted system.cpu.commit.committed_per_cycle::samples 14293 # Number of insts commited each cycle @@ -582,46 +582,46 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5640 # Class of committed instruction system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 24808 # The number of ROB reads -system.cpu.rob.rob_writes 22150 # The number of ROB writes +system.cpu.rob.rob_reads 24800 # The number of ROB reads +system.cpu.rob.rob_writes 22133 # The number of ROB writes system.cpu.timesIdled 264 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 33636 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 33637 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4999 # Number of Instructions Simulated system.cpu.committedOps 4999 # Number of Ops (including micro ops) Simulated system.cpu.cpi 9.764153 # CPI: Cycles Per Instruction system.cpu.cpi_total 9.764153 # CPI: Total CPI of All Threads system.cpu.ipc 0.102415 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.102415 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10563 # number of integer regfile reads +system.cpu.int_regfile_reads 10560 # number of integer regfile reads system.cpu.int_regfile_writes 5141 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 161 # number of misc regfile reads system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 91.114118 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2396 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 91.114159 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.114286 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.107143 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 91.114118 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 91.114159 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.022245 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.022245 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5954 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5954 # Number of data accesses +system.cpu.dcache.tags.tag_accesses 5952 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5952 # Number of data accesses system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1839 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1839 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 1838 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1838 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 557 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 557 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2396 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2396 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2396 # number of overall hits -system.cpu.dcache.overall_hits::total 2396 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits +system.cpu.dcache.overall_hits::total 2395 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 344 # number of WriteReq misses @@ -630,38 +630,38 @@ system.cpu.dcache.demand_misses::cpu.data 511 # n system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses system.cpu.dcache.overall_misses::total 511 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12711500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12711500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12709500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12709500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 34219499 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 34219499 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46930999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46930999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46930999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46930999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2006 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2006 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 46928999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46928999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46928999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46928999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2005 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2005 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2907 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2907 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2907 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2907 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083250 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.083250 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2906 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2906 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2906 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2906 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083292 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.083292 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381798 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.381798 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.175783 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.175783 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.175783 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.175783 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76116.766467 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 76116.766467 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.175843 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.175843 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.175843 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.175843 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76104.790419 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76104.790419 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99475.287791 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 99475.287791 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 91841.485323 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 91841.485323 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 91841.485323 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 91841.485323 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 91837.571429 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 91837.571429 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 91837.571429 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 91837.571429 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 636 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked @@ -684,30 +684,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 140 system.cpu.dcache.demand_mshr_misses::total 140 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 140 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8095000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8095000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8094500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8094500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4915999 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4915999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13010999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13010999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13010999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13010999 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044865 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044865 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13010499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13010499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13010499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13010499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044888 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044888 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048160 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048160 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048160 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048160 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89944.444444 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89944.444444 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048176 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048176 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048176 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048176 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89938.888889 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89938.888889 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98319.980000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98319.980000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 92935.707143 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 92935.707143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 92935.707143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 92935.707143 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 92932.135714 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 92932.135714 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 92932.135714 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 92932.135714 # average overall mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 17 # number of replacements system.cpu.icache.tags.tagsinuse 160.115290 # Cycle average of tags in use @@ -781,33 +781,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 332 system.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28113000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 28113000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28113000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 28113000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28113000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 28113000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28112000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 28112000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28112000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 28112000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28112000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 28112000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161951 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.161951 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.161951 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84677.710843 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84677.710843 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84677.710843 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 84677.710843 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84677.710843 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 84677.710843 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84674.698795 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84674.698795 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84674.698795 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 84674.698795 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84674.698795 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 84674.698795 # average overall mshr miss latency system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 253.317608 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 253.317649 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 469 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.042644 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::cpu.inst 162.143256 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 91.174352 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 91.174392 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004948 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.002782 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.007731 # Average percentage of cache occupancy @@ -840,16 +840,16 @@ system.cpu.l2cache.overall_misses::cpu.data 140 # system.cpu.l2cache.overall_misses::total 469 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4840000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4840000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27582000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 27582000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7957000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7957000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27582000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12797000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 40379000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27582000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12797000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 40379000 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27581000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 27581000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7956500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7956500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27581000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12796500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 40377500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27581000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12796500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 40377500 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) @@ -878,16 +878,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1 system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96800 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96800 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83835.866261 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83835.866261 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88411.111111 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88411.111111 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83835.866261 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91407.142857 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 86095.948827 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83835.866261 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91407.142857 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 86095.948827 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83832.826748 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83832.826748 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88405.555556 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88405.555556 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83832.826748 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91403.571429 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86092.750533 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83832.826748 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91403.571429 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86092.750533 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -908,16 +908,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 140 system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4340000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4340000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24292000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24292000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7057000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7057000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24292000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11397000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 35689000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24292000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11397000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 35689000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24291000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24291000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7056500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7056500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24291000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11396500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 35687500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24291000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11396500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 35687500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for ReadCleanReq accesses @@ -932,16 +932,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86800 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86800 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73835.866261 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73835.866261 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78411.111111 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78411.111111 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73835.866261 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81407.142857 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76095.948827 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73835.866261 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81407.142857 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76095.948827 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73832.826748 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73832.826748 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78405.555556 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78405.555556 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73832.826748 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81403.571429 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76092.750533 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73832.826748 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81403.571429 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76092.750533 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -1007,7 +1007,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 469 # Request fanout histogram -system.membus.reqLayer0.occupancy 581500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 581000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) system.membus.respLayer1.occupancy 2488500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 10.2 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini index 08a1c6669..70198a6d7 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini @@ -178,10 +178,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -195,6 +195,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -207,15 +208,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=PowerTLB @@ -293,10 +295,10 @@ pipelined=true [system.cpu.fuPool.FUList3] type=FUDesc -children=opList0 opList1 opList2 +children=opList0 opList1 opList2 opList3 opList4 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 [system.cpu.fuPool.FUList3.opList0] type=OpDesc @@ -308,11 +310,25 @@ pipelined=true [system.cpu.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 opClass=FloatDiv opLat=12 pipelined=false -[system.cpu.fuPool.FUList3.opList2] +[system.cpu.fuPool.FUList3.opList4] type=OpDesc eventq_index=0 opClass=FloatSqrt @@ -321,18 +337,25 @@ pipelined=false [system.cpu.fuPool.FUList4] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 -[system.cpu.fuPool.FUList4.opList] +[system.cpu.fuPool.FUList4.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 @@ -482,24 +505,31 @@ pipelined=true [system.cpu.fuPool.FUList6] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -[system.cpu.fuPool.FUList6.opList] +[system.cpu.fuPool.FUList6.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList7] type=FUDesc -children=opList0 opList1 +children=opList0 opList1 opList2 opList3 count=4 eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 [system.cpu.fuPool.FUList7.opList0] type=OpDesc @@ -515,6 +545,20 @@ opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList8] type=FUDesc children=opList @@ -536,10 +580,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -553,6 +597,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -565,15 +610,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=PowerInterrupts @@ -595,10 +641,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -612,6 +658,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -624,15 +671,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -677,7 +725,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/power/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello gid=100 input=cin kvmInSE=false diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index 7df757697..5b262649f 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 13 2016 20:40:28 -gem5 started Oct 13 2016 20:40:51 -gem5 executing on e108600-lin, pid 9917 -command line: /work/curdun01/gem5-external.hg/build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/power/linux/o3-timing +gem5 compiled Nov 29 2016 18:37:43 +gem5 started Nov 29 2016 18:37:59 +gem5 executing on zizzer, pid 53433 +command line: /z/powerjg/gem5-upstream/build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index fbc31e89b..1c774fd71 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 21268000 # Number of ticks simulated final_tick 21268000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133148 # Simulator instruction rate (inst/s) -host_op_rate 133114 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 488684971 # Simulator tick rate (ticks/s) -host_mem_usage 249832 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 49400 # Simulator instruction rate (inst/s) +host_op_rate 49392 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 181337178 # Simulator tick rate (ticks/s) +host_mem_usage 231948 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -299,7 +299,7 @@ system.cpu.pwrStateResidencyTicks::ON 21268000 # Cu system.cpu.numCycles 42537 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7672 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 7674 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 13369 # Number of instructions fetch has processed system.cpu.fetch.Branches 2411 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 939 # Number of branches that fetch has predicted taken @@ -310,26 +310,26 @@ system.cpu.fetch.PendingTrapStallCycles 146 # Nu system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 1861 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 290 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12418 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.076582 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.475981 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 12420 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.076409 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.475819 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10084 81.20% 81.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10086 81.21% 81.21% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 166 1.34% 82.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 214 1.72% 84.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 214 1.72% 84.27% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 147 1.18% 85.45% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 241 1.94% 87.39% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 150 1.21% 88.60% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 280 2.25% 90.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 148 1.19% 92.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 988 7.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 148 1.19% 92.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 988 7.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12418 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 12420 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.056680 # Number of branch fetches per cycle system.cpu.fetch.rate 0.314291 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7245 # Number of cycles decode is idle +system.cpu.decode.IdleCycles 7247 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 2821 # Number of cycles decode is blocked system.cpu.decode.RunCycles 1946 # Number of cycles decode is running system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking @@ -339,7 +339,7 @@ system.cpu.decode.BranchMispred 149 # Nu system.cpu.decode.DecodedInsts 11479 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 451 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 276 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7413 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 7415 # Number of cycles rename is idle system.cpu.rename.BlockCycles 800 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 463 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 1897 # Number of cycles rename is running @@ -368,11 +368,11 @@ system.cpu.iq.iqSquashedInstsIssued 53 # Nu system.cpu.iq.iqSquashedInstsExamined 4442 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 3474 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12418 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.709293 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.511827 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12420 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.709179 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.511732 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9303 74.92% 74.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9305 74.92% 74.92% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 969 7.80% 82.72% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 656 5.28% 88.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 462 3.72% 91.72% # Number of insts issued each cycle @@ -384,7 +384,7 @@ system.cpu.iq.issued_per_cycle::8 30 0.24% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12418 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12420 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 12 6.06% 6.06% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 6.06% # attempts to use FU when none available @@ -465,7 +465,7 @@ system.cpu.iq.FU_type_0::total 8808 # Ty system.cpu.iq.rate 0.207067 # Inst issue rate system.cpu.iq.fu_busy_cnt 198 # FU busy when requested system.cpu.iq.fu_busy_rate 0.022480 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30218 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 30220 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 14647 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 8115 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 67 # Number of floating instruction queue reads @@ -516,14 +516,14 @@ system.cpu.iew.wb_fanout 0.621403 # av system.cpu.commit.commitSquashedInsts 4444 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 270 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11716 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.494367 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.358573 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11718 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.494282 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.358473 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9551 81.52% 81.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 850 7.26% 88.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 527 4.50% 93.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 215 1.84% 95.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9553 81.52% 81.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 850 7.25% 88.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 527 4.50% 93.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 215 1.83% 95.11% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 176 1.50% 96.61% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 112 0.96% 97.57% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 126 1.08% 98.64% # Number of insts commited each cycle @@ -532,7 +532,7 @@ system.cpu.commit.committed_per_cycle::8 110 0.94% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11716 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11718 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -583,10 +583,10 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5792 # Class of committed instruction system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 21842 # The number of ROB reads +system.cpu.rob.rob_reads 21844 # The number of ROB reads system.cpu.rob.rob_writes 21175 # The number of ROB writes system.cpu.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30119 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 30117 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.cpi 7.344095 # CPI: Cycles Per Instruction diff --git a/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.ini new file mode 100644 index 000000000..d51a8d121 --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.ini @@ -0,0 +1,902 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +threadPolicy=RoundRobin +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 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+children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 opClasses2 opClasses3 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.json b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.json new file mode 100644 index 000000000..0bb65c740 --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.json @@ -0,0 +1,1211 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "static_frontend_latency": 10000, + "tRFC": 260000, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 7500, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1000, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6000, + "tRTW": 2500, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 7500, + "IDD4W": "0.125", + "tWR": 15000, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 13750, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, 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"system.cpu.executeFuncUnits.funcUnits5.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits5.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits5", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 1, + "name": "funcUnits6", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IprAccess", + "name": "opClasses0", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0", + "type": "MinorOpClass" + }, + { + "opClass": "InstPrefetch", + "name": "opClasses1", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits6", + "type": "MinorFU" + } + ], + "type": "MinorFUPool" + }, + "switched_out": false, + "power_model": null, + "max_insts_all_threads": 0, + "executeSetTraceTimeOnIssue": false, + "fetch2InputBufferSize": 2, + "profile": 0, + "fetch2ToDecodeForwardDelay": 1, + "executeInputWidth": 2, + "decodeToExecuteForwardDelay": 1, + "executeLSQRequestsQueueSize": 1, + "fetch2CycleInput": true, + "executeMaxAccessesInMemory": 2, + "enableIdling": true, + "executeLSQStoreBufferSize": 5, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "hello" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "executeSetTraceTimeOnCommit": true, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + }, + "threadPolicy": "RoundRobin", + "executeCommitLimit": 2, + "fetch1LineWidth": 0, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "fetch1ToFetch2ForwardDelay": 1, + "decodeInputBufferSize": 3 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simerr b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simerr new file mode 100755 index 000000000..85a6a33ad --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simerr @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simout b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simout new file mode 100755 index 000000000..2251c9b4d --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simout @@ -0,0 +1,15 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:28 +gem5 executing on zizzer, pid 34056 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/riscv/linux/minor-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 14435000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/stats.txt new file mode 100644 index 000000000..6dc71361b --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/stats.txt @@ -0,0 +1,749 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000014 # Number of seconds simulated +sim_ticks 14435000 # Number of ticks simulated +final_tick 14435000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 13240 # Simulator instruction rate (inst/s) +host_op_rate 13237 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 119615611 # Simulator tick rate (ticks/s) +host_mem_usage 232036 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +sim_insts 1597 # Number of instructions simulated +sim_ops 1597 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 9984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2048 # Number of bytes read from this memory +system.physmem.bytes_read::total 12032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 9984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 9984 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 156 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 32 # Number of read requests responded to by this memory +system.physmem.num_reads::total 188 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 691652234 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 141877381 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 833529616 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 691652234 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 691652234 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 691652234 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 141877381 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 833529616 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 188 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 188 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12032 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12032 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 97 # Per bank write bursts +system.physmem.perBankRdBursts::1 64 # Per bank write bursts +system.physmem.perBankRdBursts::2 18 # Per bank write bursts +system.physmem.perBankRdBursts::3 9 # Per bank write bursts +system.physmem.perBankRdBursts::4 0 # Per bank write bursts +system.physmem.perBankRdBursts::5 0 # Per bank write bursts +system.physmem.perBankRdBursts::6 0 # Per bank write bursts +system.physmem.perBankRdBursts::7 0 # Per bank write bursts +system.physmem.perBankRdBursts::8 0 # Per bank write bursts +system.physmem.perBankRdBursts::9 0 # Per bank write bursts +system.physmem.perBankRdBursts::10 0 # Per bank write bursts +system.physmem.perBankRdBursts::11 0 # Per bank write bursts +system.physmem.perBankRdBursts::12 0 # Per bank write bursts +system.physmem.perBankRdBursts::13 0 # Per bank write bursts +system.physmem.perBankRdBursts::14 0 # Per bank write bursts +system.physmem.perBankRdBursts::15 0 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 14206000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 188 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an 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+system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 13 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 817.230769 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 665.111831 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 349.717542 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1 7.69% 7.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 1 7.69% 15.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1 7.69% 23.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 7.69% 30.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 69.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 13 # Bytes accessed per row activation +system.physmem.totQLat 1580250 # Total ticks spent queuing +system.physmem.totMemAccLat 5105250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 940000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8405.59 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 27155.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 833.53 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 833.53 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 6.51 # Data bus utilization in percentage +system.physmem.busUtilRead 6.51 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 171 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.96 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 75563.83 # Average gap between requests +system.physmem.pageHitRate 90.96 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 121380 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 49335 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1342320 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2281140 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 17760 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 4279560 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 480 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 8706615 # Total energy per rank (pJ) +system.physmem_0.averagePower 603.160028 # Core power per rank (mW) +system.physmem_0.totalIdleTime 9188750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 18000 # Time in different power states +system.physmem_0.memoryStateTime::REF 260000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 1250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 4776000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 9379750 # Time in different power states +system.physmem_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 112290 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2995200 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 2453280 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 6175410 # Total energy per rank (pJ) +system.physmem_1.averagePower 427.808105 # Core power per rank (mW) +system.physmem_1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 7786250 # Time in different power states +system.physmem_1.memoryStateTime::REF 260000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 6388750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 995 # Number of BP lookups +system.cpu.branchPred.condPredicted 543 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 229 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 945 # Number of BTB lookups +system.cpu.branchPred.BTBHits 100 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 10.582011 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 204 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 11 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 193 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 64 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 9 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 14435000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 28870 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 1597 # Number of instructions committed +system.cpu.committedOps 1597 # Number of ops (including micro ops) committed +system.cpu.discardedOps 744 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 18.077646 # CPI: cycles per instruction +system.cpu.ipc 0.055317 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 9 0.56% 0.56% # Class of committed instruction +system.cpu.op_class_0::IntAlu 1019 63.81% 64.37% # Class of committed instruction +system.cpu.op_class_0::IntMult 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 64.37% # Class of committed instruction +system.cpu.op_class_0::MemRead 289 18.10% 82.47% # Class of committed instruction +system.cpu.op_class_0::MemWrite 280 17.53% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 1597 # Class of committed instruction +system.cpu.tickCycles 4106 # Number of cycles that the object actually ticked +system.cpu.idleCycles 24764 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 24.135470 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 645 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 33 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 19.545455 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 24.135470 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.005892 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.005892 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 33 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.008057 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1411 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1411 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 394 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 394 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 251 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 251 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 645 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 645 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 645 # number of overall hits +system.cpu.dcache.overall_hits::total 645 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 16 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 16 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 28 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 28 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 44 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 44 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 44 # number of overall misses +system.cpu.dcache.overall_misses::total 44 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1268000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1268000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2223500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2223500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 3491500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 3491500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 3491500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 3491500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 410 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 410 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 279 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 279 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 689 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 689 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 689 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 689 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039024 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.039024 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.100358 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.100358 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.063861 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.063861 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.063861 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.063861 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79250 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 79250 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79410.714286 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 79410.714286 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 79352.272727 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 79352.272727 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 79352.272727 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 79352.272727 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 11 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 11 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 11 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 16 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 16 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 17 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 17 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 33 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 33 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 33 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 33 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1252000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1252000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1342000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1342000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2594000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 2594000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2594000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 2594000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.060932 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.060932 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047896 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.047896 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047896 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.047896 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78250 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78250 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78941.176471 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78941.176471 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78606.060606 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78606.060606 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78606.060606 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78606.060606 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 79.926884 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 709 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 157 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.515924 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 79.926884 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.039027 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.039027 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 157 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 49 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.076660 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1889 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1889 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 709 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 709 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 709 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 709 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 709 # number of overall hits +system.cpu.icache.overall_hits::total 709 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 157 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 157 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 157 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 157 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 157 # number of overall misses +system.cpu.icache.overall_misses::total 157 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12560500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12560500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12560500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12560500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12560500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12560500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 866 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 866 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 866 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 866 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 866 # number of overall (read+write) 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miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79003.184713 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 102.489649 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 188 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.010638 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.179084 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 23.310565 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002416 # Average percentage of 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overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77926.282051 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79125 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78130.319149 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 17 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 17 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 156 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 156 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 15 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 15 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 156 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 32 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 156 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 32 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 188 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1146500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1146500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10596500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10596500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1065500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1065500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10596500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2212000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12808500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10596500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2212000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12808500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993631 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993631 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.937500 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.937500 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993631 # mshr miss rate for demand accesses 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+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71033.333333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71033.333333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67926.282051 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69125 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68130.319149 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67926.282051 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69125 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68130.319149 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 190 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 173 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 157 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 16 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 314 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 66 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 380 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 12160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 190 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.010526 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.102326 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 188 98.95% 98.95% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2 1.05% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 190 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 95000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 49500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 188 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 14435000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 171 # Transaction distribution +system.membus.trans_dist::ReadExReq 17 # Transaction distribution +system.membus.trans_dist::ReadExResp 17 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 171 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 376 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 376 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 12032 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 12032 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 188 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 188 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 188 # Request fanout histogram +system.membus.reqLayer0.occupancy 217500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 991750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.9 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.ini new file mode 100644 index 000000000..7fd46c549 --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.ini @@ -0,0 +1,872 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cachePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +default_p_state=UNDEFINED +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=0 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 opList3 opList4 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatMult +opLat=4 +pipelined=true + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatDiv +opLat=12 +pipelined=false + +[system.cpu.fuPool.FUList3.opList4] +type=OpDesc +eventq_index=0 +opClass=FloatSqrt +opLat=24 +pipelined=false + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +eventq_index=0 +opClass=SimdAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +eventq_index=0 +opClass=SimdAddAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +eventq_index=0 +opClass=SimdAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +eventq_index=0 +opClass=SimdCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +eventq_index=0 +opClass=SimdCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +eventq_index=0 +opClass=SimdMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +eventq_index=0 +opClass=SimdMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +eventq_index=0 +opClass=SimdMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +eventq_index=0 +opClass=SimdShift +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +eventq_index=0 +opClass=SimdShiftAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +eventq_index=0 +opClass=SimdSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +eventq_index=0 +opClass=SimdFloatDiv +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +eventq_index=0 +opClass=SimdFloatSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 opList2 opList3 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList1] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList8.opList + +[system.cpu.fuPool.FUList8.opList] +type=OpDesc +eventq_index=0 +opClass=IprAccess +opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.json b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.json new file mode 100644 index 000000000..45f6dace0 --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.json @@ -0,0 +1,1151 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "static_frontend_latency": 10000, + "tRFC": 260000, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 7500, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1000, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6000, + "tRTW": 2500, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 7500, + "IDD4W": "0.125", + "tWR": 15000, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + 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"name": "opList13", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList13", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatCvt", + "opLat": 1, + "name": "opList14", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList14", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatDiv", + "opLat": 1, + "name": "opList15", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList15", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatMisc", + "opLat": 1, + "name": "opList16", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList16", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatMult", + "opLat": 1, + "name": "opList17", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList17", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatMultAcc", + "opLat": 1, + "name": "opList18", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList18", + "type": "OpDesc" + }, + { + "opClass": "SimdFloatSqrt", + "opLat": 1, + "name": "opList19", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList5.opList19", + "type": "OpDesc" + } + ], + "name": "FUList5", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList5", + "type": "FUDesc" + }, + { + "count": 0, + "opList": [ + { + "opClass": "MemWrite", + "opLat": 1, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList6.opList0", + "type": "OpDesc" + }, + { + "opClass": "FloatMemWrite", + "opLat": 1, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList6.opList1", + "type": "OpDesc" + } + ], + "name": "FUList6", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList6", + "type": "FUDesc" + }, + { + "count": 4, + "opList": [ + { + "opClass": "MemRead", + "opLat": 1, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList0", + "type": "OpDesc" + }, + { + "opClass": "MemWrite", + "opLat": 1, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList1", + "type": "OpDesc" + }, + { + "opClass": "FloatMemRead", + "opLat": 1, + "name": "opList2", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList2", + "type": "OpDesc" + }, + { + "opClass": "FloatMemWrite", + "opLat": 1, + "name": "opList3", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList3", + "type": "OpDesc" + } + ], + "name": "FUList7", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList7", + "type": "FUDesc" + }, + { + "count": 1, + "opList": [ + { + "opClass": "IprAccess", + "opLat": 3, + "name": "opList", + "pipelined": false, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList8.opList", + "type": "OpDesc" + } + ], + "name": "FUList8", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList8", + "type": "FUDesc" + } + ], + "eventq_index": 0, + "cxx_class": "FUPool", + "path": "system.cpu.fuPool", + "type": "FUPool" + }, + "socket_id": 0, + "renameToFetchDelay": 1, + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "numRobs": 1, + "switched_out": false, + "smtLSQPolicy": "Partitioned", + "fetchBufferSize": 64, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "smtROBThreshold": 100, + "numIQEntries": 64, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "LFSTSize": 1024, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "smtROBPolicy": "Partitioned", + "iewToFetchDelay": 1, + "do_statistics_insts": true, + "dispatchWidth": 8, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "commitToDecodeDelay": 1, + "smtIQPolicy": "Partitioned", + "issueWidth": 8, + "LSQCheckLoads": true, + "commitToRenameDelay": 1, + "cachePorts": 200, + "system": "system", + "checker": null, + "numPhysFloatRegs": 256, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "type": "DerivO3CPU", + "wbWidth": 8, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "smtCommitPolicy": "RoundRobin", + "issueToExecuteDelay": 1, + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 0, + "renameToIEWDelay": 2, + "p_state_clk_gate_bins": 20, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simerr new file mode 100755 index 000000000..85a6a33ad --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simerr @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simout new file mode 100755 index 000000000..d5153ce3d --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simout @@ -0,0 +1,15 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:28 +gem5 executing on zizzer, pid 34057 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/riscv/linux/o3-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 7939500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/stats.txt new file mode 100644 index 000000000..25d8ca24a --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/stats.txt @@ -0,0 +1,1000 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000008 # Number of seconds simulated +sim_ticks 7939500 # Number of ticks simulated +final_tick 7939500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 22942 # Simulator instruction rate (inst/s) +host_op_rate 22935 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 114711600 # Simulator tick rate (ticks/s) +host_mem_usage 232976 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +sim_insts 1587 # Number of instructions simulated +sim_ops 1587 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 9600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2048 # Number of bytes read from this memory +system.physmem.bytes_read::total 11648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 9600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 9600 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 150 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 32 # Number of read requests responded to by this memory +system.physmem.num_reads::total 182 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1209144153 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 257950753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1467094905 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1209144153 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1209144153 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1209144153 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 257950753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1467094905 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 184 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 184 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11648 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11776 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 93 # Per bank write bursts +system.physmem.perBankRdBursts::1 62 # Per bank write bursts +system.physmem.perBankRdBursts::2 18 # Per bank write bursts +system.physmem.perBankRdBursts::3 9 # Per bank write bursts +system.physmem.perBankRdBursts::4 0 # Per bank write bursts +system.physmem.perBankRdBursts::5 0 # Per bank write bursts +system.physmem.perBankRdBursts::6 0 # Per bank write bursts +system.physmem.perBankRdBursts::7 0 # Per bank write bursts +system.physmem.perBankRdBursts::8 0 # Per bank write bursts +system.physmem.perBankRdBursts::9 0 # Per bank write bursts +system.physmem.perBankRdBursts::10 0 # Per bank write bursts +system.physmem.perBankRdBursts::11 0 # Per bank write bursts +system.physmem.perBankRdBursts::12 0 # Per bank write bursts +system.physmem.perBankRdBursts::13 0 # Per bank write bursts +system.physmem.perBankRdBursts::14 0 # Per bank write bursts +system.physmem.perBankRdBursts::15 0 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 7854500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 184 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 13 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 896 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 813.228460 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 265.169128 # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 1 7.69% 7.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1 7.69% 15.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 7.69% 23.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 7.69% 30.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 69.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 13 # Bytes accessed per row activation +system.physmem.totQLat 1405000 # Total ticks spent queuing +system.physmem.totMemAccLat 4817500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 910000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7635.87 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 4945.65 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26182.07 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1467.09 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1483.22 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 11.46 # Data bus utilization in percentage +system.physmem.busUtilRead 11.46 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.90 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 169 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.85 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 42687.50 # Average gap between requests +system.physmem.pageHitRate 91.85 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 92820 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 49335 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1299480 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1581180 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 10080 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 2075940 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 5723475 # Total energy per rank (pJ) +system.physmem_0.averagePower 711.322044 # Core power per rank (mW) +system.physmem_0.totalIdleTime 4551000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states +system.physmem_0.memoryStateTime::REF 139500 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 3237500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 4551000 # Time in different power states +system.physmem_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 112290 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2989920 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 3716850 # Total energy per rank (pJ) +system.physmem_1.averagePower 462.726424 # Core power per rank (mW) +system.physmem_1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 7786250 # Time in different power states +system.physmem_1.memoryStateTime::REF 153250 # Time in different power states +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 1252 # Number of BP lookups +system.cpu.branchPred.condPredicted 681 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 259 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1186 # Number of BTB lookups +system.cpu.branchPred.BTBHits 300 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 25.295110 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 253 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 25 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 228 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 67 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 9 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 7939500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 15880 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 3023 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 4970 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1252 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 325 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 964 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 540 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 803 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 191 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 4447 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.117607 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.502607 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 3513 79.00% 79.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 134 3.01% 82.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 87 1.96% 83.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 91 2.05% 86.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 45 1.01% 87.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 71 1.60% 88.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 65 1.46% 90.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 64 1.44% 91.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 377 8.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 4447 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.078841 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.312972 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 3140 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 349 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 756 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 185 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 187 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 86 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3862 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 255 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 185 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 3239 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 107 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 243 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 672 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3496 # Number of instructions processed by rename +system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full +system.cpu.rename.RenamedOperands 2449 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4481 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4481 # Number of integer rename lookups +system.cpu.rename.CommittedMaps 1077 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 1372 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 16 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 16 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 82 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 548 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 470 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 3003 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 17 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2694 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1432 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 769 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 4447 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.605802 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.426720 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 3524 79.24% 79.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 251 5.64% 84.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185 4.16% 89.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 180 4.05% 93.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 147 3.31% 96.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 65 1.46% 97.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 57 1.28% 99.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 26 0.58% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 4447 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4 5.71% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 30 42.86% 48.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 36 51.43% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 9 0.33% 0.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1755 65.14% 65.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.04% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 512 19.01% 84.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 417 15.48% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 2694 # Type of FU issued +system.cpu.iq.rate 0.169647 # Inst issue rate +system.cpu.iq.fu_busy_cnt 70 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025984 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 9926 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4453 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2310 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2755 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 14 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 259 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 191 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 185 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 106 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3020 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 66 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 548 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 470 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 17 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 12 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 187 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 199 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2452 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 472 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 242 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 847 # number of memory reference insts executed +system.cpu.iew.exec_branches 563 # Number of branches executed +system.cpu.iew.exec_stores 375 # Number of stores executed +system.cpu.iew.exec_rate 0.154408 # Inst execution rate +system.cpu.iew.wb_sent 2361 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2310 # cumulative count of insts written-back +system.cpu.iew.wb_producers 793 # num instructions producing a value +system.cpu.iew.wb_consumers 1130 # num instructions consuming a value +system.cpu.iew.wb_rate 0.145466 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.701770 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 1436 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 174 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 4156 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.381858 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.174026 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 3562 85.71% 85.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 208 5.00% 90.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 146 3.51% 94.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 85 2.05% 96.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 60 1.44% 97.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34 0.82% 98.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 26 0.63% 99.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 14 0.34% 99.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 21 0.51% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 4156 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1587 # Number of instructions committed +system.cpu.commit.committedOps 1587 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 568 # Number of memory references committed +system.cpu.commit.loads 289 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 373 # Number of branches committed +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1587 # Number of committed integer instructions. +system.cpu.commit.function_calls 142 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 1019 64.21% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.21% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 289 18.21% 82.42% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 279 17.58% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1587 # Class of committed instruction +system.cpu.commit.bw_lim_events 21 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 7041 # The number of ROB reads +system.cpu.rob.rob_writes 6340 # The number of ROB writes +system.cpu.timesIdled 96 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11433 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1587 # Number of Instructions Simulated +system.cpu.committedOps 1587 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 10.006301 # CPI: Cycles Per Instruction +system.cpu.cpi_total 10.006301 # CPI: Total CPI of All Threads +system.cpu.ipc 0.099937 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.099937 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3068 # number of integer regfile reads +system.cpu.int_regfile_writes 1663 # number of integer regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 24.179106 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 626 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 33 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 18.969697 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 24.179106 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.005903 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.005903 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 33 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.008057 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1497 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1497 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 432 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 432 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 194 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 194 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 626 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 626 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 626 # number of overall hits +system.cpu.dcache.overall_hits::total 626 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 21 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 21 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 106 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 106 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 106 # number of overall misses +system.cpu.dcache.overall_misses::total 106 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1305000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1305000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6101500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6101500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7406500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7406500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7406500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7406500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 453 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 453 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 279 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 279 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 732 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 732 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 732 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 732 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.046358 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.046358 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.304659 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.304659 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.144809 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.144809 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.144809 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.144809 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62142.857143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62142.857143 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71782.352941 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 71782.352941 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69872.641509 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69872.641509 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69872.641509 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69872.641509 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 67 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 67 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 72 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 72 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 72 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 16 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 16 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 18 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 18 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 34 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 34 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 34 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 34 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1141000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1141000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1431500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1431500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2572500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 2572500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2572500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 2572500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035320 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035320 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.064516 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.064516 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.046448 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.046448 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046448 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.046448 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71312.500000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71312.500000 # average ReadReq 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rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68027.777778 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68027.777778 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66578.947368 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66578.947368 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64400 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64400 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66578.947368 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66378.787879 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66543.243243 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66578.947368 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66378.787879 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66543.243243 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 187 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 166 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 18 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 18 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 153 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 16 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 304 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 67 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 371 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 11776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 187 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.010695 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103139 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 185 98.93% 98.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2 1.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 187 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 93500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 226500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 49500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 184 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 7939500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 164 # Transaction distribution +system.membus.trans_dist::ReadExReq 18 # Transaction distribution +system.membus.trans_dist::ReadExResp 18 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 166 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 366 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 366 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 11648 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 11648 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 184 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 184 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 184 # Request fanout histogram +system.membus.reqLayer0.occupancy 228500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 948750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.9 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.ini new file mode 100644 index 000000000..76abe1457 --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.ini @@ -0,0 +1,211 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.json b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.json new file mode 100644 index 000000000..663d5cd98 --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.json @@ -0,0 +1,289 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "atomic", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "simulate_data_stalls": false, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "AtomicSimpleCPU", + "max_loads_all_threads": 0, + "system": "system", + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "width": 1, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "do_quiesce": true, + "type": "AtomicSimpleCPU", + "fastmem": false, + "profile": 0, + "icache_port": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.membus.slave[2]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "hello" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "simulate_inst_stalls": false, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simout new file mode 100755 index 000000000..0253c62ea --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simout @@ -0,0 +1,15 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-atomic/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:29 +gem5 executing on zizzer, pid 34058 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-atomic + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 798000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/stats.txt new file mode 100644 index 000000000..c14fe390a --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/stats.txt @@ -0,0 +1,153 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000001 # Number of seconds simulated +sim_ticks 798000 # Number of ticks simulated +final_tick 798000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 49942 # Simulator instruction rate (inst/s) +host_op_rate 49911 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25081647 # Simulator tick rate (ticks/s) +host_mem_usage 221640 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +sim_insts 1587 # Number of instructions simulated +sim_ops 1587 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 798000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 6388 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1816 # Number of bytes read from this memory +system.physmem.bytes_read::total 8204 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 6388 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6388 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 1750 # Number of bytes written to this memory +system.physmem.bytes_written::total 1750 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1597 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1886 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 279 # Number of write requests responded to by this memory +system.physmem.num_writes::total 279 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8005012531 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2275689223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10280701754 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8005012531 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8005012531 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 2192982456 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2192982456 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8005012531 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4468671679 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12473684211 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 798000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 9 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 798000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1597 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 1587 # Number of instructions committed +system.cpu.committedOps 1587 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1588 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 142 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 231 # number of instructions that are conditional controls +system.cpu.num_int_insts 1588 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 2062 # number of times the integer registers were read +system.cpu.num_int_register_writes 1077 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 569 # number of memory refs +system.cpu.num_load_insts 289 # Number of load instructions +system.cpu.num_store_insts 280 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 1597 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 373 # Number of branches fetched +system.cpu.op_class::No_OpClass 9 0.56% 0.56% # Class of executed instruction +system.cpu.op_class::IntAlu 1019 63.81% 64.37% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::MemRead 289 18.10% 82.47% # Class of executed instruction +system.cpu.op_class::MemWrite 280 17.53% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 1597 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 798000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 1886 # Transaction distribution +system.membus.trans_dist::ReadResp 1886 # Transaction distribution +system.membus.trans_dist::WriteReq 279 # Transaction distribution +system.membus.trans_dist::WriteResp 279 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3194 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1136 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4330 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6388 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3566 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 9954 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2165 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2165 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2165 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.ini new file mode 100644 index 000000000..9d9106168 --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.ini @@ -0,0 +1,1265 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:268435455:0:0:0:0 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu.clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] +icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] + +[system.cpu.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000 + +[system.mem_ctrls] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +page_policy=open_adaptive +power_model=Null +range=0:268435455:5:19:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10 +static_frontend_latency=10 +tBURST=5 +tCCD_L=0 +tCK=1 +tCL=14 +tCS=3 +tRAS=35 +tRCD=14 +tREFI=7800 +tRFC=260 +tRP=14 +tRRD=6 +tRRD_L=0 +tRTP=8 +tRTW=3 +tWR=15 +tWTR=8 +tXAW=30 +tXP=6 +tXPDLL=0 +tXS=270 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.ruby.dir_cntrl0.memory + +[system.ruby] +type=RubySystem +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +access_backing_store=false +all_instructions=false +block_size_bytes=64 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hot_lines=false +memory_size_bits=48 +num_of_sequencers=1 +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +phys_mem=Null +power_model=Null +randomization=false + +[system.ruby.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.ruby.dir_cntrl0] +type=Directory_Controller +children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory +buffer_size=0 +clk_domain=system.ruby.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +directory=system.ruby.dir_cntrl0.directory +directory_latency=12 +dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir +dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir +eventq_index=0 +forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestToDir=system.ruby.dir_cntrl0.requestToDir +responseFromDir=system.ruby.dir_cntrl0.responseFromDir +responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory +ruby_system=system.ruby +system=system +to_memory_controller_latency=1 +transitions_per_cycle=4 +version=0 +memory=system.mem_ctrls.port + +[system.ruby.dir_cntrl0.directory] +type=RubyDirectoryMemory +eventq_index=0 +numa_high_bit=5 +size=268435456 +version=0 + +[system.ruby.dir_cntrl0.dmaRequestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[3] + +[system.ruby.dir_cntrl0.dmaResponseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[3] + +[system.ruby.dir_cntrl0.forwardFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[4] + +[system.ruby.dir_cntrl0.requestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[2] + +[system.ruby.dir_cntrl0.responseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[2] + +[system.ruby.dir_cntrl0.responseFromMemory] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0] +type=L1Cache_Controller +children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer +buffer_size=0 +cacheMemory=system.ruby.l1_cntrl0.cacheMemory +cache_response_latency=12 +clk_domain=system.cpu.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +eventq_index=0 +forwardToCache=system.ruby.l1_cntrl0.forwardToCache +issue_latency=2 +mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestFromCache=system.ruby.l1_cntrl0.requestFromCache +responseFromCache=system.ruby.l1_cntrl0.responseFromCache +responseToCache=system.ruby.l1_cntrl0.responseToCache +ruby_system=system.ruby +send_evictions=false +sequencer=system.ruby.l1_cntrl0.sequencer +system=system +transitions_per_cycle=4 +version=0 + +[system.ruby.l1_cntrl0.cacheMemory] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=1 +eventq_index=0 +is_icache=false +replacement_policy=system.ruby.l1_cntrl0.cacheMemory.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=256 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 + +[system.ruby.l1_cntrl0.cacheMemory.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=256 + +[system.ruby.l1_cntrl0.forwardToCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[0] + +[system.ruby.l1_cntrl0.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0.requestFromCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[0] + +[system.ruby.l1_cntrl0.responseFromCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[1] + +[system.ruby.l1_cntrl0.responseToCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[1] + +[system.ruby.l1_cntrl0.sequencer] +type=RubySequencer +clk_domain=system.cpu.clk_domain +coreid=99 +dcache=system.ruby.l1_cntrl0.cacheMemory +dcache_hit_latency=1 +deadlock_threshold=500000 +default_p_state=UNDEFINED +eventq_index=0 +garnet_standalone=false +icache=system.ruby.l1_cntrl0.cacheMemory +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.cpu.icache_port system.cpu.dcache_port + +[system.ruby.memctrl_clk_domain] +type=DerivedClockDomain +clk_divider=3 +clk_domain=system.ruby.clk_domain +eventq_index=0 + +[system.ruby.network] +type=SimpleNetwork +children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 +adaptive_routing=false +buffer_size=0 +clk_domain=system.ruby.clk_domain +control_msg_size=8 +default_p_state=UNDEFINED +endpoint_bandwidth=1000 +eventq_index=0 +ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 +netifs= +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 +ruby_system=system.ruby +topology=Crossbar +master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave +slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master + +[system.ruby.network.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.l1_cntrl0 +int_node=system.ruby.network.routers0 +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.ext_links1] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.dir_cntrl0 +int_node=system.ruby.network.routers1 +latency=1 +link_id=1 +weight=1 + +[system.ruby.network.int_link_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers09] +type=MessageBuffer +buffer_size=0 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+[system.ruby.network.int_link_buffers17] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers20] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers21] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers22] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers23] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 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+[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers36] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers37] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers38] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_links0] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=2 +src_node=system.ruby.network.routers0 +src_outport= +weight=1 + +[system.ruby.network.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=3 +src_node=system.ruby.network.routers1 +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=4 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=5 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.routers0] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 +power_model=Null +router_id=0 +virt_nets=5 + +[system.ruby.network.routers0.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 +power_model=Null +router_id=1 +virt_nets=5 + +[system.ruby.network.routers1.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 +power_model=Null +router_id=2 +virt_nets=5 + +[system.ruby.network.routers2.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + 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+support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.system_port + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.json b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.json new file mode 100644 index 000000000..331c89064 --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.json @@ -0,0 +1,1734 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + 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"tRRD": 6, + "tRTW": 3, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 8, + "IDD4W": "0.125", + "tWR": 15, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 14, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 3, + "power_model": null, + "tCL": 14, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1, + "tRAS": 35, + "tRP": 14, + "tBURST": 5, + "path": "system.mem_ctrls", + "tXP": 6, + "tXS": 270, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "mem_ctrls", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30, + "write_low_thresh_perc": 50, + "range": "0:268435455:5:19:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800 + } + ], + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simerr new file mode 100755 index 000000000..63b14556f --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simerr @@ -0,0 +1,11 @@ +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simout new file mode 100755 index 000000000..a4d87ef7e --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simout @@ -0,0 +1,15 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:29 +gem5 executing on zizzer, pid 34060 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-timing-ruby + +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 27947 because target called exit() diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/stats.txt new file mode 100644 index 000000000..e859af8d4 --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/stats.txt @@ -0,0 +1,639 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000028 # Number of seconds simulated +sim_ticks 27947 # Number of ticks simulated +final_tick 27947 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 19868 # Simulator instruction rate (inst/s) +host_op_rate 19863 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 349695 # Simulator tick rate (ticks/s) +host_mem_usage 390760 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +sim_insts 1587 # Number of instructions simulated +sim_ops 1587 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 28032 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 28032 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 27776 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 27776 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 438 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 438 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 434 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 434 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 1003041471 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1003041471 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 993881275 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 993881275 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1996922747 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1996922747 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 438 # Number of read requests accepted +system.mem_ctrls.writeReqs 434 # Number of write requests accepted +system.mem_ctrls.readBursts 438 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 434 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 15616 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 12416 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 14912 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 28032 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 27776 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 194 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 183 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 102 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 69 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 43 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 30 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 100 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 62 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 41 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 30 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 27875 # Total gap between requests +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 438 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 434 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 244 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see 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req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 12 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 14 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 15 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 15 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 16 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 14 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 14 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 14 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 14 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 14 # What write queue length does an incoming req see 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write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 35 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 835.657143 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 690.201292 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 331.080756 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 2 5.71% 5.71% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 2 5.71% 11.43% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 1 2.86% 14.29% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 1 2.86% 17.14% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 1 2.86% 20.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 3 8.57% 28.57% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 25 71.43% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 35 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 14 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 17.285714 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 16.736288 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 5.580579 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 1 7.14% 7.14% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 4 28.57% 35.71% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 7 50.00% 85.71% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 1 7.14% 92.86% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 7.14% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 14 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 14 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.642857 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.611629 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.081818 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 10 71.43% 71.43% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 3 21.43% 92.86% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 1 7.14% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 14 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 2979 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 7615 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 1220 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 12.21 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 31.21 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 558.77 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 533.58 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1003.04 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 993.88 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 8.53 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.37 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.17 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 24.44 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 212 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 228 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 86.89 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 90.84 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 31.97 # Average gap between requests +system.mem_ctrls.pageHitRate 88.89 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 264180 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 135240 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 2787456 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 1946016 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 4405872 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 40704 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 8149176 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 118272 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 19690836 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 704.577808 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 18179 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 22 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 780 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 308 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 8966 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 17871 # Time in different power states +system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 224352 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3002880 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 2889984 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 2906160 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 10252656 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 366.860701 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 7526 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 526 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 12109 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 7526 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 9 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 27947 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 27947 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 1587 # Number of instructions committed +system.cpu.committedOps 1587 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1588 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 142 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 231 # number of instructions that are conditional controls +system.cpu.num_int_insts 1588 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 2062 # number of times the integer registers were read +system.cpu.num_int_register_writes 1077 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 569 # number of memory refs +system.cpu.num_load_insts 289 # Number of load instructions +system.cpu.num_store_insts 280 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 27947 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 373 # Number of branches fetched +system.cpu.op_class::No_OpClass 9 0.56% 0.56% # Class of executed instruction +system.cpu.op_class::IntAlu 1019 63.81% 64.37% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::MemRead 289 18.10% 82.47% # Class of executed instruction +system.cpu.op_class::MemWrite 280 17.53% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 1597 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 872 # delay histogram for all message +system.ruby.delayHist | 872 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 872 # delay histogram for all message +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 2166 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 2166 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 2166 +system.ruby.latency_hist_seqr::bucket_size 32 +system.ruby.latency_hist_seqr::max_bucket 319 +system.ruby.latency_hist_seqr::samples 2165 +system.ruby.latency_hist_seqr::mean 11.908545 +system.ruby.latency_hist_seqr::gmean 2.205817 +system.ruby.latency_hist_seqr::stdev 24.908130 +system.ruby.latency_hist_seqr | 1727 79.77% 79.77% | 202 9.33% 89.10% | 224 10.35% 99.45% | 2 0.09% 99.54% | 2 0.09% 99.63% | 7 0.32% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 1 0.05% 100.00% +system.ruby.latency_hist_seqr::total 2165 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 1727 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 1727 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 1727 +system.ruby.miss_latency_hist_seqr::bucket_size 32 +system.ruby.miss_latency_hist_seqr::max_bucket 319 +system.ruby.miss_latency_hist_seqr::samples 438 +system.ruby.miss_latency_hist_seqr::mean 54.920091 +system.ruby.miss_latency_hist_seqr::gmean 49.915756 +system.ruby.miss_latency_hist_seqr::stdev 27.345330 +system.ruby.miss_latency_hist_seqr | 0 0.00% 0.00% | 202 46.12% 46.12% | 224 51.14% 97.26% | 2 0.46% 97.72% | 2 0.46% 98.17% | 7 1.60% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 1 0.23% 100.00% +system.ruby.miss_latency_hist_seqr::total 438 +system.ruby.Directory.incomplete_times_seqr 437 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.cacheMemory.demand_hits 1727 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 438 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 2165 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 7.800479 +system.ruby.network.routers0.msg_count.Control::2 438 +system.ruby.network.routers0.msg_count.Data::2 434 +system.ruby.network.routers0.msg_count.Response_Data::4 438 +system.ruby.network.routers0.msg_count.Writeback_Control::3 434 +system.ruby.network.routers0.msg_bytes.Control::2 3504 +system.ruby.network.routers0.msg_bytes.Data::2 31248 +system.ruby.network.routers0.msg_bytes.Response_Data::4 31536 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 3472 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 7.800479 +system.ruby.network.routers1.msg_count.Control::2 438 +system.ruby.network.routers1.msg_count.Data::2 434 +system.ruby.network.routers1.msg_count.Response_Data::4 438 +system.ruby.network.routers1.msg_count.Writeback_Control::3 434 +system.ruby.network.routers1.msg_bytes.Control::2 3504 +system.ruby.network.routers1.msg_bytes.Data::2 31248 +system.ruby.network.routers1.msg_bytes.Response_Data::4 31536 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 3472 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 7.800479 +system.ruby.network.routers2.msg_count.Control::2 438 +system.ruby.network.routers2.msg_count.Data::2 434 +system.ruby.network.routers2.msg_count.Response_Data::4 438 +system.ruby.network.routers2.msg_count.Writeback_Control::3 434 +system.ruby.network.routers2.msg_bytes.Control::2 3504 +system.ruby.network.routers2.msg_bytes.Data::2 31248 +system.ruby.network.routers2.msg_bytes.Response_Data::4 31536 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 3472 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 1314 +system.ruby.network.msg_count.Data 1302 +system.ruby.network.msg_count.Response_Data 1314 +system.ruby.network.msg_count.Writeback_Control 1302 +system.ruby.network.msg_byte.Control 10512 +system.ruby.network.msg_byte.Data 93744 +system.ruby.network.msg_byte.Response_Data 94608 +system.ruby.network.msg_byte.Writeback_Control 10416 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 27947 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 7.829105 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 438 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 434 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 31536 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 3472 +system.ruby.network.routers0.throttle1.link_utilization 7.771854 +system.ruby.network.routers0.throttle1.msg_count.Control::2 438 +system.ruby.network.routers0.throttle1.msg_count.Data::2 434 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 3504 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 31248 +system.ruby.network.routers1.throttle0.link_utilization 7.771854 +system.ruby.network.routers1.throttle0.msg_count.Control::2 438 +system.ruby.network.routers1.throttle0.msg_count.Data::2 434 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 3504 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 31248 +system.ruby.network.routers1.throttle1.link_utilization 7.829105 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 438 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 434 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 31536 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 3472 +system.ruby.network.routers2.throttle0.link_utilization 7.829105 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 438 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 434 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 31536 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 3472 +system.ruby.network.routers2.throttle1.link_utilization 7.771854 +system.ruby.network.routers2.throttle1.msg_count.Control::2 438 +system.ruby.network.routers2.throttle1.msg_count.Data::2 434 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 3504 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 31248 +system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 438 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 438 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 438 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 434 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 434 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 434 # delay histogram for vnet_2 +system.ruby.LD.latency_hist_seqr::bucket_size 32 +system.ruby.LD.latency_hist_seqr::max_bucket 319 +system.ruby.LD.latency_hist_seqr::samples 289 +system.ruby.LD.latency_hist_seqr::mean 23.332180 +system.ruby.LD.latency_hist_seqr::gmean 5.457216 +system.ruby.LD.latency_hist_seqr::stdev 32.553168 +system.ruby.LD.latency_hist_seqr | 161 55.71% 55.71% | 72 24.91% 80.62% | 54 18.69% 99.31% | 0 0.00% 99.31% | 0 0.00% 99.31% | 1 0.35% 99.65% | 0 0.00% 99.65% | 0 0.00% 99.65% | 0 0.00% 99.65% | 1 0.35% 100.00% +system.ruby.LD.latency_hist_seqr::total 289 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 161 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 161 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 161 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 32 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 319 +system.ruby.LD.miss_latency_hist_seqr::samples 128 +system.ruby.LD.miss_latency_hist_seqr::mean 51.421875 +system.ruby.LD.miss_latency_hist_seqr::gmean 46.125665 +system.ruby.LD.miss_latency_hist_seqr::stdev 31.235103 +system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 72 56.25% 56.25% | 54 42.19% 98.44% | 0 0.00% 98.44% | 0 0.00% 98.44% | 1 0.78% 99.22% | 0 0.00% 99.22% | 0 0.00% 99.22% | 0 0.00% 99.22% | 1 0.78% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 128 +system.ruby.ST.latency_hist_seqr::bucket_size 16 +system.ruby.ST.latency_hist_seqr::max_bucket 159 +system.ruby.ST.latency_hist_seqr::samples 279 +system.ruby.ST.latency_hist_seqr::mean 13.150538 +system.ruby.ST.latency_hist_seqr::gmean 2.682693 +system.ruby.ST.latency_hist_seqr::stdev 23.311750 +system.ruby.ST.latency_hist_seqr | 206 73.84% 73.84% | 0 0.00% 73.84% | 45 16.13% 89.96% | 2 0.72% 90.68% | 22 7.89% 98.57% | 2 0.72% 99.28% | 0 0.00% 99.28% | 1 0.36% 99.64% | 1 0.36% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 279 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 206 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 206 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 206 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 16 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 159 +system.ruby.ST.miss_latency_hist_seqr::samples 73 +system.ruby.ST.miss_latency_hist_seqr::mean 47.438356 +system.ruby.ST.miss_latency_hist_seqr::gmean 43.447321 +system.ruby.ST.miss_latency_hist_seqr::stdev 21.997466 +system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 45 61.64% 61.64% | 2 2.74% 64.38% | 22 30.14% 94.52% | 2 2.74% 97.26% | 0 0.00% 97.26% | 1 1.37% 98.63% | 1 1.37% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 73 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 32 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 319 +system.ruby.IFETCH.latency_hist_seqr::samples 1597 +system.ruby.IFETCH.latency_hist_seqr::mean 9.624296 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.809372 +system.ruby.IFETCH.latency_hist_seqr::stdev 22.939232 +system.ruby.IFETCH.latency_hist_seqr | 1360 85.16% 85.16% | 83 5.20% 90.36% | 146 9.14% 99.50% | 1 0.06% 99.56% | 1 0.06% 99.62% | 6 0.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 1597 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 1360 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 1360 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 1360 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 237 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 59.113924 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 54.365760 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 25.891554 +system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 83 35.02% 35.02% | 146 61.60% 96.62% | 1 0.42% 97.05% | 1 0.42% 97.47% | 6 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 237 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 32 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 319 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 438 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 54.920091 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 49.915756 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 27.345330 +system.ruby.Directory.miss_mach_latency_hist_seqr | 0 0.00% 0.00% | 202 46.12% 46.12% | 224 51.14% 97.26% | 2 0.46% 97.72% | 2 0.46% 98.17% | 7 1.60% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 1 0.23% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 438 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 128 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 51.421875 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 46.125665 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 31.235103 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 72 56.25% 56.25% | 54 42.19% 98.44% | 0 0.00% 98.44% | 0 0.00% 98.44% | 1 0.78% 99.22% | 0 0.00% 99.22% | 0 0.00% 99.22% | 0 0.00% 99.22% | 1 0.78% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 128 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 73 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 47.438356 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 43.447321 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 21.997466 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 45 61.64% 61.64% | 2 2.74% 64.38% | 22 30.14% 94.52% | 2 2.74% 97.26% | 0 0.00% 97.26% | 1 1.37% 98.63% | 1 1.37% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 73 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 237 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 59.113924 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 54.365760 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 25.891554 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 83 35.02% 35.02% | 146 61.60% 96.62% | 1 0.42% 97.05% | 1 0.42% 97.47% | 6 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 237 +system.ruby.Directory_Controller.GETX 438 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 434 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 438 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 434 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 438 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 434 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 438 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 434 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 289 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 1597 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 279 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 438 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 434 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 434 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 128 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 237 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 73 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 161 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 1360 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 206 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 434 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 434 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 365 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 73 0.00% 0.00% + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.ini new file mode 100644 index 000000000..95b43cc99 --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.ini @@ -0,0 +1,380 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tag_latency=2 +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 +tag_latency=2 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=2 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tag_latency=2 +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=2 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 +tag_latency=2 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +data_latency=20 +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tag_latency=20 +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +data_latency=20 +default_p_state=UNDEFINED +eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 +tag_latency=20 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.json b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.json new file mode 100644 index 000000000..0e161c12e --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.json @@ -0,0 +1,508 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 131072, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "data_latency": 2, + "tag_latency": 2, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "mshrs": 20, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 2097152, + "tag_latency": 20, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 20 + }, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "data_latency": 20, + "tag_latency": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/z/powerjg/gem5-upstream/tests/test-progs/hello/bin/riscv/linux/hello", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "hello" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "type": "Cache", + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "mshrs": 4, + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "tags": { + "size": 262144, + "tag_latency": 2, + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "block_size": 64, + "type": "LRU", + "data_latency": 2 + }, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "data_latency": 2, + "tag_latency": 2, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +}
\ No newline at end of file diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simerr new file mode 100755 index 000000000..fd133b12b --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simerr @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simout new file mode 100755 index 000000000..b34519614 --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simout @@ -0,0 +1,15 @@ +Redirecting stdout to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing/simout +Redirecting stderr to build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 30 2016 14:33:35 +gem5 started Nov 30 2016 16:18:29 +gem5 executing on zizzer, pid 34059 +command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 11602500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/stats.txt new file mode 100644 index 000000000..bb8642e88 --- /dev/null +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/stats.txt @@ -0,0 +1,511 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 11602500 # Number of ticks simulated +final_tick 11602500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 36172 # Simulator instruction rate (inst/s) +host_op_rate 36155 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 264212858 # Simulator tick rate (ticks/s) +host_mem_usage 230876 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +sim_insts 1587 # Number of instructions simulated +sim_ops 1587 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 7808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1920 # Number of bytes read from this memory +system.physmem.bytes_read::total 9728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 7808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7808 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 122 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 30 # Number of read requests responded to by this memory +system.physmem.num_reads::total 152 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 672958414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 165481577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 838439991 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 672958414 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 672958414 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 672958414 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 165481577 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 838439991 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 9 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 11602500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 23205 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 1587 # Number of instructions committed +system.cpu.committedOps 1587 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1588 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 142 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 231 # number of instructions that are conditional controls +system.cpu.num_int_insts 1588 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 2062 # number of times the integer registers were read +system.cpu.num_int_register_writes 1077 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 569 # number of memory refs +system.cpu.num_load_insts 289 # Number of load instructions +system.cpu.num_store_insts 280 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 23205 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 373 # Number of branches fetched +system.cpu.op_class::No_OpClass 9 0.56% 0.56% # Class of executed instruction +system.cpu.op_class::IntAlu 1019 63.81% 64.37% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.37% # Class of executed instruction +system.cpu.op_class::MemRead 289 18.10% 82.47% # Class of executed instruction +system.cpu.op_class::MemWrite 280 17.53% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 1597 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 22.779229 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 537 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 31 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.322581 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 22.779229 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.005561 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.005561 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 31 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.007568 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1167 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1167 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 276 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 276 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 261 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 261 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 537 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 537 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 537 # number of overall hits +system.cpu.dcache.overall_hits::total 537 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 13 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 13 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 18 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 18 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 31 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 31 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 31 # number of overall misses +system.cpu.dcache.overall_misses::total 31 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 770000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 770000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1134000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1134000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1904000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1904000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1904000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1904000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 289 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 289 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 279 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 279 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 568 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 568 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 568 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 568 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.044983 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.044983 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.064516 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.064516 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.054577 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.054577 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.054577 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.054577 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59230.769231 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59230.769231 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61419.354839 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61419.354839 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61419.354839 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61419.354839 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 13 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 13 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 18 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 18 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 31 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 31 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 31 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 31 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 757000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 757000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1116000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1116000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1873000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 1873000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1873000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 1873000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044983 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044983 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.064516 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.064516 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054577 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.054577 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054577 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.054577 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58230.769231 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58230.769231 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60419.354839 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60419.354839 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60419.354839 # average overall mshr miss latency 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+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 122 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 122 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 122 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 122 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 122 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 122 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7564500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 7564500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7564500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 7564500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7564500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 7564500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076345 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076345 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076345 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.076345 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076345 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.076345 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62004.098361 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62004.098361 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62004.098361 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 62004.098361 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62004.098361 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 62004.098361 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 78.991344 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 152 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.006579 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 57.023406 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 21.967939 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001740 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000670 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.002411 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 152 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.004639 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 1376 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 1376 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits +system.cpu.l2cache.overall_hits::total 1 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 18 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 18 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 122 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 122 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 12 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 122 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 30 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 152 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 122 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 30 # number of overall misses +system.cpu.l2cache.overall_misses::total 152 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1089000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1089000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 7381500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 7381500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 726000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 726000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 7381500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1815000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9196500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 7381500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1815000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9196500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_accesses::cpu.data 18 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 18 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 122 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 122 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 13 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 13 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 122 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 31 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 153 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 122 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 31 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 153 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.923077 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.923077 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.967742 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.993464 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.967742 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.993464 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60504.098361 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60504.098361 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60504.098361 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60503.289474 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60504.098361 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60503.289474 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 18 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 18 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 122 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 122 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 122 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 30 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 152 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 122 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 30 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 152 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 909000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 909000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 6161500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 6161500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 606000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 606000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6161500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1515000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7676500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6161500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1515000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7676500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.923077 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.923077 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.967742 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.993464 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.967742 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.993464 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50504.098361 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50504.098361 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50504.098361 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50503.289474 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50504.098361 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50503.289474 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 153 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 135 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 18 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 18 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 122 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 13 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 244 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 306 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 9792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 153 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.006536 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.080845 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 152 99.35% 99.35% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.65% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 153 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 76500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 183000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 46500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 152 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 11602500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 134 # Transaction distribution +system.membus.trans_dist::ReadExReq 18 # Transaction distribution +system.membus.trans_dist::ReadExResp 18 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 134 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 304 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 304 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 9728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 9728 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 152 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 152 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 152 # Request fanout histogram +system.membus.reqLayer0.occupancy 152500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 760000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.6 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini index 774234af5..5809007c6 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini @@ -183,10 +183,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -200,6 +200,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -212,15 +213,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=X86TLB @@ -313,10 +315,10 @@ pipelined=true [system.cpu.fuPool.FUList3] type=FUDesc -children=opList0 opList1 opList2 +children=opList0 opList1 opList2 opList3 opList4 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 [system.cpu.fuPool.FUList3.opList0] type=OpDesc @@ -328,11 +330,25 @@ pipelined=true [system.cpu.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 opClass=FloatDiv opLat=12 pipelined=false -[system.cpu.fuPool.FUList3.opList2] +[system.cpu.fuPool.FUList3.opList4] type=OpDesc eventq_index=0 opClass=FloatSqrt @@ -341,18 +357,25 @@ pipelined=false [system.cpu.fuPool.FUList4] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 -[system.cpu.fuPool.FUList4.opList] +[system.cpu.fuPool.FUList4.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 @@ -502,24 +525,31 @@ pipelined=true [system.cpu.fuPool.FUList6] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -[system.cpu.fuPool.FUList6.opList] +[system.cpu.fuPool.FUList6.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList7] type=FUDesc -children=opList0 opList1 +children=opList0 opList1 opList2 opList3 count=4 eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 [system.cpu.fuPool.FUList7.opList0] type=OpDesc @@ -535,6 +565,20 @@ opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList8] type=FUDesc children=opList @@ -556,10 +600,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -573,6 +617,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -585,15 +630,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=X86LocalApic @@ -643,10 +689,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -660,6 +706,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -672,15 +719,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -725,7 +773,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/x86/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin kvmInSE=false diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index ce4c9483b..5ab7e4cb5 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 21:09:20 -gem5 executing on e108600-lin, pid 17644 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/x86/linux/o3-timing +gem5 compiled Nov 29 2016 18:55:59 +gem5 started Nov 29 2016 18:56:21 +gem5 executing on zizzer, pid 719 +command line: /z/powerjg/gem5-upstream/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 7984b1b75..ff0e9261d 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 22466500 # Number of ticks simulated final_tick 22466500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70304 # Simulator instruction rate (inst/s) -host_op_rate 127350 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 293494415 # Simulator tick rate (ticks/s) -host_mem_usage 271256 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 24766 # Simulator instruction rate (inst/s) +host_op_rate 44863 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 103395613 # Simulator tick rate (ticks/s) +host_mem_usage 253532 # Number of bytes of host memory used +host_seconds 0.22 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 2 2.11% 93.68% # By system.physmem.bytesPerActivate::896-1023 2 2.11% 95.79% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 4 4.21% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 95 # Bytes accessed per row activation -system.physmem.totQLat 6803250 # Total ticks spent queuing -system.physmem.totMemAccLat 14640750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 6799250 # Total ticks spent queuing +system.physmem.totMemAccLat 14636750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2090000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16275.72 # Average queueing delay per DRAM burst +system.physmem.avgQLat 16266.15 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 35025.72 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 35016.15 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1190.75 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1190.75 # Average system read bandwidth in MiByte/s @@ -247,9 +247,9 @@ system.physmem_1.preEnergy 235290 # En system.physmem_1.readEnergy 1570800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2963430 # Energy for active background per rank (pJ) +system.physmem_1.actBackEnergy 2962290 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 82560 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 7182000 # Energy for active power-down per rank (pJ) +system.physmem_1.actPowerDownEnergy 7183140 # Energy for active power-down per rank (pJ) system.physmem_1.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.physmem_1.totalEnergy 13750320 # Total energy per rank (pJ) @@ -354,13 +354,13 @@ system.cpu.iq.iqSquashedOperandsExamined 16553 # Nu system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 24836 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.729264 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.710819 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.710701 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19691 79.28% 79.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1200 4.83% 84.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 866 3.49% 87.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 19689 79.28% 79.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1202 4.84% 84.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 867 3.49% 87.61% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 575 2.32% 89.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 815 3.28% 93.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 814 3.28% 93.20% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 575 2.32% 95.51% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 614 2.47% 97.99% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 364 1.47% 99.45% # Number of insts issued each cycle @@ -493,20 +493,20 @@ system.cpu.iew.exec_stores 1259 # Nu system.cpu.iew.exec_rate 0.379178 # Inst execution rate system.cpu.iew.wb_sent 16737 # cumulative count of insts sent to commit system.cpu.iew.wb_count 16422 # cumulative count of insts written-back -system.cpu.iew.wb_producers 11019 # num instructions producing a value -system.cpu.iew.wb_consumers 17148 # num instructions consuming a value +system.cpu.iew.wb_producers 11018 # num instructions producing a value +system.cpu.iew.wb_consumers 17146 # num instructions consuming a value system.cpu.iew.wb_rate 0.365469 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.642582 # average fanout of values written-back +system.cpu.iew.wb_fanout 0.642599 # average fanout of values written-back system.cpu.commit.commitSquashedInsts 12050 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 648 # The number of times a branch was mispredicted system.cpu.commit.committed_per_cycle::samples 22793 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 0.427631 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.307645 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.307612 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19538 85.72% 85.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1001 4.39% 90.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 566 2.48% 92.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19537 85.71% 85.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1003 4.40% 90.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 565 2.48% 92.59% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 727 3.19% 95.78% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 384 1.68% 97.47% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 133 0.58% 98.05% # Number of insts commited each cycle @@ -586,12 +586,12 @@ system.cpu.misc_regfile_reads 7640 # nu system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.537714 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 81.537314 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2520 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 17.872340 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.537714 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 81.537314 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.019907 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.019907 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id @@ -617,14 +617,14 @@ system.cpu.dcache.demand_misses::cpu.data 193 # n system.cpu.dcache.demand_misses::total 193 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 193 # number of overall misses system.cpu.dcache.overall_misses::total 193 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10226000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10226000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7070500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7070500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17296500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17296500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17296500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17296500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10224000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10224000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7069500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7069500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17293500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17293500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17293500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17293500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1778 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1778 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) @@ -641,14 +641,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.071139 system.cpu.dcache.demand_miss_rate::total 0.071139 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.071139 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.071139 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87401.709402 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 87401.709402 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93032.894737 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 93032.894737 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 89619.170984 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 89619.170984 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 89619.170984 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 89619.170984 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87384.615385 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 87384.615385 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93019.736842 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 93019.736842 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 89603.626943 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 89603.626943 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 89603.626943 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 89603.626943 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -669,14 +669,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6448000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6448000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6994500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6994500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13442500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13442500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13442500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13442500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6446000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6446000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6993500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6993500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13439500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13439500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13439500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13439500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036558 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036558 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses @@ -685,24 +685,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051972 system.cpu.dcache.demand_mshr_miss_rate::total 0.051972 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051972 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.051972 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 99200 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 99200 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 92032.894737 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92032.894737 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 95336.879433 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 95336.879433 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 95336.879433 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 95336.879433 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 99169.230769 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 99169.230769 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 92019.736842 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 92019.736842 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 95315.602837 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 95315.602837 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 95315.602837 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 95315.602837 # average overall mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 130.260906 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 130.259615 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1641 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 278 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 5.902878 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 130.260906 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063604 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063604 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 130.259615 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.063603 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063603 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 278 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id @@ -722,12 +722,12 @@ system.cpu.icache.demand_misses::cpu.inst 385 # n system.cpu.icache.demand_misses::total 385 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 385 # number of overall misses system.cpu.icache.overall_misses::total 385 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30146000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30146000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30146000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30146000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30146000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30146000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30145000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30145000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30145000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30145000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30145000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30145000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2026 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2026 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2026 # number of demand (read+write) accesses @@ -740,12 +740,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.190030 system.cpu.icache.demand_miss_rate::total 0.190030 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.190030 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.190030 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78301.298701 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 78301.298701 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 78301.298701 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 78301.298701 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 78301.298701 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 78301.298701 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78298.701299 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 78298.701299 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 78298.701299 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 78298.701299 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 78298.701299 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 78298.701299 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 171 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -764,33 +764,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 278 system.cpu.icache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 278 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23206500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23206500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23206500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23206500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23206500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23206500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23205500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23205500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23205500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23205500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23205500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23205500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.137216 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.137216 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.137216 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.137216 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83476.618705 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83476.618705 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83476.618705 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 83476.618705 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83476.618705 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 83476.618705 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83473.021583 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83473.021583 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83473.021583 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 83473.021583 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83473.021583 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 83473.021583 # average overall mshr miss latency system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 211.897546 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 211.895854 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 418 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002392 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.293933 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 81.603612 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.292642 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 81.603212 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003976 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.002490 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006467 # Average percentage of cache occupancy @@ -819,18 +819,18 @@ system.cpu.l2cache.demand_misses::total 418 # nu system.cpu.l2cache.overall_misses::cpu.inst 277 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses system.cpu.l2cache.overall_misses::total 418 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6880500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6880500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22777500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 22777500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6350000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6350000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22777500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13230500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 36008000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22777500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13230500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 36008000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6879500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6879500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22776500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 22776500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6348000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6348000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22776500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13227500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 36004000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22776500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13227500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 36004000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 278 # number of ReadCleanReq accesses(hits+misses) @@ -855,18 +855,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.997613 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996403 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997613 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90532.894737 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90532.894737 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82229.241877 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82229.241877 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97692.307692 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 97692.307692 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82229.241877 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93833.333333 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 86143.540670 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82229.241877 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93833.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 86143.540670 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90519.736842 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90519.736842 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82225.631769 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82225.631769 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97661.538462 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 97661.538462 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82225.631769 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93812.056738 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86133.971292 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82225.631769 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93812.056738 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86133.971292 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -885,18 +885,18 @@ system.cpu.l2cache.demand_mshr_misses::total 418 system.cpu.l2cache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 418 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6120500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6120500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20007500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20007500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5700000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5700000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20007500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11820500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 31828000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20007500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11820500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 31828000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6119500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6119500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20006500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20006500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5698000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5698000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20006500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11817500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 31824000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20006500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11817500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31824000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for ReadCleanReq accesses @@ -909,18 +909,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997613 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997613 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80532.894737 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80532.894737 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72229.241877 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72229.241877 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87692.307692 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87692.307692 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72229.241877 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83833.333333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76143.540670 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72229.241877 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83833.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76143.540670 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80519.736842 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80519.736842 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72225.631769 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72225.631769 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87661.538462 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87661.538462 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72225.631769 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83812.056738 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76133.971292 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72225.631769 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83812.056738 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76133.971292 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 419 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |