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authorMitch Hayenga <mitch.hayenga+gem5@gmail.com>2013-03-27 18:36:09 -0500
committerMitch Hayenga <mitch.hayenga+gem5@gmail.com>2013-03-27 18:36:09 -0500
commit4920f0d7e5a4c29ada074bf3a73f36510e138016 (patch)
tree5c3f5a730dce39a62111a09240a63a95645aa090 /tests/quick/se/00.hello/ref
parentf0b745d556a937607652e536338a4bc6f30480e5 (diff)
downloadgem5-4920f0d7e5a4c29ada074bf3a73f36510e138016.tar.xz
mem: Fix cache latency bug
Fixes a latency calculation bug for accesses during a cache line fill. Under a cache miss, before the line is filled, accesses to the cache are associated with a MSHR and marked as targets. Once the line fill completes, MSHR target packets pay an additional latency of "responseLatency + busSerializationLatency". However, the "whenReady" field of the cache line is only set to an additional delay of "busSerializationLatency". This lacks the responseLatency component of the fill. It is possible for accesses that occur on the cycle of (or briefly after) the line fill to respond without properly paying the responseLatency. This also creates the situation where two accesses to the same address may be serviced in an order opposite of how they were received by the cache. For stores to the same address, this means that although the cache performs the stores in the order they were received, acknowledgements may be sent in a different order. Adding the responseLatency component to the whenReady field preserves the penalty that should be paid and prevents these ordering issues. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
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