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authorNilay Vaish <nilay@cs.wisc.edu>2012-09-11 09:34:40 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2012-09-11 09:34:40 -0500
commitfe5deb4a22260b3e67839fb1efa978cff51e79ba (patch)
treed8768dfdaccd6beed5a95fa2b3d305b9f018d7e9 /tests/quick/se/00.hello/ref
parentf47c2f64156ee031c481af8d1516ada9d19da775 (diff)
downloadgem5-fe5deb4a22260b3e67839fb1efa978cff51e79ba.tar.xz
x86 Regressions: Update stats due to register predication
Diffstat (limited to 'tests/quick/se/00.hello/ref')
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini13
-rwxr-xr-xtests/quick/se/00.hello/ref/x86/linux/o3-timing/simout10
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt899
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini10
-rwxr-xr-xtests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout8
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt14
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini2
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats22
-rwxr-xr-xtests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout4
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt14
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini13
-rwxr-xr-xtests/quick/se/00.hello/ref/x86/linux/simple-timing/simout8
-rw-r--r--tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt14
13 files changed, 527 insertions, 504 deletions
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
index 5085616c4..6978d28ee 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
@@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -95,7 +96,6 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
-phase=0
predType=tournament
profile=0
progress_interval=0
@@ -129,6 +129,7 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=1
forward_snoops=true
hash_delay=1
is_top_level=true
@@ -157,6 +158,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
+clock=1
system=system
port=system.cpu.toL2Bus.slave[3]
@@ -428,6 +430,7 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=1
forward_snoops=true
hash_delay=1
is_top_level=true
@@ -450,9 +453,10 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=X86LocalApic
+clock=1
int_latency=1000
pio_addr=2305843009213693952
-pio_latency=1000
+pio_latency=100000
system=system
int_master=system.membus.slave[2]
int_slave=system.membus.master[2]
@@ -466,6 +470,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
+clock=1
system=system
port=system.cpu.toL2Bus.slave[2]
@@ -474,6 +479,7 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=1
forward_snoops=true
hash_delay=1
is_top_level=false
@@ -515,7 +521,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+executable=tests/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -538,6 +544,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
[system.physmem]
type=SimpleMemory
+clock=1
conf_table_reported=false
file=
in_addr_map=true
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
index f4d9273f5..1bec04837 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
@@ -1,11 +1,13 @@
+Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 17:08:22
-gem5 started Aug 13 2012 18:22:30
-gem5 executing on zizzer
+gem5 compiled Sep 10 2012 21:50:34
+gem5 started Sep 10 2012 21:50:39
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 12789500 because target called exit()
+Exiting @ tick 12607000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
index 89fb2bf27..1be5d9ebb 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
@@ -1,272 +1,271 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000013 # Number of seconds simulated
-sim_ticks 12789500 # Number of ticks simulated
-final_tick 12789500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 12607000 # Number of ticks simulated
+final_tick 12607000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 20973 # Simulator instruction rate (inst/s)
-host_op_rate 37987 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 49851854 # Simulator tick rate (ticks/s)
-host_mem_usage 232356 # Number of bytes of host memory used
+host_inst_rate 20393 # Simulator instruction rate (inst/s)
+host_op_rate 36936 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 47780701 # Simulator tick rate (ticks/s)
+host_mem_usage 271708 # Number of bytes of host memory used
host_seconds 0.26 # Real time elapsed on the host
sim_insts 5380 # Number of instructions simulated
sim_ops 9745 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19456 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9280 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28736 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9216 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28672 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 304 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 145 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 449 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1521247899 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 725595215 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2246843113 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1521247899 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1521247899 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1521247899 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 725595215 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2246843113 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::cpu.data 144 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 448 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1543269612 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 731022448 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2274292060 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1543269612 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1543269612 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1543269612 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 731022448 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2274292060 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 11 # Number of system calls
-system.cpu.numCycles 25580 # number of cpu cycles simulated
+system.cpu.numCycles 25215 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 3138 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 3138 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 562 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 2607 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 814 # Number of BTB hits
+system.cpu.BPredUnit.lookups 3186 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 3186 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 582 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 2623 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 777 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 8037 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 15123 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 3138 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 814 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 4093 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 2492 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 3369 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 178 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 17601 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.521504 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.991998 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 8059 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 15139 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 3186 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 777 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 4132 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 2534 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 3329 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 20 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 126 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 1963 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 17595 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.538335 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.007747 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 13611 77.33% 77.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 183 1.04% 78.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 154 0.87% 79.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 201 1.14% 80.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 179 1.02% 81.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 174 0.99% 82.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 262 1.49% 83.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 168 0.95% 84.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 2669 15.16% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 13576 77.16% 77.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 181 1.03% 78.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 155 0.88% 79.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 205 1.17% 80.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 167 0.95% 81.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 166 0.94% 82.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 255 1.45% 83.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 187 1.06% 84.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 2703 15.36% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 17601 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.122674 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.591204 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 8517 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 3363 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 3698 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1897 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 25566 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 1897 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 8847 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 2031 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 471 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 3459 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 896 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 24019 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 44 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 760 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 34373 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 69151 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 69135 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 17595 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.126353 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.600397 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 8491 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 3340 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 3724 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 111 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1929 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 25781 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 1929 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 8836 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 2060 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 411 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 3455 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 904 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 24174 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 9 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 13 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 785 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 26591 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 58087 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 58071 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 14595 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 19778 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 35 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 35 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 1918 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2391 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1803 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 21439 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 41 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 17729 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 95 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 11045 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 19872 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 17601 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.007272 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.841273 # Number of insts issued each cycle
+system.cpu.rename.CommittedMaps 11060 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 15531 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 32 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 32 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 2042 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2405 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1780 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 21436 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 18052 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 228 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 10867 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 14920 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 17595 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.025973 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.871104 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 12034 68.37% 68.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1562 8.87% 77.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 1007 5.72% 82.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 685 3.89% 86.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 692 3.93% 90.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 711 4.04% 94.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 630 3.58% 98.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 245 1.39% 99.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 35 0.20% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 12050 68.49% 68.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1507 8.56% 77.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 947 5.38% 82.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 676 3.84% 86.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 766 4.35% 90.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 693 3.94% 94.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 642 3.65% 98.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 270 1.53% 99.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 44 0.25% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 17601 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 17595 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 137 74.46% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 74.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 28 15.22% 89.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 19 10.33% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 141 77.47% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 21 11.54% 89.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 20 10.99% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 14250 80.38% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.40% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 1990 11.22% 91.62% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1485 8.38% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 14462 80.11% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.14% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2078 11.51% 91.65% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1508 8.35% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 17729 # Type of FU issued
-system.cpu.iq.rate 0.693081 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 184 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.010378 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 53330 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 32532 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 16277 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 18052 # Type of FU issued
+system.cpu.iq.rate 0.715923 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 182 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.010082 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 54101 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 32345 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 16592 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 17905 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 18226 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 157 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 132 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1339 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 20 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 869 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1353 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 19 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 846 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1897 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1429 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 34 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 21480 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 37 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2391 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1803 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 1929 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1486 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 21473 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 34 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2405 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1780 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 631 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 699 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 16697 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 1851 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1032 # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 642 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 708 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 17072 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 1925 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 980 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 3217 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1636 # Number of branches executed
-system.cpu.iew.exec_stores 1366 # Number of stores executed
-system.cpu.iew.exec_rate 0.652737 # Inst execution rate
-system.cpu.iew.wb_sent 16474 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 16281 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 10466 # num instructions producing a value
-system.cpu.iew.wb_consumers 23993 # num instructions consuming a value
+system.cpu.iew.exec_refs 3318 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1690 # Number of branches executed
+system.cpu.iew.exec_stores 1393 # Number of stores executed
+system.cpu.iew.exec_rate 0.677057 # Inst execution rate
+system.cpu.iew.wb_sent 16795 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 16596 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 10614 # num instructions producing a value
+system.cpu.iew.wb_consumers 16437 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.636474 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.436211 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.658180 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.645738 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 5380 # The number of committed instructions
system.cpu.commit.commitCommittedOps 9745 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 11734 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 11727 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 583 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 15704 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.620543 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.459156 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 596 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 15666 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.622048 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.485565 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 11988 76.34% 76.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1532 9.76% 86.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 562 3.58% 89.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 734 4.67% 94.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 373 2.38% 96.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 129 0.82% 97.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 134 0.85% 98.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 70 0.45% 98.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 182 1.16% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 12031 76.80% 76.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1491 9.52% 86.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 525 3.35% 89.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 708 4.52% 94.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 369 2.36% 96.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 134 0.86% 97.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 127 0.81% 98.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 76 0.49% 98.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 205 1.31% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 15704 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 15666 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5380 # Number of instructions committed
system.cpu.commit.committedOps 9745 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -277,68 +276,68 @@ system.cpu.commit.branches 1208 # Nu
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 9650 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
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@@ -347,94 +346,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
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@@ -443,56 +442,56 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996721 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.997778 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.997773 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996721 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.997778 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32832.236842 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35297.101449 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33288.203753 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33440.789474 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33440.789474 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32832.236842 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34324.137931 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33314.031180 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32832.236842 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34324.137931 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33314.031180 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.997773 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32927.631579 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35845.588235 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33461.021505 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33315.789474 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33315.789474 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32927.631579 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34510.416667 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33436.383929 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32927.631579 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34510.416667 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33436.383929 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
index 1c047bcde..d417ce700 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
@@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -48,7 +49,6 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
@@ -68,14 +68,16 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
+clock=1
system=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=X86LocalApic
+clock=1
int_latency=1000
pio_addr=2305843009213693952
-pio_latency=1000
+pio_latency=100000
system=system
int_master=system.membus.slave[5]
int_slave=system.membus.master[2]
@@ -89,6 +91,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
+clock=1
system=system
port=system.membus.slave[3]
@@ -103,7 +106,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+executable=tests/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -126,6 +129,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
[system.physmem]
type=SimpleMemory
+clock=1
conf_table_reported=false
file=
in_addr_map=true
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
index 2878f37c1..a8facaf1f 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic/simout
+Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 17:08:22
-gem5 started Aug 13 2012 18:22:41
-gem5 executing on zizzer
+gem5 compiled Sep 10 2012 21:50:34
+gem5 started Sep 10 2012 21:50:39
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
index 288f81674..67f89709c 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000006 # Nu
sim_ticks 5614000 # Number of ticks simulated
final_tick 5614000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 93021 # Simulator instruction rate (inst/s)
-host_op_rate 168430 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 96993365 # Simulator tick rate (ticks/s)
-host_mem_usage 222752 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 59958 # Simulator instruction rate (inst/s)
+host_op_rate 108572 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 62528382 # Simulator tick rate (ticks/s)
+host_mem_usage 261084 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9746 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory
@@ -45,8 +45,8 @@ system.cpu.num_func_calls 0 # nu
system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls
system.cpu.num_int_insts 9651 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 29744 # number of times the integer registers were read
-system.cpu.num_int_register_writes 14595 # number of times the integer registers were written
+system.cpu.num_int_register_reads 24812 # number of times the integer registers were read
+system.cpu.num_int_register_writes 11060 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 1986 # number of memory refs
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
index 09c807544..8e358d7bf 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
@@ -73,7 +73,7 @@ type=X86LocalApic
clock=1
int_latency=1
pio_addr=2305843009213693952
-pio_latency=1
+pio_latency=100
system=system
int_master=system.l1_cntrl0.sequencer.slave[4]
int_slave=system.l1_cntrl0.sequencer.master[1]
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
index cd9956361..5f61ae7e1 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
@@ -1,4 +1,4 @@
-Real time: Sep/09/2012 13:51:25
+Real time: Sep/10/2012 21:50:40
Profiler Stats
--------------
@@ -7,18 +7,18 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.53
-Virtual_time_in_minutes: 0.00883333
-Virtual_time_in_hours: 0.000147222
-Virtual_time_in_days: 6.13426e-06
+Virtual_time_in_seconds: 0.48
+Virtual_time_in_minutes: 0.008
+Virtual_time_in_hours: 0.000133333
+Virtual_time_in_days: 5.55556e-06
Ruby_current_time: 121759
Ruby_start_time: 0
Ruby_cycles: 121759
-mbytes_resident: 59.5742
-mbytes_total: 275.16
-resident_ratio: 0.216522
+mbytes_resident: 57.9453
+mbytes_total: 275.082
+resident_ratio: 0.210662
ruby_cycles_executed: [ 121760 ]
@@ -89,11 +89,11 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 11362
+page_reclaims: 11940
page_faults: 0
swaps: 0
-block_inputs: 0
-block_outputs: 80
+block_inputs: 24
+block_outputs: 88
Network Stats
-------------
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
index 290b12614..33d7b7dce 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-tim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 9 2012 13:51:17
-gem5 started Sep 9 2012 13:51:25
+gem5 compiled Sep 10 2012 21:50:34
+gem5 started Sep 10 2012 21:50:39
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
index 5b3d1f38b..6f7115490 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000122 # Nu
sim_ticks 121759 # Number of ticks simulated
final_tick 121759 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 4061 # Simulator instruction rate (inst/s)
-host_op_rate 7355 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 91887 # Simulator tick rate (ticks/s)
-host_mem_usage 243480 # Number of bytes of host memory used
-host_seconds 1.33 # Real time elapsed on the host
+host_inst_rate 21174 # Simulator instruction rate (inst/s)
+host_op_rate 38347 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 479042 # Simulator tick rate (ticks/s)
+host_mem_usage 281688 # Number of bytes of host memory used
+host_seconds 0.25 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9746 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory
@@ -51,8 +51,8 @@ system.cpu.num_func_calls 0 # nu
system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls
system.cpu.num_int_insts 9651 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 29744 # number of times the integer registers were read
-system.cpu.num_int_register_writes 14595 # number of times the integer registers were written
+system.cpu.num_int_register_reads 24812 # number of times the integer registers were read
+system.cpu.num_int_register_writes 11060 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 1986 # number of memory refs
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
index 3f04b065a..e0483161d 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -47,7 +48,6 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
system=system
@@ -61,6 +61,7 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=1
forward_snoops=true
hash_delay=1
is_top_level=true
@@ -89,6 +90,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
+clock=1
system=system
port=system.cpu.toL2Bus.slave[3]
@@ -97,6 +99,7 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=1
forward_snoops=true
hash_delay=1
is_top_level=true
@@ -119,9 +122,10 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=X86LocalApic
+clock=1
int_latency=1000
pio_addr=2305843009213693952
-pio_latency=1000
+pio_latency=100000
system=system
int_master=system.membus.slave[2]
int_slave=system.membus.master[2]
@@ -135,6 +139,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
+clock=1
system=system
port=system.cpu.toL2Bus.slave[2]
@@ -143,6 +148,7 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=1
forward_snoops=true
hash_delay=1
is_top_level=false
@@ -184,7 +190,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
+executable=tests/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -207,6 +213,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
[system.physmem]
type=SimpleMemory
+clock=1
conf_table_reported=false
file=
in_addr_map=true
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
index 4ca1a9d26..6c9c7da05 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing/simout
+Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 17:08:22
-gem5 started Aug 13 2012 18:22:51
-gem5 executing on zizzer
+gem5 compiled Sep 10 2012 21:50:34
+gem5 started Sep 10 2012 21:50:39
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
index c89020746..c50a3998a 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000030 # Nu
sim_ticks 29676000 # Number of ticks simulated
final_tick 29676000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 192246 # Simulator instruction rate (inst/s)
-host_op_rate 347982 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1058982197 # Simulator tick rate (ticks/s)
-host_mem_usage 231200 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
+host_inst_rate 72347 # Simulator instruction rate (inst/s)
+host_op_rate 131001 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 398795084 # Simulator tick rate (ticks/s)
+host_mem_usage 269536 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9746 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory
@@ -39,8 +39,8 @@ system.cpu.num_func_calls 0 # nu
system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls
system.cpu.num_int_insts 9651 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 29744 # number of times the integer registers were read
-system.cpu.num_int_register_writes 14595 # number of times the integer registers were written
+system.cpu.num_int_register_reads 24812 # number of times the integer registers were read
+system.cpu.num_int_register_writes 11060 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_mem_refs 1986 # number of memory refs