diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-15 08:14:09 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-15 08:14:09 -0500 |
| commit | 0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e (patch) | |
| tree | 45d559d0511bdca749a08a2f42eeafdcf25739cf /tests/quick/se/00.hello/ref | |
| parent | 3de9def6c1ad38d6a5068b07512cbefffafcb758 (diff) | |
| download | gem5-0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e.tar.xz | |
stats: updates due to recent changesets including d0934b57735a
Diffstat (limited to 'tests/quick/se/00.hello/ref')
22 files changed, 3797 insertions, 3807 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index b5554ceae..1a6e00d22 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000038 # Number of seconds simulated -sim_ticks 37623000 # Number of ticks simulated -final_tick 37623000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 37552000 # Number of ticks simulated +final_tick 37552000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152308 # Simulator instruction rate (inst/s) -host_op_rate 152258 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 894784408 # Simulator tick rate (ticks/s) -host_mem_usage 293572 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 72134 # Simulator instruction rate (inst/s) +host_op_rate 72118 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 423067865 # Simulator tick rate (ticks/s) +host_mem_usage 288748 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 6400 # Number of instructions simulated sim_ops 6400 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 23296 # Nu system.physmem.num_reads::cpu.inst 364 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory system.physmem.num_reads::total 533 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 619195705 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 287483720 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 906679425 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 619195705 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 619195705 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 619195705 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 287483720 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 906679425 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 620366425 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 288027269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 908393694 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 620366425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 620366425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 620366425 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 288027269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 908393694 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 533 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 37518500 # Total gap between requests +system.physmem.totGap 37447500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -188,8 +188,8 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 84 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 384 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 247.494057 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.812732 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 247.290862 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.108272 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 20 23.81% 23.81% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 19 22.62% 46.43% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 10 11.90% 58.33% # Bytes accessed per row activation @@ -200,19 +200,19 @@ system.physmem.bytesPerActivate::768-895 3 3.57% 83.33% # By system.physmem.bytesPerActivate::896-1023 6 7.14% 90.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 8 9.52% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 84 # Bytes accessed per row activation -system.physmem.totQLat 3336750 # Total ticks spent queuing -system.physmem.totMemAccLat 13330500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3307750 # Total ticks spent queuing +system.physmem.totMemAccLat 13301500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6260.32 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6205.91 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25010.32 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 906.68 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24955.91 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 908.39 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 906.68 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 908.39 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.08 # Data bus utilization in percentage -system.physmem.busUtilRead 7.08 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.10 # Data bus utilization in percentage +system.physmem.busUtilRead 7.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,7 +220,7 @@ system.physmem.readRowHits 437 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 70391.18 # Average gap between requests +system.physmem.avgGap 70257.97 # Average gap between requests system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 226800 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 123750 # Energy for precharge commands per rank (pJ) @@ -231,32 +231,32 @@ system.physmem_0.actBackEnergy 21178350 # En system.physmem_0.preBackEnergy 265500 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 25872240 # Total energy per rank (pJ) system.physmem_0.averagePower 823.825505 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 435750 # Time in different power states +system.physmem_0.memoryStateTime::IDLE 346000 # Time in different power states system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 30032750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 347760 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 189750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1544400 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 1552200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 20558475 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 809250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 25483875 # Total energy per rank (pJ) -system.physmem_1.averagePower 811.459163 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1209750 # Time in different power states +system.physmem_1.actBackEnergy 20535390 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 831750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 25491090 # Total energy per rank (pJ) +system.physmem_1.averagePower 811.591993 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1333500 # Time in different power states system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 29169000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 29134000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1965 # Number of BP lookups -system.cpu.branchPred.condPredicted 1205 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1556 # Number of BTB lookups -system.cpu.branchPred.BTBHits 382 # Number of BTB hits +system.cpu.branchPred.lookups 1929 # Number of BP lookups +system.cpu.branchPred.condPredicted 1187 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 360 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1557 # Number of BTB lookups +system.cpu.branchPred.BTBHits 398 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 24.550129 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 25.561978 # BTB Hit Percentage system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -264,22 +264,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1371 # DTB read hits +system.cpu.dtb.read_hits 1369 # DTB read hits system.cpu.dtb.read_misses 11 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1382 # DTB read accesses +system.cpu.dtb.read_accesses 1380 # DTB read accesses system.cpu.dtb.write_hits 884 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 887 # DTB write accesses -system.cpu.dtb.data_hits 2255 # DTB hits +system.cpu.dtb.data_hits 2253 # DTB hits system.cpu.dtb.data_misses 14 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2269 # DTB accesses -system.cpu.itb.fetch_hits 2639 # ITB hits +system.cpu.dtb.data_accesses 2267 # DTB accesses +system.cpu.itb.fetch_hits 2651 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2656 # ITB accesses +system.cpu.itb.fetch_accesses 2668 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,40 +293,40 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 75246 # number of cpu cycles simulated +system.cpu.numCycles 75104 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6400 # Number of instructions committed system.cpu.committedOps 6400 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1115 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1085 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 11.757188 # CPI: cycles per instruction -system.cpu.ipc 0.085054 # IPC: instructions per cycle -system.cpu.tickCycles 12577 # Number of cycles that the object actually ticked -system.cpu.idleCycles 62669 # Total number of cycles that the object has spent stopped +system.cpu.cpi 11.735000 # CPI: cycles per instruction +system.cpu.ipc 0.085215 # IPC: instructions per cycle +system.cpu.tickCycles 12517 # Number of cycles that the object actually ticked +system.cpu.idleCycles 62587 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.998872 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1975 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 103.919220 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1972 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.686391 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.668639 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.998872 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025390 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025390 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.919220 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025371 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025371 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4573 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4573 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1235 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1235 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4567 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4567 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1232 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1232 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1975 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1975 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1975 # number of overall hits -system.cpu.dcache.overall_hits::total 1975 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1972 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1972 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1972 # number of overall hits +system.cpu.dcache.overall_hits::total 1972 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 102 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 125 # number of WriteReq misses @@ -335,38 +335,38 @@ system.cpu.dcache.demand_misses::cpu.data 227 # n system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 227 # number of overall misses system.cpu.dcache.overall_misses::total 227 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8109500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8109500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9137500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9137500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17247000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17247000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17247000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17247000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1337 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1337 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8311500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8311500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9136500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9136500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17448000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17448000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17448000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17448000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1334 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1334 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2202 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2202 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2202 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2202 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076290 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.076290 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2199 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2199 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2199 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2199 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076462 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076462 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.144509 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.103088 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.103088 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.103088 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.103088 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79504.901961 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 79504.901961 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73100 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73100 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75977.973568 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75977.973568 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75977.973568 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75977.973568 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.103229 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.103229 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.103229 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.103229 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81485.294118 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 81485.294118 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73092 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73092 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76863.436123 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76863.436123 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76863.436123 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76863.436123 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -391,82 +391,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 169 system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7616500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7616500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5372000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5372000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12988500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12988500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12988500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12988500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071803 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071803 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7818500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7818500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5371500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5371500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13190000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13190000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13190000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13190000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071964 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071964 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076748 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076748 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076748 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076748 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79338.541667 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79338.541667 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73589.041096 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73589.041096 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76855.029586 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76855.029586 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76855.029586 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76855.029586 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076853 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076853 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076853 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076853 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81442.708333 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81442.708333 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73582.191781 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73582.191781 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78047.337278 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78047.337278 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78047.337278 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78047.337278 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 175.991805 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2274 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 175.811080 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 2286 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.230137 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.263014 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 175.991805 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.085933 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.085933 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 175.811080 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.085845 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.085845 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 5643 # Number of tag accesses -system.cpu.icache.tags.data_accesses 5643 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 2274 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2274 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2274 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2274 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2274 # number of overall hits -system.cpu.icache.overall_hits::total 2274 # number of overall hits +system.cpu.icache.tags.tag_accesses 5667 # Number of tag accesses +system.cpu.icache.tags.data_accesses 5667 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 2286 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2286 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2286 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2286 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2286 # number of overall hits +system.cpu.icache.overall_hits::total 2286 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28165000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28165000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28165000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28165000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28165000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28165000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2639 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2639 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2639 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2639 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2639 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2639 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138310 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.138310 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.138310 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.138310 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.138310 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.138310 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77164.383562 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77164.383562 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77164.383562 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77164.383562 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77164.383562 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77164.383562 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 27931500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 27931500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 27931500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 27931500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 27931500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 27931500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2651 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2651 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2651 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2651 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2651 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2651 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.137684 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.137684 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.137684 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.137684 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.137684 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.137684 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76524.657534 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76524.657534 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76524.657534 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76524.657534 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76524.657534 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76524.657534 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,39 +481,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365 system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27800000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27800000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27800000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27800000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27800000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27800000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138310 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.138310 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.138310 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76164.383562 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76164.383562 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76164.383562 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 76164.383562 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76164.383562 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 76164.383562 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27566500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27566500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27566500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27566500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27566500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27566500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.137684 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.137684 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.137684 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75524.657534 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75524.657534 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75524.657534 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75524.657534 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75524.657534 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75524.657534 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 233.662872 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 233.447652 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 176.005347 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.657524 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005371 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001760 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007131 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.824515 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.623137 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005366 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001759 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007124 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014038 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4805 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4805 # Number of data accesses @@ -535,18 +535,18 @@ system.cpu.l2cache.demand_misses::total 533 # nu system.cpu.l2cache.overall_misses::cpu.inst 364 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses system.cpu.l2cache.overall_misses::total 533 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5261500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5261500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27241500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 27241500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7471000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7471000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27241500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12732500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 39974000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27241500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12732500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 39974000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5261000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5261000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27008000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 27008000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7673000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7673000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27008000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12934000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 39942000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27008000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12934000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 39942000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 365 # number of ReadCleanReq accesses(hits+misses) @@ -571,18 +571,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.998127 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997260 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72075.342466 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72075.342466 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74839.285714 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74839.285714 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77822.916667 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77822.916667 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74839.285714 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75340.236686 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74998.123827 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74839.285714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75340.236686 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74998.123827 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72068.493151 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72068.493151 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74197.802198 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74197.802198 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79927.083333 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79927.083333 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74197.802198 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76532.544379 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74938.086304 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74197.802198 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76532.544379 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74938.086304 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -603,18 +603,18 @@ system.cpu.l2cache.demand_mshr_misses::total 533 system.cpu.l2cache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4531500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4531500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23601500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23601500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6511000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6511000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23601500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11042500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 34644000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23601500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11042500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 34644000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4531000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4531000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23368000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23368000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6713000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6713000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23368000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11244000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 34612000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23368000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11244000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 34612000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for ReadCleanReq accesses @@ -627,18 +627,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62075.342466 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62075.342466 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64839.285714 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64839.285714 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67822.916667 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67822.916667 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64839.285714 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65340.236686 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64998.123827 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64839.285714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65340.236686 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64998.123827 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62068.493151 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62068.493151 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64197.802198 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64197.802198 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69927.083333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69927.083333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64197.802198 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66532.544379 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64938.086304 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64197.802198 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66532.544379 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64938.086304 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -688,7 +688,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 533 # Request fanout histogram -system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 602500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) system.membus.respLayer1.occupancy 2833000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 7.5 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index 5a166e70e..7f87c40d6 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 22 2015 07:55:25 -gem5 started Apr 22 2015 08:11:59 -gem5 executing on phenom -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing +gem5 compiled Sep 14 2015 20:54:01 +gem5 started Sep 14 2015 21:14:59 +gem5 executing on ribera.cs.wisc.edu +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 22074000 because target called exit() +Exiting @ tick 21900500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 96f652b92..85a8b430a 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,51 +1,51 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 21947000 # Number of ticks simulated -final_tick 21947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21900500 # Number of ticks simulated +final_tick 21900500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95577 # Simulator instruction rate (inst/s) -host_op_rate 95558 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 329070081 # Simulator tick rate (ticks/s) -host_mem_usage 294868 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 43231 # Simulator instruction rate (inst/s) +host_op_rate 43225 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 148545474 # Simulator tick rate (ticks/s) +host_mem_usage 289772 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory -system.physmem.bytes_read::total 31104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory -system.physmem.num_reads::total 486 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 912744339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 504488085 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1417232424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 912744339 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 912744339 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 912744339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 504488085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1417232424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 486 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 19840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10944 # Number of bytes read from this memory +system.physmem.bytes_read::total 30784 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19840 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 310 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 171 # Number of read requests responded to by this memory +system.physmem.num_reads::total 481 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 905915390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 499714618 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1405630008 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 905915390 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 905915390 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 905915390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 499714618 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1405630008 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 481 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 486 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 481 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 31104 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 30784 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 31104 # Total read bytes from the system interface side +system.physmem.bytesReadSys 30784 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 69 # Per bank write bursts -system.physmem.perBankRdBursts::1 33 # Per bank write bursts +system.physmem.perBankRdBursts::0 68 # Per bank write bursts +system.physmem.perBankRdBursts::1 32 # Per bank write bursts system.physmem.perBankRdBursts::2 32 # Per bank write bursts system.physmem.perBankRdBursts::3 47 # Per bank write bursts -system.physmem.perBankRdBursts::4 42 # Per bank write bursts +system.physmem.perBankRdBursts::4 41 # Per bank write bursts system.physmem.perBankRdBursts::5 20 # Per bank write bursts system.physmem.perBankRdBursts::6 1 # Per bank write bursts system.physmem.perBankRdBursts::7 3 # Per bank write bursts @@ -54,7 +54,7 @@ system.physmem.perBankRdBursts::9 1 # Pe system.physmem.perBankRdBursts::10 22 # Per bank write bursts system.physmem.perBankRdBursts::11 25 # Per bank write bursts system.physmem.perBankRdBursts::12 14 # Per bank write bursts -system.physmem.perBankRdBursts::13 120 # Per bank write bursts +system.physmem.perBankRdBursts::13 118 # Per bank write bursts system.physmem.perBankRdBursts::14 45 # Per bank write bursts system.physmem.perBankRdBursts::15 12 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21815000 # Total gap between requests +system.physmem.totGap 21763000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 486 # Read request sizes (log2) +system.physmem.readPktSize::6 481 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 138 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 270 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,99 +186,99 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 81 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 332.641975 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 207.725130 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 321.981029 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 25 30.86% 30.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18 22.22% 53.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 11.11% 64.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 9 11.11% 75.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 6 7.41% 82.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 1.23% 83.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 3.70% 87.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 12.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 81 # Bytes accessed per row activation -system.physmem.totQLat 4379250 # Total ticks spent queuing -system.physmem.totMemAccLat 13491750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2430000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9010.80 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 337.822785 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.071445 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.417518 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21 26.58% 26.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22 27.85% 54.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 11.39% 65.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 9 11.39% 77.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 5.06% 82.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 1.27% 83.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 3.80% 87.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 12.66% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation +system.physmem.totQLat 3965000 # Total ticks spent queuing +system.physmem.totMemAccLat 12983750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2405000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8243.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27760.80 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1417.23 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26993.24 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1405.63 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1417.23 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1405.63 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.07 # Data bus utilization in percentage -system.physmem.busUtilRead 11.07 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.98 # Data bus utilization in percentage +system.physmem.busUtilRead 10.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 390 # Number of row buffer hits during reads +system.physmem.readRowHits 387 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.25 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.46 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 44886.83 # Average gap between requests -system.physmem.pageHitRate 80.25 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 219240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 119625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1653600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 45245.32 # Average gap between requests +system.physmem.pageHitRate 80.46 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1630200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 10785825 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 13833660 # Total energy per rank (pJ) -system.physmem_0.averagePower 873.750829 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states +system.physmem_0.totalEnergy 13775205 # Total energy per rank (pJ) +system.physmem_0.averagePower 870.058740 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 209750 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 325080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 177375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1271400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 317520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 173250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1287000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10129185 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 614250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13534410 # Total energy per rank (pJ) -system.physmem_1.averagePower 854.849834 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 953500 # Time in different power states +system.physmem_1.actBackEnergy 10183905 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 566250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13545045 # Total energy per rank (pJ) +system.physmem_1.averagePower 855.521554 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 873500 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14372750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14452750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2810 # Number of BP lookups -system.cpu.branchPred.condPredicted 1662 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 478 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2116 # Number of BTB lookups -system.cpu.branchPred.BTBHits 679 # Number of BTB hits +system.cpu.branchPred.lookups 2551 # Number of BP lookups +system.cpu.branchPred.condPredicted 1518 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 429 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1991 # Number of BTB lookups +system.cpu.branchPred.BTBHits 726 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.088847 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 396 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 36.464088 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 383 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 29 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2105 # DTB read hits -system.cpu.dtb.read_misses 55 # DTB read misses +system.cpu.dtb.read_hits 2033 # DTB read hits +system.cpu.dtb.read_misses 43 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2160 # DTB read accesses -system.cpu.dtb.write_hits 1074 # DTB write hits -system.cpu.dtb.write_misses 30 # DTB write misses +system.cpu.dtb.read_accesses 2076 # DTB read accesses +system.cpu.dtb.write_hits 1052 # DTB write hits +system.cpu.dtb.write_misses 28 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1104 # DTB write accesses -system.cpu.dtb.data_hits 3179 # DTB hits -system.cpu.dtb.data_misses 85 # DTB misses +system.cpu.dtb.write_accesses 1080 # DTB write accesses +system.cpu.dtb.data_hits 3085 # DTB hits +system.cpu.dtb.data_misses 71 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3264 # DTB accesses -system.cpu.itb.fetch_hits 2194 # ITB hits -system.cpu.itb.fetch_misses 34 # ITB misses +system.cpu.dtb.data_accesses 3156 # DTB accesses +system.cpu.itb.fetch_hits 2086 # ITB hits +system.cpu.itb.fetch_misses 32 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2228 # ITB accesses +system.cpu.itb.fetch_accesses 2118 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -292,237 +292,237 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 43895 # number of cpu cycles simulated +system.cpu.numCycles 43802 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8597 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16278 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2810 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1075 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4298 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1038 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 740 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2194 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14179 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.148036 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.557344 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 8360 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14953 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2551 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1109 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4527 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 940 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 730 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2086 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 308 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14111 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.059670 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.447373 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11320 79.84% 79.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 289 2.04% 81.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 216 1.52% 83.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 204 1.44% 84.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 243 1.71% 86.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 208 1.47% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 242 1.71% 89.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 175 1.23% 90.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1282 9.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11381 80.65% 80.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 309 2.19% 82.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 232 1.64% 84.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 210 1.49% 85.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 257 1.82% 87.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 204 1.45% 89.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 249 1.76% 91.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 144 1.02% 92.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1125 7.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14179 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.064016 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.370840 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8623 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2500 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2414 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 200 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 442 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 227 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14886 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 224 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 442 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8796 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1074 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 427 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2425 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1015 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14276 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 33 # Number of times rename has blocked due to LQ full +system.cpu.fetch.rateDist::total 14111 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.058239 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.341377 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8350 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2903 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2283 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 178 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 397 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 199 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 74 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 13658 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 213 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 397 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8499 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1362 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 551 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2297 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1005 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 13185 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 29 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 937 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 10794 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17927 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17918 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 9916 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 16517 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 16508 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6224 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 32 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 5346 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 538 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2680 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1315 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 571 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2513 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1264 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12940 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 12094 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10735 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6595 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3561 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 10150 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 8 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5749 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3122 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14179 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.757106 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.490778 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14111 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.719297 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.444291 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10173 71.75% 71.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1278 9.01% 80.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 898 6.33% 87.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 679 4.79% 91.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 528 3.72% 95.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 333 2.35% 97.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 209 1.47% 99.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 55 0.39% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 26 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10252 72.65% 72.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1258 8.92% 81.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 873 6.19% 87.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 669 4.74% 92.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 489 3.47% 95.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 327 2.32% 98.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 176 1.25% 99.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 44 0.31% 99.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 23 0.16% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14179 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14111 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 29 20.14% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 73 50.69% 70.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 42 29.17% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 18 13.64% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 73 55.30% 68.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 41 31.06% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7243 67.47% 67.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2356 21.95% 89.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1131 10.54% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 6822 67.21% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2214 21.81% 89.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1109 10.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10735 # Type of FU issued -system.cpu.iq.rate 0.244561 # Inst issue rate -system.cpu.iq.fu_busy_cnt 144 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013414 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 35792 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19571 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9784 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10150 # Type of FU issued +system.cpu.iq.rate 0.231725 # Inst issue rate +system.cpu.iq.fu_busy_cnt 132 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013005 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 34530 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 17879 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9316 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10866 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10269 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 71 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 64 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1497 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1330 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 450 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 399 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 65 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 71 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 442 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1033 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13054 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 109 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2680 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1315 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 397 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1267 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 12206 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2513 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1264 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 20 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 81 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 395 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 476 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10242 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2163 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 493 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 85 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 341 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 426 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 9752 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2076 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 86 # number of nop insts executed -system.cpu.iew.exec_refs 3269 # number of memory reference insts executed -system.cpu.iew.exec_branches 1598 # Number of branches executed -system.cpu.iew.exec_stores 1106 # Number of stores executed -system.cpu.iew.exec_rate 0.233330 # Inst execution rate -system.cpu.iew.wb_sent 9957 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9794 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5300 # num instructions producing a value -system.cpu.iew.wb_consumers 7297 # num instructions consuming a value +system.cpu.iew.exec_nop 84 # number of nop insts executed +system.cpu.iew.exec_refs 3158 # number of memory reference insts executed +system.cpu.iew.exec_branches 1540 # Number of branches executed +system.cpu.iew.exec_stores 1082 # Number of stores executed +system.cpu.iew.exec_rate 0.222638 # Inst execution rate +system.cpu.iew.wb_sent 9474 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9326 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4992 # num instructions producing a value +system.cpu.iew.wb_consumers 6833 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.223123 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.726326 # average fanout of values written-back +system.cpu.iew.wb_rate 0.212913 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.730572 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6664 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5821 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 401 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12978 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.492295 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.405132 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 356 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13063 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.489091 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.409393 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10520 81.06% 81.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1167 8.99% 90.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 504 3.88% 93.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 209 1.61% 95.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 136 1.05% 96.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 76 0.59% 97.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 89 0.69% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 87 0.67% 98.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 190 1.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10626 81.34% 81.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1163 8.90% 90.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 487 3.73% 93.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 202 1.55% 95.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 127 0.97% 96.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 82 0.63% 97.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 98 0.75% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 84 0.64% 98.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 194 1.49% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13063 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -568,186 +568,186 @@ system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 6389 # Class of committed instruction -system.cpu.commit.bw_lim_events 190 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 25490 # The number of ROB reads -system.cpu.rob.rob_writes 27321 # The number of ROB writes -system.cpu.timesIdled 258 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29716 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 194 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 24728 # The number of ROB reads +system.cpu.rob.rob_writes 25475 # The number of ROB writes +system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29691 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.888732 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.888732 # CPI: Total CPI of All Threads -system.cpu.ipc 0.145165 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.145165 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13013 # number of integer regfile reads -system.cpu.int_regfile_writes 7460 # number of integer regfile writes +system.cpu.cpi 6.874137 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.874137 # CPI: Total CPI of All Threads +system.cpu.ipc 0.145473 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.145473 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12362 # number of integer regfile reads +system.cpu.int_regfile_writes 7056 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 107.548347 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2343 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.543353 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 107.516544 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2276 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.309942 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 107.548347 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026257 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026257 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 107.516544 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026249 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026249 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 171 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5891 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5891 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1835 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1835 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 508 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 508 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2343 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2343 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2343 # number of overall hits -system.cpu.dcache.overall_hits::total 2343 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 159 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 159 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 357 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 357 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 516 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 516 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 516 # number of overall misses -system.cpu.dcache.overall_misses::total 516 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11993500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11993500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24175975 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24175975 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 36169475 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 36169475 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 36169475 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 36169475 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1994 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1994 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_task_id_percent::1024 0.041748 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5747 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5747 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1770 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1770 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2276 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2276 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2276 # number of overall hits +system.cpu.dcache.overall_hits::total 2276 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 153 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 153 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 512 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 512 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 512 # number of overall misses +system.cpu.dcache.overall_misses::total 512 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11315000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11315000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23651475 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23651475 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34966475 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34966475 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34966475 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34966475 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1923 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1923 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2859 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2859 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2859 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2859 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079739 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.079739 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412717 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.412717 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.180483 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.180483 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.180483 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.180483 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75430.817610 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75430.817610 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67719.817927 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 67719.817927 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70095.881783 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70095.881783 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 70095.881783 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 70095.881783 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2284 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2788 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2788 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2788 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2788 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079563 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.079563 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.183644 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.183644 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.183644 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.183644 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73954.248366 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73954.248366 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65881.545961 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65881.545961 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 68293.896484 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 68293.896484 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 68293.896484 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 68293.896484 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2328 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 41 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.707317 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.428571 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 285 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 285 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 343 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 343 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 343 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 343 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 54 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 341 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 341 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 341 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 341 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 99 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 99 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8588000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8588000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5911000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5911000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14499000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14499000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14499000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14499000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050652 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050652 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 171 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 171 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8341000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8341000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5669500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5669500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14010500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14010500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14010500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14010500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051482 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051482 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.060511 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.060511 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.060511 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.060511 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85029.702970 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85029.702970 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82097.222222 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82097.222222 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83809.248555 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 83809.248555 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83809.248555 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 83809.248555 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061334 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.061334 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061334 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.061334 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84252.525253 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84252.525253 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78743.055556 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78743.055556 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81932.748538 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 81932.748538 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81932.748538 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 81932.748538 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 158.228991 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1714 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.458599 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 157.774053 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1627 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 311 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.231511 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 158.228991 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077260 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077260 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 157.774053 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077038 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077038 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4702 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4702 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1714 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1714 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1714 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1714 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1714 # number of overall hits -system.cpu.icache.overall_hits::total 1714 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 480 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 480 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 480 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 480 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 480 # number of overall misses -system.cpu.icache.overall_misses::total 480 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 33574500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 33574500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 33574500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 33574500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 33574500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 33574500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2194 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2194 # 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average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75575.079872 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75575.079872 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83450.495050 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83450.495050 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75575.079872 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82245.664740 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77949.588477 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75575.079872 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82245.664740 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77949.588477 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997925 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77201.388889 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77201.388889 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75419.354839 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75419.354839 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82676.767677 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82676.767677 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75419.354839 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80371.345029 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77179.833680 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75419.354839 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80371.345029 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77179.833680 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -880,104 +880,104 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 313 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 313 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 101 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 101 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 486 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 486 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20525000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20525000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7418500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7418500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20525000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12498500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 33023500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20525000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12498500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 33023500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 310 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 310 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 99 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 99 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 310 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 171 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 481 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 310 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 171 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 481 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4838500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4838500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20280000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20280000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7195000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7195000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20280000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12033500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 32313500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20280000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12033500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 32313500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996815 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996785 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997925 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70555.555556 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70555.555556 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65575.079872 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65575.079872 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73450.495050 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73450.495050 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65575.079872 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72245.664740 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67949.588477 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65575.079872 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72245.664740 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67949.588477 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997925 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67201.388889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67201.388889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65419.354839 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65419.354839 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72676.767677 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72676.767677 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65419.354839 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70371.345029 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67179.833680 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65419.354839 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70371.345029 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67179.833680 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 314 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 101 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 974 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 311 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 99 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 622 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 342 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 964 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 487 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 482 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 487 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 482 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 487 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 243500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 482 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 471000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 466500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 256500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 414 # Transaction distribution +system.membus.trans_dist::ReadResp 409 # Transaction distribution system.membus.trans_dist::ReadExReq 72 # Transaction distribution system.membus.trans_dist::ReadExResp 72 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 414 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 972 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 972 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 31104 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 409 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 962 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 962 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30784 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 486 # Request fanout histogram +system.membus.snoop_fanout::samples 481 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 486 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 481 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 486 # Request fanout histogram -system.membus.reqLayer0.occupancy 594500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 481 # Request fanout histogram +system.membus.reqLayer0.occupancy 586000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 2585500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 2558250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini index e07ba072a..5b279bd35 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -228,7 +228,6 @@ hot_lines=false memory_size_bits=48 num_of_sequencers=1 phys_mem=Null -random_seed=1234 randomization=false [system.ruby.clk_domain] diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini index 011f7e597..bf628f608 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini @@ -228,7 +228,6 @@ hot_lines=false memory_size_bits=48 num_of_sequencers=1 phys_mem=Null -random_seed=1234 randomization=false [system.ruby.clk_domain] diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini index 3ff859531..7d246ed9e 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini @@ -228,7 +228,6 @@ hot_lines=false memory_size_bits=48 num_of_sequencers=1 phys_mem=Null -random_seed=1234 randomization=false [system.ruby.clk_domain] diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index 7c57b2554..2f7c0906a 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20091000 # Number of ticks simulated -final_tick 20091000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20075000 # Number of ticks simulated +final_tick 20075000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125803 # Simulator instruction rate (inst/s) -host_op_rate 125723 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 976523768 # Simulator tick rate (ticks/s) -host_mem_usage 293292 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 42420 # Simulator instruction rate (inst/s) +host_op_rate 42407 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 329231154 # Simulator tick rate (ticks/s) +host_mem_usage 287436 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 14272 # Nu system.physmem.num_reads::cpu.inst 223 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 308 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 710367826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 270768006 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 981135832 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 710367826 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 710367826 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 710367826 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 270768006 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 981135832 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 710933998 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 270983811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 981917808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 710933998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 710933998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 710933998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 270983811 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 981917808 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 308 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 308 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20003000 # Total gap between requests +system.physmem.totGap 19987000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -200,15 +200,15 @@ system.physmem.bytesPerActivate::768-895 3 7.32% 85.37% # By system.physmem.bytesPerActivate::896-1023 3 7.32% 92.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 3 7.32% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation -system.physmem.totQLat 1567250 # Total ticks spent queuing -system.physmem.totMemAccLat 7342250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1568250 # Total ticks spent queuing +system.physmem.totMemAccLat 7343250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5088.47 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5091.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23838.47 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 981.14 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23841.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 981.92 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 981.14 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 981.92 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 7.67 # Data bus utilization in percentage @@ -220,7 +220,7 @@ system.physmem.readRowHits 258 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.77 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 64944.81 # Average gap between requests +system.physmem.avgGap 64892.86 # Average gap between requests system.physmem.pageHitRate 83.77 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 83160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 45375 # Energy for precharge commands per rank (pJ) @@ -231,7 +231,7 @@ system.physmem_0.actBackEnergy 10605420 # En system.physmem_0.preBackEnergy 196500 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 12727575 # Total energy per rank (pJ) system.physmem_0.averagePower 803.889152 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 536250 # Time in different power states +system.physmem_0.memoryStateTime::IDLE 534250 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 15041250 # Time in different power states @@ -241,22 +241,22 @@ system.physmem_1.preEnergy 103125 # En system.physmem_1.readEnergy 1201200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10489995 # Energy for active background per rank (pJ) +system.physmem_1.actBackEnergy 10488285 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 299250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13299690 # Total energy per rank (pJ) -system.physmem_1.averagePower 839.892011 # Core power per rank (mW) +system.physmem_1.totalEnergy 13297980 # Total energy per rank (pJ) +system.physmem_1.averagePower 839.916627 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 457000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14871250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14869250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 793 # Number of BP lookups -system.cpu.branchPred.condPredicted 397 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 168 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 563 # Number of BTB lookups -system.cpu.branchPred.BTBHits 58 # Number of BTB hits +system.cpu.branchPred.lookups 787 # Number of BP lookups +system.cpu.branchPred.condPredicted 394 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 164 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 560 # Number of BTB lookups +system.cpu.branchPred.BTBHits 60 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 10.301954 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 10.714286 # BTB Hit Percentage system.cpu.branchPred.usedRAS 138 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -264,22 +264,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 509 # DTB read hits +system.cpu.dtb.read_hits 506 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 516 # DTB read accesses +system.cpu.dtb.read_accesses 513 # DTB read accesses system.cpu.dtb.write_hits 307 # DTB write hits system.cpu.dtb.write_misses 6 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 313 # DTB write accesses -system.cpu.dtb.data_hits 816 # DTB hits +system.cpu.dtb.data_hits 813 # DTB hits system.cpu.dtb.data_misses 13 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 829 # DTB accesses -system.cpu.itb.fetch_hits 971 # ITB hits +system.cpu.dtb.data_accesses 826 # DTB accesses +system.cpu.itb.fetch_hits 965 # ITB hits system.cpu.itb.fetch_misses 13 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 984 # ITB accesses +system.cpu.itb.fetch_accesses 978 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,40 +293,40 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 40182 # number of cpu cycles simulated +system.cpu.numCycles 40150 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2585 # Number of instructions committed system.cpu.committedOps 2585 # Number of ops (including micro ops) committed -system.cpu.discardedOps 594 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 581 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 15.544294 # CPI: cycles per instruction -system.cpu.ipc 0.064332 # IPC: instructions per cycle -system.cpu.tickCycles 5392 # Number of cycles that the object actually ticked -system.cpu.idleCycles 34790 # Total number of cycles that the object has spent stopped +system.cpu.cpi 15.531915 # CPI: cycles per instruction +system.cpu.ipc 0.064384 # IPC: instructions per cycle +system.cpu.tickCycles 5369 # Number of cycles that the object actually ticked +system.cpu.idleCycles 34781 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 48.329975 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 48.313800 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 689 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.141176 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.105882 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 48.329975 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011799 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011799 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 48.313800 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011795 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011795 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1677 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1677 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 441 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 441 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 1671 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1671 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 438 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 438 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 251 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 251 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 692 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 692 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 692 # number of overall hits -system.cpu.dcache.overall_hits::total 692 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 689 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 689 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 689 # number of overall hits +system.cpu.dcache.overall_hits::total 689 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses @@ -343,22 +343,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 7981500 system.cpu.dcache.demand_miss_latency::total 7981500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 7981500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 7981500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 502 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 502 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 499 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 499 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 796 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 796 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 796 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 796 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.121514 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.121514 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 793 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 793 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 793 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 793 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.122244 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.122244 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.146259 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.146259 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.130653 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.130653 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.130653 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.130653 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.131148 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.131148 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.131148 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.131148 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77426.229508 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 77426.229508 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75779.069767 # average WriteReq miss latency @@ -399,14 +399,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6459500 system.cpu.dcache.demand_mshr_miss_latency::total 6459500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6459500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 6459500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.115538 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.115538 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.116232 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.116232 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.106784 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.106784 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.106784 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.106784 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.107188 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.107188 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.107188 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.107188 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76586.206897 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76586.206897 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74722.222222 # average WriteReq mshr miss latency @@ -417,56 +417,56 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75994.117647 system.cpu.dcache.overall_avg_mshr_miss_latency::total 75994.117647 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 117.935175 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 748 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 117.873256 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 742 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 223 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.354260 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.327354 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 117.935175 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057586 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057586 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 117.873256 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057555 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057555 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 223 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2165 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2165 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 748 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 748 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 748 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 748 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 748 # number of overall hits -system.cpu.icache.overall_hits::total 748 # number of overall hits +system.cpu.icache.tags.tag_accesses 2153 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2153 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 742 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 742 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 742 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 742 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 742 # number of overall hits +system.cpu.icache.overall_hits::total 742 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 223 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 223 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 223 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 223 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 223 # number of overall misses system.cpu.icache.overall_misses::total 223 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16978500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16978500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16978500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16978500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16978500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16978500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 971 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 971 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 971 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 971 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 971 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 971 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229660 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.229660 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.229660 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.229660 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.229660 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.229660 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76136.771300 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76136.771300 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76136.771300 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76136.771300 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76136.771300 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76136.771300 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16979500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16979500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16979500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16979500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16979500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16979500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 965 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 965 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 965 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 965 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 965 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 965 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.231088 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.231088 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.231088 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.231088 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.231088 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.231088 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76141.255605 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76141.255605 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76141.255605 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76141.255605 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76141.255605 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76141.255605 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,36 +481,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 223 system.cpu.icache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 223 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16755500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16755500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16755500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16755500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16755500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16755500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.229660 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.229660 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.229660 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.229660 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.229660 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.229660 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75136.771300 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75136.771300 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75136.771300 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75136.771300 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75136.771300 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75136.771300 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16756500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16756500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16756500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16756500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16756500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16756500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231088 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231088 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231088 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.231088 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231088 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.231088 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75141.255605 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75141.255605 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75141.255605 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75141.255605 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75141.255605 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75141.255605 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 145.853573 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 145.780629 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 281 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 118.051720 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 27.801853 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003603 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 117.989893 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 27.790736 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003601 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000848 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004451 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004449 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 281 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id @@ -531,16 +531,16 @@ system.cpu.l2cache.overall_misses::cpu.data 85 # system.cpu.l2cache.overall_misses::total 308 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1977000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1977000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16421000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 16421000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16422000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 16422000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4354000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 4354000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16421000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16422000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 6331000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22752000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16421000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 22753000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16422000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 6331000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22752000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22753000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 223 # number of ReadCleanReq accesses(hits+misses) @@ -567,16 +567,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1 system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73222.222222 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73222.222222 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73636.771300 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73636.771300 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73641.255605 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73641.255605 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75068.965517 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75068.965517 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73636.771300 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73641.255605 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74482.352941 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73870.129870 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73636.771300 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73873.376623 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73641.255605 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74482.352941 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73870.129870 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73873.376623 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -599,16 +599,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 85 system.cpu.l2cache.overall_mshr_misses::total 308 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1707000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1707000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14191000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14191000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14192000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14192000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3774000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3774000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14191000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14192000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5481000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19672000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14191000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19673000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14192000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5481000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19672000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19673000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses @@ -623,16 +623,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63222.222222 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63222.222222 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63636.771300 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63636.771300 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63641.255605 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63641.255605 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65068.965517 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65068.965517 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63636.771300 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63641.255605 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64482.352941 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63870.129870 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63636.771300 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63873.376623 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63641.255605 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64482.352941 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63870.129870 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63873.376623 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index ee80959b5..6ee889334 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 12591500 # Number of ticks simulated -final_tick 12591500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 12363500 # Number of ticks simulated +final_tick 12363500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74456 # Simulator instruction rate (inst/s) -host_op_rate 74426 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 392441951 # Simulator tick rate (ticks/s) -host_mem_usage 293552 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 20992 # Simulator instruction rate (inst/s) +host_op_rate 20989 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 108692792 # Simulator tick rate (ticks/s) +host_mem_usage 288464 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 11968 # Nu system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 950482468 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 432037486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1382519954 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 950482468 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 950482468 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 950482468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 432037486 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1382519954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 968010677 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 440004853 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1408015530 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 968010677 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 968010677 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 968010677 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 440004853 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1408015530 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 272 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 272 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 12495000 # Total gap between requests +system.physmem.totGap 12267000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 82 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -200,27 +200,27 @@ system.physmem.bytesPerActivate::768-895 2 5.56% 83.33% # By system.physmem.bytesPerActivate::896-1023 1 2.78% 86.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 13.89% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 36 # Bytes accessed per row activation -system.physmem.totQLat 1676750 # Total ticks spent queuing -system.physmem.totMemAccLat 6776750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1685750 # Total ticks spent queuing +system.physmem.totMemAccLat 6785750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6164.52 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6197.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24914.52 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1382.52 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24947.61 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1408.02 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1382.52 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1408.02 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.80 # Data bus utilization in percentage -system.physmem.busUtilRead 10.80 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.00 # Data bus utilization in percentage +system.physmem.busUtilRead 11.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 226 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45937.50 # Average gap between requests +system.physmem.avgGap 45099.26 # Average gap between requests system.physmem.pageHitRate 83.09 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 68040 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 37125 # Energy for precharge commands per rank (pJ) @@ -250,36 +250,36 @@ system.physmem_1.memoryStateTime::REF 260000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 7371500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1086 # Number of BP lookups -system.cpu.branchPred.condPredicted 546 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 229 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 723 # Number of BTB lookups -system.cpu.branchPred.BTBHits 206 # Number of BTB hits +system.cpu.branchPred.lookups 890 # Number of BP lookups +system.cpu.branchPred.condPredicted 443 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 195 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 616 # Number of BTB lookups +system.cpu.branchPred.BTBHits 164 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 28.492393 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 197 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 26.623377 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 186 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 9 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 688 # DTB read hits -system.cpu.dtb.read_misses 18 # DTB read misses +system.cpu.dtb.read_hits 719 # DTB read hits +system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 706 # DTB read accesses -system.cpu.dtb.write_hits 353 # DTB write hits -system.cpu.dtb.write_misses 17 # DTB write misses +system.cpu.dtb.read_accesses 729 # DTB read accesses +system.cpu.dtb.write_hits 347 # DTB write hits +system.cpu.dtb.write_misses 16 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 370 # DTB write accesses -system.cpu.dtb.data_hits 1041 # DTB hits -system.cpu.dtb.data_misses 35 # DTB misses +system.cpu.dtb.write_accesses 363 # DTB write accesses +system.cpu.dtb.data_hits 1066 # DTB hits +system.cpu.dtb.data_misses 26 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1076 # DTB accesses -system.cpu.itb.fetch_hits 931 # ITB hits -system.cpu.itb.fetch_misses 26 # ITB misses +system.cpu.dtb.data_accesses 1092 # DTB accesses +system.cpu.itb.fetch_hits 802 # ITB hits +system.cpu.itb.fetch_misses 35 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 957 # ITB accesses +system.cpu.itb.fetch_accesses 837 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,236 +293,235 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 25184 # number of cpu cycles simulated +system.cpu.numCycles 24728 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4404 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6508 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1086 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 403 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1405 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 504 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 4265 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 5512 # Number of instructions fetch has processed +system.cpu.fetch.Branches 890 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 350 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1015 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 436 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1109 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1206 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 931 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 153 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7199 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.904014 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.325149 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 802 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 146 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 6733 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.818654 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.224131 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6086 84.54% 84.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 49 0.68% 85.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 124 1.72% 86.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 82 1.14% 88.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 134 1.86% 89.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 58 0.81% 90.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 66 0.92% 91.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 57 0.79% 92.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 543 7.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5799 86.13% 86.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30 0.45% 86.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 91 1.35% 87.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 76 1.13% 89.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 118 1.75% 90.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 72 1.07% 91.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40 0.59% 92.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 56 0.83% 93.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 451 6.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7199 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.043123 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.258418 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5197 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 794 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 972 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 178 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 158 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 5639 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 276 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 178 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5280 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 486 # Number of cycles rename is blocking +system.cpu.fetch.rateDist::total 6733 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.035992 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.222905 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5190 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 505 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 865 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 28 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 145 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 132 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 4839 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 268 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 145 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5257 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 212 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 288 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 942 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 25 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5401 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 13 # Number of times rename has blocked due to IQ full -system.cpu.rename.RenamedOperands 3881 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6093 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6086 # Number of integer rename lookups +system.cpu.rename.RunCycles 824 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 7 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 4680 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full +system.cpu.rename.RenamedOperands 3347 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5277 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5270 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2113 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 1579 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 109 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 882 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 453 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4674 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 52 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 795 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 418 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 4078 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 3880 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2292 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1214 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 3608 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 32 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1696 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 859 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7199 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.538964 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.280196 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 6733 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.535868 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.279819 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5699 79.16% 79.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 500 6.95% 86.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 351 4.88% 90.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 251 3.49% 94.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 194 2.69% 97.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 116 1.61% 98.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 57 0.79% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 21 0.29% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5352 79.49% 79.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 449 6.67% 86.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 318 4.72% 90.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 240 3.56% 94.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 185 2.75% 97.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 110 1.63% 98.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 49 0.73% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 21 0.31% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 9 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7199 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 6733 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 11.76% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 22 43.14% 54.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 45.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 8.70% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 39 56.52% 65.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 24 34.78% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2765 71.26% 71.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.29% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 738 19.02% 90.31% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 376 9.69% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2482 68.79% 68.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.03% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.82% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 757 20.98% 89.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 368 10.20% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3880 # Type of FU issued -system.cpu.iq.rate 0.154066 # Inst issue rate -system.cpu.iq.fu_busy_cnt 51 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013144 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15012 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 6969 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3584 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 3608 # Type of FU issued +system.cpu.iq.rate 0.145907 # Inst issue rate +system.cpu.iq.fu_busy_cnt 69 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019124 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 14037 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 5777 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3273 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 3924 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 3670 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 28 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 467 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 380 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 159 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 124 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 24 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 91 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 178 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 422 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5018 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 28 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 882 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 453 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 145 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 186 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 4365 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 29 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 795 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 418 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 21 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 168 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 189 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3751 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 707 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 129 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 20 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 120 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 140 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3509 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 730 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 99 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 338 # number of nop insts executed -system.cpu.iew.exec_refs 1077 # number of memory reference insts executed -system.cpu.iew.exec_branches 639 # Number of branches executed -system.cpu.iew.exec_stores 370 # Number of stores executed -system.cpu.iew.exec_rate 0.148944 # Inst execution rate -system.cpu.iew.wb_sent 3648 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3590 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1708 # num instructions producing a value -system.cpu.iew.wb_consumers 2182 # num instructions consuming a value +system.cpu.iew.exec_nop 281 # number of nop insts executed +system.cpu.iew.exec_refs 1093 # number of memory reference insts executed +system.cpu.iew.exec_branches 570 # Number of branches executed +system.cpu.iew.exec_stores 363 # Number of stores executed +system.cpu.iew.exec_rate 0.141904 # Inst execution rate +system.cpu.iew.wb_sent 3329 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3279 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1560 # num instructions producing a value +system.cpu.iew.wb_consumers 1998 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.142551 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.782768 # average fanout of values written-back +system.cpu.iew.wb_rate 0.132603 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.780781 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2428 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1787 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 155 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6748 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.381743 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.245988 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 122 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6402 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.402374 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.273029 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5894 87.34% 87.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193 2.86% 90.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 303 4.49% 94.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 109 1.62% 96.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 72 1.07% 97.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 56 0.83% 98.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 33 0.49% 98.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 20 0.30% 98.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 68 1.01% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5545 86.61% 86.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 194 3.03% 89.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 304 4.75% 94.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 116 1.81% 96.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 62 0.97% 97.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 60 0.94% 98.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 35 0.55% 98.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 20 0.31% 98.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 66 1.03% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6748 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6402 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -568,101 +567,101 @@ system.cpu.commit.op_class_0::MemWrite 294 11.41% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 2576 # Class of committed instruction -system.cpu.commit.bw_lim_events 68 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 11437 # The number of ROB reads -system.cpu.rob.rob_writes 10476 # The number of ROB writes -system.cpu.timesIdled 151 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17985 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 66 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 10452 # The number of ROB reads +system.cpu.rob.rob_writes 9060 # The number of ROB writes +system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17995 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 10.550482 # CPI: Cycles Per Instruction -system.cpu.cpi_total 10.550482 # CPI: Total CPI of All Threads -system.cpu.ipc 0.094782 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.094782 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4532 # number of integer regfile reads -system.cpu.int_regfile_writes 2777 # number of integer regfile writes +system.cpu.cpi 10.359447 # CPI: Cycles Per Instruction +system.cpu.cpi_total 10.359447 # CPI: Total CPI of All Threads +system.cpu.ipc 0.096530 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.096530 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4249 # number of integer regfile reads +system.cpu.int_regfile_writes 2511 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 45.864197 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 731 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 45.334739 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 716 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.600000 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.423529 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 45.864197 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011197 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011197 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 45.334739 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011068 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011068 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1937 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1937 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 518 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 518 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 1873 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1873 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 503 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 503 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 731 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 731 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 731 # number of overall hits -system.cpu.dcache.overall_hits::total 731 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 114 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 114 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 716 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 716 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 716 # number of overall hits +system.cpu.dcache.overall_hits::total 716 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 195 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 195 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 195 # number of overall misses -system.cpu.dcache.overall_misses::total 195 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7589500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7589500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5666500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5666500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13256000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13256000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13256000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13256000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 632 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 632 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 178 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 178 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 178 # number of overall misses +system.cpu.dcache.overall_misses::total 178 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6583000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6583000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5672000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5672000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12255000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12255000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12255000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12255000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 600 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 600 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 926 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 926 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 926 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 926 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180380 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.180380 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 894 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 894 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 894 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 894 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.161667 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.161667 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.210583 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.210583 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.210583 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.210583 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66574.561404 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66574.561404 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69956.790123 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69956.790123 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67979.487179 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67979.487179 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67979.487179 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67979.487179 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 139 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.199105 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.199105 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.199105 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.199105 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67865.979381 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67865.979381 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70024.691358 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70024.691358 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 68848.314607 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 68848.314607 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 68848.314607 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 68848.314607 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 292 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.444444 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 53 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 36 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 36 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 110 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 110 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 110 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 110 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 93 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 93 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 93 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -671,82 +670,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4809500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4809500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4810000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4810000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1851000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1851000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6660500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6660500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6660500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6660500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.096519 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.096519 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6661000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6661000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6661000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6661000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.101667 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.101667 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091793 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091793 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091793 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091793 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78844.262295 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78844.262295 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.095078 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.095078 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.095078 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.095078 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78852.459016 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78852.459016 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77125 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77125 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78358.823529 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78358.823529 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78358.823529 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78358.823529 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78364.705882 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78364.705882 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78364.705882 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78364.705882 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 91.507771 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 679 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 90.143737 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 552 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.631016 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 2.951872 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 91.507771 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.044682 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.044682 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 90.143737 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.044015 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.044015 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 187 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.091309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2049 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2049 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 679 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 679 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 679 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 679 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 679 # number of overall hits -system.cpu.icache.overall_hits::total 679 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 252 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 252 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 252 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 252 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 252 # number of overall misses -system.cpu.icache.overall_misses::total 252 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18724999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18724999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18724999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18724999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18724999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18724999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 931 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 931 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 931 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 931 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 931 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 931 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.270677 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.270677 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.270677 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.270677 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.270677 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.270677 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74305.551587 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74305.551587 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74305.551587 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74305.551587 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74305.551587 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74305.551587 # average overall miss latency +system.cpu.icache.tags.tag_accesses 1791 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1791 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 552 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 552 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 552 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 552 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 552 # number of overall hits +system.cpu.icache.overall_hits::total 552 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses +system.cpu.icache.overall_misses::total 250 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18739499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18739499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18739499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18739499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18739499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18739499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 802 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 802 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 802 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 802 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.311721 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.311721 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.311721 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.311721 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.311721 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.311721 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74957.996000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74957.996000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74957.996000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74957.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74957.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74957.996000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -755,51 +754,51 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 62.500000 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 65 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 65 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 65 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 65 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14173499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14173499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14173499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14173499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14173499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14173499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.200859 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.200859 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.200859 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.200859 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.200859 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.200859 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75794.112299 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75794.112299 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75794.112299 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75794.112299 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75794.112299 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75794.112299 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14179499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14179499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14179499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14179499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14179499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14179499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.233167 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.233167 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.233167 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.233167 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.233167 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.233167 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75826.197861 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75826.197861 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75826.197861 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75826.197861 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75826.197861 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75826.197861 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 120.686426 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 118.927175 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 248 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 91.663709 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29.022716 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002797 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000886 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003683 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.302552 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.624623 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002756 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000874 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003629 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 248 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 48 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 205 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007568 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2448 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2448 # Number of data accesses @@ -817,16 +816,16 @@ system.cpu.l2cache.overall_misses::cpu.data 85 # system.cpu.l2cache.overall_misses::total 272 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1813500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1813500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13892000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 13892000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4718000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4718000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13892000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6531500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20423500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13892000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6531500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20423500 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13898000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 13898000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4718500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4718500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 13898000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6532000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20430000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 13898000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6532000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20430000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187 # number of ReadCleanReq accesses(hits+misses) @@ -853,16 +852,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1 system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75562.500000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75562.500000 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74288.770053 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74288.770053 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77344.262295 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77344.262295 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74288.770053 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76841.176471 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75086.397059 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74288.770053 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76841.176471 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75086.397059 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74320.855615 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74320.855615 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77352.459016 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77352.459016 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74320.855615 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76847.058824 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75110.294118 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74320.855615 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76847.058824 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75110.294118 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -885,16 +884,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 85 system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1573500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1573500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12022000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12022000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4108000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4108000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12022000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5681500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17703500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12022000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5681500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17703500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12028000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12028000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4108500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4108500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12028000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5682000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17710000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12028000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5682000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17710000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses @@ -909,16 +908,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65562.500000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65562.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64288.770053 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64288.770053 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67344.262295 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67344.262295 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64288.770053 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66841.176471 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65086.397059 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64288.770053 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66841.176471 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65086.397059 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64320.855615 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64320.855615 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67352.459016 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67352.459016 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64320.855615 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66847.058824 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65110.294118 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64320.855615 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66847.058824 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65110.294118 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution @@ -946,7 +945,7 @@ system.cpu.toL2Bus.snoop_fanout::total 272 # Re system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 280500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.membus.trans_dist::ReadResp 248 # Transaction distribution @@ -968,9 +967,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 272 # Request fanout histogram -system.membus.reqLayer0.occupancy 337000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 335500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 1441250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 1441000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini index 32421c7b3..0c42ac84b 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini @@ -228,7 +228,6 @@ hot_lines=false memory_size_bits=48 num_of_sequencers=1 phys_mem=Null -random_seed=1234 randomization=false [system.ruby.clk_domain] diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini index 0d1926cd4..f0b756165 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -228,7 +228,6 @@ hot_lines=false memory_size_bits=48 num_of_sequencers=1 phys_mem=Null -random_seed=1234 randomization=false [system.ruby.clk_domain] diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini index ebc9b7aa1..a00344038 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -228,7 +228,6 @@ hot_lines=false memory_size_bits=48 num_of_sequencers=1 phys_mem=Null -random_seed=1234 randomization=false [system.ruby.clk_domain] diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini index d78920aa6..6e0294d29 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini @@ -228,7 +228,6 @@ hot_lines=false memory_size_bits=48 num_of_sequencers=1 phys_mem=Null -random_seed=1234 randomization=false [system.ruby.clk_domain] diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini index 408894bb9..46fd0f447 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini @@ -228,7 +228,6 @@ hot_lines=false memory_size_bits=48 num_of_sequencers=1 phys_mem=Null -random_seed=1234 randomization=false [system.ruby.clk_domain] diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index e5ff065c1..3e86bd3ac 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 29934500 # Number of ticks simulated -final_tick 29934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 29941500 # Number of ticks simulated +final_tick 29941500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115469 # Simulator instruction rate (inst/s) -host_op_rate 135130 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 750106498 # Simulator tick rate (ticks/s) -host_mem_usage 310152 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 58660 # Simulator instruction rate (inst/s) +host_op_rate 68656 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 381226078 # Simulator tick rate (ticks/s) +host_mem_usage 304332 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4605 # Number of instructions simulated sim_ops 5391 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory system.physmem.num_reads::total 421 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 652090397 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 248008151 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 900098548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 652090397 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 652090397 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 652090397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 248008151 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 900098548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 651937946 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 247950169 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 899888115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 651937946 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 651937946 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 651937946 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 247950169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 899888115 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 421 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 29844000 # Total gap between requests +system.physmem.totGap 29851000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -200,15 +200,15 @@ system.physmem.bytesPerActivate::768-895 3 4.84% 83.87% # By system.physmem.bytesPerActivate::896-1023 1 1.61% 85.48% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation -system.physmem.totQLat 2214000 # Total ticks spent queuing -system.physmem.totMemAccLat 10107750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 2218000 # Total ticks spent queuing +system.physmem.totMemAccLat 10111750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5258.91 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5268.41 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24008.91 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 900.10 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24018.41 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 899.89 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 900.10 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 899.89 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 7.03 # Data bus utilization in percentage @@ -220,7 +220,7 @@ system.physmem.readRowHits 350 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 70888.36 # Average gap between requests +system.physmem.avgGap 70904.99 # Average gap between requests system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) @@ -250,14 +250,14 @@ system.physmem_1.memoryStateTime::REF 780000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 22328250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1918 # Number of BP lookups -system.cpu.branchPred.condPredicted 1150 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 336 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1604 # Number of BTB lookups -system.cpu.branchPred.BTBHits 341 # Number of BTB hits +system.cpu.branchPred.lookups 1912 # Number of BP lookups +system.cpu.branchPred.condPredicted 1153 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 338 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1608 # Number of BTB lookups +system.cpu.branchPred.BTBHits 347 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 21.259352 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 218 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 21.579602 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,44 +377,44 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 59869 # number of cpu cycles simulated +system.cpu.numCycles 59883 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4605 # Number of instructions committed system.cpu.committedOps 5391 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1116 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1120 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 13.000869 # CPI: cycles per instruction -system.cpu.ipc 0.076918 # IPC: instructions per cycle -system.cpu.tickCycles 10574 # Number of cycles that the object actually ticked -system.cpu.idleCycles 49295 # Total number of cycles that the object has spent stopped +system.cpu.cpi 13.003909 # CPI: cycles per instruction +system.cpu.ipc 0.076900 # IPC: instructions per cycle +system.cpu.tickCycles 10593 # Number of cycles that the object actually ticked +system.cpu.idleCycles 49290 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.493580 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 86.506122 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.116438 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.493580 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021117 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021117 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.506122 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021120 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021120 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4346 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4346 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1050 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1050 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4340 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4340 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1047 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1047 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits -system.cpu.dcache.overall_hits::total 1896 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1893 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1893 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1893 # number of overall hits +system.cpu.dcache.overall_hits::total 1893 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses @@ -423,42 +423,42 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6956000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6956000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6956500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6956500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 5019500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 5019500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 11975500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 11975500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 11975500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 11975500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1165 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1165 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 11976000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 11976000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 11976000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 11976000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1162 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1162 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2078 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2078 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2078 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2078 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098712 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098712 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2075 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2075 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2075 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2075 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098967 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098967 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.087584 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.087584 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.087584 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.087584 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60486.956522 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60486.956522 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.087711 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.087711 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.087711 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.087711 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60491.304348 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60491.304348 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74917.910448 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 74917.910448 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65799.450549 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65799.450549 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65799.450549 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65799.450549 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65802.197802 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65802.197802 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65802.197802 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65802.197802 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -483,82 +483,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6353000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6353000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6353500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6353500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3198000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3198000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9551000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9551000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9551000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9551000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088412 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088412 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9551500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9551500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9551500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9551500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088640 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088640 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070260 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.070260 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070260 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.070260 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61679.611650 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61679.611650 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070361 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.070361 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070361 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.070361 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61684.466019 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61684.466019 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74372.093023 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74372.093023 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65417.808219 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65417.808219 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65417.808219 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65417.808219 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65421.232877 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65421.232877 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65421.232877 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 65421.232877 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 161.765243 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1909 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 161.800750 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1920 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.928571 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.962733 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 161.765243 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078987 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078987 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 161.800750 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.079004 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.079004 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4784 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4784 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1909 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1909 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1909 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1909 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1909 # number of overall hits -system.cpu.icache.overall_hits::total 1909 # number of overall hits +system.cpu.icache.tags.tag_accesses 4806 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4806 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1920 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1920 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1920 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1920 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1920 # number of overall hits +system.cpu.icache.overall_hits::total 1920 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses system.cpu.icache.overall_misses::total 322 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23594000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23594000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23594000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23594000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23594000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23594000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2231 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2231 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2231 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2231 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2231 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2231 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.144330 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.144330 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.144330 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.144330 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.144330 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.144330 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73273.291925 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 73273.291925 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 73273.291925 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 73273.291925 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 73273.291925 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73273.291925 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23597500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23597500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23597500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23597500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23597500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23597500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2242 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2242 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2242 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2242 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2242 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2242 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143622 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.143622 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.143622 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.143622 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.143622 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.143622 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73284.161491 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73284.161491 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 73284.161491 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73284.161491 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 73284.161491 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73284.161491 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -573,36 +573,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 322 system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23272000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23272000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23272000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23272000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23272000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23272000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.144330 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.144330 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.144330 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.144330 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.144330 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.144330 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72273.291925 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72273.291925 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72273.291925 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72273.291925 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72273.291925 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72273.291925 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23275500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23275500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23275500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23275500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23275500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23275500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143622 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.143622 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.143622 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72284.161491 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72284.161491 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72284.161491 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72284.161491 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72284.161491 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72284.161491 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 195.411120 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 195.452372 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 41 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.108466 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.281002 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 41.130118 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004708 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.314702 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 41.137670 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004709 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005963 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005965 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id @@ -633,16 +633,16 @@ system.cpu.l2cache.overall_misses::cpu.data 124 # system.cpu.l2cache.overall_misses::total 429 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3133500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3133500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22610500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 22610500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5960500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 5960500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22610500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9094000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31704500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22610500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9094000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31704500 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22614000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 22614000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5961000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 5961000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22614000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9094500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31708500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22614000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9094500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31708500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses) @@ -669,16 +669,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72872.093023 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72872.093023 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74132.786885 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74132.786885 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73586.419753 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73586.419753 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74132.786885 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73338.709677 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73903.263403 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74132.786885 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73338.709677 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73903.263403 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74144.262295 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74144.262295 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73592.592593 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73592.592593 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74144.262295 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73912.587413 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74144.262295 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73342.741935 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73912.587413 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -707,16 +707,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 116 system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2703500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2703500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19560500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19560500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4700500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4700500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19560500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7404000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26964500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19560500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7404000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26964500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19564000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19564000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4701000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4701000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19564000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7404500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26968500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19564000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7404500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26968500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses @@ -731,16 +731,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62872.093023 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62872.093023 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64132.786885 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64132.786885 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64390.410959 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64390.410959 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64132.786885 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63827.586207 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64048.693587 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64132.786885 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63827.586207 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64048.693587 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64144.262295 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64144.262295 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64397.260274 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64397.260274 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64144.262295 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64058.194774 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64144.262295 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63831.896552 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64058.194774 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 2 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index e4986f157..800acea54 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -1,14 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simout +Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 22 2015 10:58:25 -gem5 started Apr 22 2015 14:33:28 -gem5 executing on phenom -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 14 2015 23:30:05 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second - 0: system.cpu.checker.isa: ISA system set to: 0 0x38f90a0 - 0: system.cpu.isa: ISA system set to: 0 0x38f90a0 info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 17307500 because target called exit() +Exiting @ tick 17163000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 80e232875..be50d79db 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17226500 # Number of ticks simulated -final_tick 17226500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 17163000 # Number of ticks simulated +final_tick 17163000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55427 # Simulator instruction rate (inst/s) -host_op_rate 64904 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 207866253 # Simulator tick rate (ticks/s) -host_mem_usage 311436 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 25428 # Simulator instruction rate (inst/s) +host_op_rate 29777 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 95019968 # Simulator tick rate (ticks/s) +host_mem_usage 305352 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17600 # Nu system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory system.physmem.num_reads::total 396 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1021681711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 449539953 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1471221664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1021681711 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1021681711 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1021681711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 449539953 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1471221664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1025461749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 451203170 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1476664919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1025461749 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1025461749 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1025461749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 451203170 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1476664919 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 396 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 17159000 # Total gap between requests +system.physmem.totGap 17090000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 206 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,78 +186,78 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 395.354839 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 263.720067 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 338.958245 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 11 17.74% 17.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19 30.65% 48.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6 9.68% 58.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 12.90% 70.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.84% 75.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.23% 79.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 3.23% 82.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 3.23% 85.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation -system.physmem.totQLat 3039250 # Total ticks spent queuing -system.physmem.totMemAccLat 10464250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 389.079365 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 252.523009 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 343.171701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13 20.63% 20.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18 28.57% 49.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6 9.52% 58.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8 12.70% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 3.17% 85.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation +system.physmem.totQLat 3055250 # Total ticks spent queuing +system.physmem.totMemAccLat 10480250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7674.87 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7715.28 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26424.87 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1471.22 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26465.28 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1476.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1471.22 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1476.66 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.49 # Data bus utilization in percentage -system.physmem.busUtilRead 11.49 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.54 # Data bus utilization in percentage +system.physmem.busUtilRead 11.54 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 331 # Number of row buffer hits during reads +system.physmem.readRowHits 330 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.59 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.33 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43330.81 # Average gap between requests -system.physmem.pageHitRate 83.59 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 302400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 165000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 43156.57 # Average gap between requests +system.physmem.pageHitRate 83.33 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2106000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10797795 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 10794375 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14404965 # Total energy per rank (pJ) -system.physmem_0.averagePower 909.404356 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 69250 # Time in different power states +system.physmem_0.totalEnergy 14428830 # Total energy per rank (pJ) +system.physmem_0.averagePower 911.198611 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 65750 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16109250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16176750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 748800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10359180 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 412500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12771300 # Total energy per rank (pJ) -system.physmem_1.averagePower 806.650876 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 820250 # Time in different power states +system.physmem_1.actBackEnergy 10407915 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 369750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12777285 # Total energy per rank (pJ) +system.physmem_1.averagePower 807.028896 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 665250 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14680750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14752750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2576 # Number of BP lookups -system.cpu.branchPred.condPredicted 1602 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 469 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2087 # Number of BTB lookups -system.cpu.branchPred.BTBHits 781 # Number of BTB hits +system.cpu.branchPred.lookups 2533 # Number of BP lookups +system.cpu.branchPred.condPredicted 1576 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 452 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2102 # Number of BTB lookups +system.cpu.branchPred.BTBHits 812 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 37.422137 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 336 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 38.629876 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 321 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -496,237 +496,237 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 34454 # number of cpu cycles simulated +system.cpu.numCycles 34327 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7709 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12205 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2576 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1117 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4748 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 987 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 7647 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11725 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2533 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1133 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4667 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 953 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 2016 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13219 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.088585 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.463952 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1968 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 290 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13059 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.059729 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.422792 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10589 80.10% 80.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 274 2.07% 82.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 212 1.60% 83.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 221 1.67% 85.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 236 1.79% 87.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 324 2.45% 89.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 139 1.05% 90.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 161 1.22% 91.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1063 8.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10498 80.39% 80.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 262 2.01% 82.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 215 1.65% 84.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 219 1.68% 85.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 263 2.01% 87.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 312 2.39% 90.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 142 1.09% 91.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 158 1.21% 92.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 990 7.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13219 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.074766 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.354240 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6369 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4276 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2102 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 134 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 338 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 13059 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.073790 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.341568 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6338 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4216 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2063 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 121 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 321 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 380 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11852 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 468 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 338 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6584 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 692 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2356 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2013 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1236 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11200 # Number of instructions processed by rename +system.cpu.decode.DecodedInsts 11316 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 321 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6551 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 647 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2328 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1964 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1248 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 10673 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 168 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 130 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1064 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 11331 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 51672 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12441 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups +system.cpu.rename.SQFullEvents 1076 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 10857 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 48954 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 11788 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 74 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5837 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 43 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 5363 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 42 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 422 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2287 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1689 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 38 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 34 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10125 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 428 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2126 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1537 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 9711 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8202 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 55 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4793 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12371 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 7972 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4379 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 10941 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13219 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.620471 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.365465 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13059 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.610460 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.342240 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10002 75.66% 75.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1166 8.82% 84.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 755 5.71% 90.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 451 3.41% 93.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 357 2.70% 96.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 278 2.10% 98.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 131 0.99% 99.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 63 0.48% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 16 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9876 75.63% 75.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1174 8.99% 84.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 762 5.84% 90.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 454 3.48% 93.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 326 2.50% 96.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 278 2.13% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 116 0.89% 99.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 62 0.47% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13219 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13059 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 5.26% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 84 49.12% 54.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78 45.61% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 5.92% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 67 44.08% 50.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 76 50.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4937 60.19% 60.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1959 23.88% 84.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1297 15.81% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4885 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.09% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1831 22.97% 84.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1246 15.63% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8202 # Type of FU issued -system.cpu.iq.rate 0.238057 # Inst issue rate -system.cpu.iq.fu_busy_cnt 171 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020849 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29750 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14855 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7430 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 7972 # Type of FU issued +system.cpu.iq.rate 0.232237 # Inst issue rate +system.cpu.iq.fu_busy_cnt 152 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019067 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29107 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14039 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7309 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 93 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 116 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8330 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8081 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 24 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1260 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1099 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 751 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 599 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 34 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 338 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 660 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 321 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 613 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10180 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 127 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2287 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1689 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 9766 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 119 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2126 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1537 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 111 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 234 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 345 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7868 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1843 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 334 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 215 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 327 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7697 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1736 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 275 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 9 # number of nop insts executed -system.cpu.iew.exec_refs 3072 # number of memory reference insts executed -system.cpu.iew.exec_branches 1434 # Number of branches executed -system.cpu.iew.exec_stores 1229 # Number of stores executed -system.cpu.iew.exec_rate 0.228362 # Inst execution rate -system.cpu.iew.wb_sent 7574 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7462 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3524 # num instructions producing a value -system.cpu.iew.wb_consumers 6897 # num instructions consuming a value +system.cpu.iew.exec_refs 2930 # number of memory reference insts executed +system.cpu.iew.exec_branches 1433 # Number of branches executed +system.cpu.iew.exec_stores 1194 # Number of stores executed +system.cpu.iew.exec_rate 0.224226 # Inst execution rate +system.cpu.iew.wb_sent 7432 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7341 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3456 # num instructions producing a value +system.cpu.iew.wb_consumers 6757 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.216579 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.510947 # average fanout of values written-back +system.cpu.iew.wb_rate 0.213855 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.511470 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4801 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4387 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 314 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12382 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.434340 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.281233 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 297 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12286 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.437734 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.284067 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10327 83.40% 83.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 891 7.20% 90.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 421 3.40% 94.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 214 1.73% 95.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 114 0.92% 96.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 212 1.71% 98.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 49 0.40% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.31% 99.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 115 0.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10235 83.31% 83.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 882 7.18% 90.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 420 3.42% 93.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 222 1.81% 95.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 111 0.90% 96.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 213 1.73% 98.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 51 0.42% 98.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.33% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 111 0.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12382 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12286 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -772,121 +772,121 @@ system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction -system.cpu.commit.bw_lim_events 115 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22289 # The number of ROB reads -system.cpu.rob.rob_writes 21210 # The number of ROB writes -system.cpu.timesIdled 194 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21235 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 111 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 21783 # The number of ROB reads +system.cpu.rob.rob_writes 20313 # The number of ROB writes +system.cpu.timesIdled 192 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 21268 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.503049 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.503049 # CPI: Total CPI of All Threads -system.cpu.ipc 0.133279 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.133279 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7752 # number of integer regfile reads -system.cpu.int_regfile_writes 4259 # number of integer regfile writes +system.cpu.cpi 7.475392 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.475392 # CPI: Total CPI of All Threads +system.cpu.ipc 0.133772 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.133772 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 7631 # number of integer regfile reads +system.cpu.int_regfile_writes 4176 # number of integer regfile writes system.cpu.fp_regfile_reads 32 # number of floating regfile reads -system.cpu.cc_regfile_reads 28119 # number of cc regfile reads -system.cpu.cc_regfile_writes 3280 # number of cc regfile writes -system.cpu.misc_regfile_reads 3175 # number of misc regfile reads +system.cpu.cc_regfile_reads 27375 # number of cc regfile reads +system.cpu.cc_regfile_writes 3204 # number of cc regfile writes +system.cpu.misc_regfile_reads 3054 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.080084 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2156 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.767123 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.851603 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2054 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.972789 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.080084 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021260 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021260 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 87.851603 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021448 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021448 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5466 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5466 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1537 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1537 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits +system.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5255 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5255 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1436 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1436 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 596 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 596 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2134 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2134 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2134 # number of overall hits -system.cpu.dcache.overall_hits::total 2134 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 186 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 186 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2032 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2032 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2032 # number of overall hits +system.cpu.dcache.overall_hits::total 2032 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 181 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 181 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 317 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 317 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses -system.cpu.dcache.overall_misses::total 502 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10668000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10668000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22567500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22567500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses +system.cpu.dcache.overall_misses::total 498 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10572000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10572000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22577500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22577500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 142000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33235500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33235500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33235500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33235500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1723 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1723 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 33149500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33149500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33149500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33149500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1617 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1617 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2636 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2636 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2636 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2636 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.107951 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.107951 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2530 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2530 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2530 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2530 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.111936 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.111936 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.347207 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.347207 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.190440 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.190440 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.190440 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.190440 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57354.838710 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 57354.838710 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71416.139241 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 71416.139241 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.196838 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.196838 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.196838 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.196838 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58408.839779 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58408.839779 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71222.397476 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 71222.397476 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66206.175299 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66206.175299 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66206.175299 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66206.175299 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66565.261044 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66565.261044 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66565.261044 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66565.261044 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 63 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.333333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 274 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 76 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 275 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 275 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -895,135 +895,135 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6685000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6685000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3406500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3406500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10091500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10091500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10091500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10091500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.060940 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.060940 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6969000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6969000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3397000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3397000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10366000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10366000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10366000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10366000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.064935 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.064935 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055766 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.055766 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055766 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.055766 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63666.666667 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63666.666667 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81107.142857 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81107.142857 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68649.659864 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68649.659864 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68649.659864 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68649.659864 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058103 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.058103 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058103 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.058103 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66371.428571 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66371.428571 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80880.952381 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80880.952381 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70517.006803 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70517.006803 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70517.006803 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70517.006803 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 149.175552 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1623 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 149.741808 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1582 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 293 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.539249 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.399317 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 149.175552 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.072840 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.072840 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 149.741808 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073116 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073116 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4325 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4325 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1623 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1623 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1623 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1623 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1623 # number of overall hits -system.cpu.icache.overall_hits::total 1623 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 393 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 393 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 393 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 393 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 393 # number of overall misses -system.cpu.icache.overall_misses::total 393 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 27030000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 27030000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 27030000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 27030000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 27030000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 27030000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2016 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2016 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2016 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2016 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2016 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2016 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194940 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.194940 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.194940 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.194940 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.194940 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.194940 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68778.625954 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68778.625954 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68778.625954 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68778.625954 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68778.625954 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68778.625954 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 456 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 4229 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4229 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1582 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1582 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1582 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1582 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1582 # number of overall hits +system.cpu.icache.overall_hits::total 1582 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 386 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 386 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 386 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 386 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 386 # number of overall misses +system.cpu.icache.overall_misses::total 386 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26869500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26869500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26869500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26869500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26869500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26869500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1968 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1968 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1968 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1968 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1968 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1968 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196138 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.196138 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.196138 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.196138 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.196138 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.196138 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69610.103627 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69610.103627 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69610.103627 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69610.103627 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69610.103627 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69610.103627 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 432 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 91.200000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 86.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 100 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 100 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 100 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 100 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 100 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 93 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 93 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 93 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 93 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 93 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 293 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 293 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 293 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 293 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21572000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21572000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21572000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21572000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21572000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21572000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145337 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145337 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145337 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.145337 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145337 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.145337 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73624.573379 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73624.573379 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73624.573379 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73624.573379 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73624.573379 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73624.573379 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21385500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21385500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21385500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21385500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21385500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21385500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148882 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148882 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148882 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148882 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148882 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148882 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72988.054608 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72988.054608 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72988.054608 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72988.054608 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72988.054608 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72988.054608 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 186.076752 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 187.228350 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 354 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.110169 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.018845 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.057907 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004273 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001406 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005679 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.551776 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 46.676574 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004289 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001424 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005714 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010803 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3916 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3916 # Number of data accesses @@ -1049,18 +1049,18 @@ system.cpu.l2cache.demand_misses::total 401 # nu system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 126 # number of overall misses system.cpu.l2cache.overall_misses::total 401 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3342500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3342500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 20942500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 20942500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6371000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6371000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20942500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9713500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30656000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20942500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9713500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30656000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3333000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3333000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 20756000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 20756000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6584500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6584500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20756000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9917500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30673500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20756000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9917500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30673500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 293 # number of ReadCleanReq accesses(hits+misses) @@ -1085,18 +1085,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.911364 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938567 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.857143 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.911364 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79583.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79583.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76154.545455 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76154.545455 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75845.238095 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75845.238095 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76154.545455 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77091.269841 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76448.877805 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76154.545455 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77091.269841 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76448.877805 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79357.142857 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79357.142857 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75476.363636 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75476.363636 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78386.904762 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78386.904762 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75476.363636 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78710.317460 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76492.518703 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75476.363636 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78710.317460 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76492.518703 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1123,18 +1123,18 @@ system.cpu.l2cache.demand_mshr_misses::total 396 system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2922500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2922500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18192500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18192500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5250500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5250500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18192500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8173000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26365500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18192500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8173000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26365500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2913000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2913000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18006000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18006000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5464000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5464000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18006000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8377000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26383000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18006000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8377000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26383000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for ReadCleanReq accesses @@ -1147,30 +1147,30 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.900000 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69583.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69583.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66154.545455 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66154.545455 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66462.025316 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66462.025316 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66154.545455 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67545.454545 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66579.545455 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66154.545455 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67545.454545 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66579.545455 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69357.142857 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69357.142857 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65476.363636 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65476.363636 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69164.556962 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69164.556962 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65476.363636 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69231.404959 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66623.737374 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65476.363636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69231.404959 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66623.737374 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 397 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 293 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 586 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 879 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 880 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram @@ -1187,7 +1187,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy 220500 # La system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 439500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 221495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 222995 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) system.membus.trans_dist::ReadResp 354 # Transaction distribution system.membus.trans_dist::ReadExReq 42 # Transaction distribution @@ -1210,7 +1210,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 396 # Request fanout histogram system.membus.reqLayer0.occupancy 485500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 2095750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2097000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 12.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 5213b7cc0..d3878acf4 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 22403000 # Number of ticks simulated -final_tick 22403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 22451000 # Number of ticks simulated +final_tick 22451000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79030 # Simulator instruction rate (inst/s) -host_op_rate 79012 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 354943993 # Simulator tick rate (ticks/s) -host_mem_usage 292784 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 41665 # Simulator instruction rate (inst/s) +host_op_rate 41658 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 187549895 # Simulator tick rate (ticks/s) +host_mem_usage 287968 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 4986 # Number of instructions simulated sim_ops 4986 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 21120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 20992 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory -system.physmem.bytes_read::total 30144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21120 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 330 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 30016 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 20992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 20992 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 328 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory -system.physmem.num_reads::total 471 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 942730884 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 402803196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1345534080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 942730884 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 942730884 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 942730884 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 402803196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1345534080 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 471 # Number of read requests accepted +system.physmem.num_reads::total 469 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 935014031 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 401942007 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1336956038 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 935014031 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 935014031 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 935014031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 401942007 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1336956038 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 469 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 471 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30144 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 30016 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30144 # Total read bytes from the system interface side +system.physmem.bytesReadSys 30016 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -55,7 +55,7 @@ system.physmem.perBankRdBursts::10 43 # Pe system.physmem.perBankRdBursts::11 20 # Per bank write bursts system.physmem.perBankRdBursts::12 51 # Per bank write bursts system.physmem.perBankRdBursts::13 29 # Per bank write bursts -system.physmem.perBankRdBursts::14 80 # Per bank write bursts +system.physmem.perBankRdBursts::14 78 # Per bank write bursts system.physmem.perBankRdBursts::15 7 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22316000 # Total gap between requests +system.physmem.totGap 22364000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 471 # Read request sizes (log2) +system.physmem.readPktSize::6 469 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,79 +186,79 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 105 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 260.876190 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.828028 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 254.099908 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 30 28.57% 28.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 33 31.43% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 19 18.10% 78.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 10 9.52% 87.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 2.86% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 1.90% 92.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 0.95% 93.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 0.95% 94.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6 5.71% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 105 # Bytes accessed per row activation -system.physmem.totQLat 4348750 # Total ticks spent queuing -system.physmem.totMemAccLat 13180000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2355000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9233.01 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 104 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 262.153846 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.926322 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 251.694944 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 29 27.88% 27.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 32 30.77% 58.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 20 19.23% 77.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 9 8.65% 86.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 3.85% 90.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 1.92% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 0.96% 93.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 0.96% 94.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6 5.77% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 104 # Bytes accessed per row activation +system.physmem.totQLat 4505500 # Total ticks spent queuing +system.physmem.totMemAccLat 13299250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9606.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27983.01 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1345.53 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28356.61 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1336.96 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1345.53 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1336.96 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.51 # Data bus utilization in percentage -system.physmem.busUtilRead 10.51 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.44 # Data bus utilization in percentage +system.physmem.busUtilRead 10.44 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.71 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 356 # Number of row buffer hits during reads +system.physmem.readRowHits 355 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.69 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 47380.04 # Average gap between requests -system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined +system.physmem.avgGap 47684.43 # Average gap between requests +system.physmem.pageHitRate 75.69 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 538200 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 530400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 9525555 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1143750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 12423270 # Total energy per rank (pJ) -system.physmem_0.averagePower 784.668877 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2113750 # Time in different power states +system.physmem_0.actBackEnergy 9542655 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1130250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12419070 # Total energy per rank (pJ) +system.physmem_0.averagePower 784.279760 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1840500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 13462250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 13487750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 521640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 284625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2191800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 514080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 280500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2168400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10738800 # Energy for active background per rank (pJ) +system.physmem_1.actBackEnergy 10730250 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 87000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14840985 # Total energy per rank (pJ) -system.physmem_1.averagePower 936.635216 # Core power per rank (mW) +system.physmem_1.totalEnergy 14797350 # Total energy per rank (pJ) +system.physmem_1.averagePower 934.618664 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 103500 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15234500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15222750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2126 # Number of BP lookups -system.cpu.branchPred.condPredicted 1379 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 429 # Number of conditional branches incorrect +system.cpu.branchPred.lookups 2031 # Number of BP lookups +system.cpu.branchPred.condPredicted 1362 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 402 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 1641 # Number of BTB lookups -system.cpu.branchPred.BTBHits 514 # Number of BTB hits +system.cpu.branchPred.BTBHits 605 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 31.322364 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 281 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 36.867764 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 242 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 66 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -279,236 +279,236 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 44807 # number of cpu cycles simulated +system.cpu.numCycles 44903 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8961 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12993 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2126 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 795 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4908 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 876 # Number of cycles fetch has spent squashing -system.cpu.fetch.PendingTrapStallCycles 194 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2040 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14501 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.896007 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.195594 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 8843 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12328 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2031 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 847 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4817 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 822 # Number of cycles fetch has spent squashing +system.cpu.fetch.PendingTrapStallCycles 190 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1979 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 255 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14261 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.864456 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.133927 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11177 77.08% 77.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1470 10.14% 87.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 121 0.83% 88.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 160 1.10% 89.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 283 1.95% 91.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 95 0.66% 91.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 127 0.88% 92.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 112 0.77% 93.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 956 6.59% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10999 77.13% 77.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1480 10.38% 87.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 118 0.83% 88.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 169 1.19% 89.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 282 1.98% 91.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 102 0.72% 92.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 134 0.94% 93.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 153 1.07% 94.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 824 5.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14501 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.047448 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.289977 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8511 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2687 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2777 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 129 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 397 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 172 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12008 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 170 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 397 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8669 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 506 # Number of cycles rename is blocking +system.cpu.fetch.rateDist::total 14261 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.045231 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.274547 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8380 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2677 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2707 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 371 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 41 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 11351 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 162 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 371 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8518 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 542 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 996 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2735 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1198 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11509 # Number of instructions processed by rename +system.cpu.rename.RunCycles 2675 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1159 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 10918 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 229 # Number of times rename has blocked due to LQ full +system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 179 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 954 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 6966 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13566 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13315 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 6512 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 12905 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12683 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3282 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3684 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3230 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 14 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 296 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2503 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1169 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 314 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2295 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1159 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9007 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8632 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8237 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4031 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1845 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 7937 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3656 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1608 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14501 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.568030 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.308332 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14261 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.556553 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.276985 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11165 76.99% 76.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1330 9.17% 86.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 739 5.10% 91.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 423 2.92% 94.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 353 2.43% 96.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 304 2.10% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 105 0.72% 99.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 58 0.40% 99.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 24 0.17% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10981 77.00% 77.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1321 9.26% 86.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 733 5.14% 91.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 439 3.08% 94.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 350 2.45% 96.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 277 1.94% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 91 0.64% 99.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 50 0.35% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14501 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14261 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7 3.57% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 131 66.84% 70.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 58 29.59% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 3.41% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 112 63.64% 67.05% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 58 32.95% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4840 58.76% 58.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2319 28.15% 87.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1071 13.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4719 59.46% 59.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 59.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 1 0.01% 59.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2143 27.00% 86.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1068 13.46% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8237 # Type of FU issued -system.cpu.iq.rate 0.183833 # Inst issue rate -system.cpu.iq.fu_busy_cnt 196 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023795 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31205 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 13056 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7426 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 7937 # Type of FU issued +system.cpu.iq.rate 0.176759 # Inst issue rate +system.cpu.iq.fu_busy_cnt 176 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.022175 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30327 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12306 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7277 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8431 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8111 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 83 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 89 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1371 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1163 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 258 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 23 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 397 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 472 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10561 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 155 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2503 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1169 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 371 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 425 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 88 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10126 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 130 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2295 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1159 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 9 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 89 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 354 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 452 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7898 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2175 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 339 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 321 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 419 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7671 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2045 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 266 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1543 # number of nop insts executed -system.cpu.iew.exec_refs 3228 # number of memory reference insts executed -system.cpu.iew.exec_branches 1368 # Number of branches executed +system.cpu.iew.exec_nop 1483 # number of nop insts executed +system.cpu.iew.exec_refs 3098 # number of memory reference insts executed +system.cpu.iew.exec_branches 1353 # Number of branches executed system.cpu.iew.exec_stores 1053 # Number of stores executed -system.cpu.iew.exec_rate 0.176267 # Inst execution rate -system.cpu.iew.wb_sent 7529 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7428 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2859 # num instructions producing a value -system.cpu.iew.wb_consumers 4251 # num instructions consuming a value +system.cpu.iew.exec_rate 0.170835 # Inst execution rate +system.cpu.iew.wb_sent 7354 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7279 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2832 # num instructions producing a value +system.cpu.iew.wb_consumers 4198 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.165778 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.672548 # average fanout of values written-back +system.cpu.iew.wb_rate 0.162105 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.674607 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4937 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4505 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 388 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13632 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.412485 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.223639 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 362 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13468 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.417508 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.246465 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11448 83.98% 83.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 886 6.50% 90.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 511 3.75% 94.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 255 1.87% 96.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 161 1.18% 97.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 164 1.20% 98.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 65 0.48% 98.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 40 0.29% 99.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 102 0.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11324 84.08% 84.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 857 6.36% 90.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 503 3.73% 94.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 247 1.83% 96.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 153 1.14% 97.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 168 1.25% 98.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 61 0.45% 98.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.29% 99.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 116 0.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13632 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13468 # Number of insts commited each cycle system.cpu.commit.committedInsts 5623 # Number of instructions committed system.cpu.commit.committedOps 5623 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -554,101 +554,101 @@ system.cpu.commit.op_class_0::MemWrite 901 16.02% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5623 # Class of committed instruction -system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 24077 # The number of ROB reads -system.cpu.rob.rob_writes 22001 # The number of ROB writes -system.cpu.timesIdled 266 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30306 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 116 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 23467 # The number of ROB reads +system.cpu.rob.rob_writes 21056 # The number of ROB writes +system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 30642 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4986 # Number of Instructions Simulated system.cpu.committedOps 4986 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.986562 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.986562 # CPI: Total CPI of All Threads -system.cpu.ipc 0.111277 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.111277 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10682 # number of integer regfile reads -system.cpu.int_regfile_writes 5223 # number of integer regfile writes +system.cpu.cpi 9.005816 # CPI: Cycles Per Instruction +system.cpu.cpi_total 9.005816 # CPI: Total CPI of All Threads +system.cpu.ipc 0.111039 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.111039 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10418 # number of integer regfile reads +system.cpu.int_regfile_writes 5064 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 167 # number of misc regfile reads +system.cpu.misc_regfile_reads 158 # number of misc regfile reads system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 91.242537 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2427 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 90.670819 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2302 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.212766 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.326241 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 91.242537 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022276 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022276 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 90.670819 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022136 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022136 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 6025 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 6025 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1871 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1871 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5765 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5765 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1746 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1746 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2427 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2427 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2427 # number of overall hits -system.cpu.dcache.overall_hits::total 2427 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2302 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2302 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2302 # number of overall hits +system.cpu.dcache.overall_hits::total 2302 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 165 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 165 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 345 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 345 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 515 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 515 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 515 # number of overall misses -system.cpu.dcache.overall_misses::total 515 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11738500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11738500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24073999 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24073999 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35812499 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35812499 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35812499 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35812499 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2041 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2041 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses +system.cpu.dcache.overall_misses::total 510 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11734000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11734000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24014999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24014999 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35748999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35748999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35748999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35748999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1911 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1911 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2942 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2942 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2942 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2942 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083293 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.083293 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2812 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2812 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2812 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2812 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086342 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.086342 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.382908 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.382908 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.175051 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.175051 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.175051 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.175051 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69050 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 69050 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69779.707246 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69779.707246 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69538.833010 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69538.833010 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69538.833010 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69538.833010 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 615 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.181366 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.181366 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.181366 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.181366 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71115.151515 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71115.151515 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69608.692754 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69608.692754 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70096.076471 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70096.076471 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 70096.076471 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70096.076471 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 587 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.909091 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.700000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 295 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 295 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 369 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 369 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 369 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses @@ -657,82 +657,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7586500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7586500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4094999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4094999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11681499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11681499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11681499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11681499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044586 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044586 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7594500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7594500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4083499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4083499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11677999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11677999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11677999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11677999 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.047619 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.047619 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047927 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.047927 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047927 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.047927 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83368.131868 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83368.131868 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81899.980000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81899.980000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82847.510638 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 82847.510638 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82847.510638 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 82847.510638 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.050142 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.050142 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.050142 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.050142 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83456.043956 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83456.043956 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81669.980000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81669.980000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82822.687943 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82822.687943 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82822.687943 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82822.687943 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 158.208729 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1588 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 333 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.768769 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 156.398029 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1547 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 331 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.673716 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 158.208729 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077250 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077250 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 316 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.154297 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4413 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4413 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1588 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1588 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1588 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1588 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1588 # number of overall hits -system.cpu.icache.overall_hits::total 1588 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 452 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 452 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 452 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 452 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 452 # number of overall misses -system.cpu.icache.overall_misses::total 452 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 33055000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 33055000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 33055000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 33055000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 33055000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 33055000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2040 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2040 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2040 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2040 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2040 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2040 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.221569 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.221569 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.221569 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.221569 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.221569 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.221569 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73130.530973 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 73130.530973 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 73130.530973 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 73130.530973 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 73130.530973 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73130.530973 # average overall miss latency +system.cpu.icache.tags.occ_blocks::cpu.inst 156.398029 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.076366 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.076366 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4289 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4289 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1547 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1547 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1547 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1547 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1547 # number of overall hits +system.cpu.icache.overall_hits::total 1547 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 432 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 432 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 432 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 432 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 432 # number of overall misses +system.cpu.icache.overall_misses::total 432 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32419500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32419500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32419500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32419500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32419500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32419500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1979 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1979 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1979 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1979 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1979 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1979 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.218292 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.218292 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.218292 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.218292 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.218292 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.218292 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75045.138889 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75045.138889 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75045.138889 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75045.138889 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75045.138889 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75045.138889 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -741,54 +741,54 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 119 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 119 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 119 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 119 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 119 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 333 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 333 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 333 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 333 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 333 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 333 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25884000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25884000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25884000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25884000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25884000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25884000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.163235 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.163235 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.163235 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.163235 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163235 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.163235 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77729.729730 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77729.729730 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77729.729730 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 77729.729730 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77729.729730 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 77729.729730 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 101 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 101 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 101 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 101 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 101 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 331 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 331 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 331 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 331 # 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miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990937 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.993671 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990991 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.993644 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990937 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.993671 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80380 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80380 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76827.272727 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76827.272727 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81829.670330 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81829.670330 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76827.272727 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81315.602837 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78170.912951 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76827.272727 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81315.602837 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78170.912951 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80150 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80150 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77358.231707 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77358.231707 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81923.076923 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81923.076923 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77358.231707 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81294.326241 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78541.577825 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77358.231707 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81294.326241 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78541.577825 # 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number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 91 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 330 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 328 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 471 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 330 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 328 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 471 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3519000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3519000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22053000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22053000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6536500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6536500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22053000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10055500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 32108500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22053000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10055500 # 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mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990937 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.993671 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.993644 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990937 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.993671 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66827.272727 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71315.602837 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68170.912951 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70150 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70150 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67358.231707 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67358.231707 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71923.076923 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71923.076923 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67358.231707 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71294.326241 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68541.577825 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67358.231707 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71294.326241 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68541.577825 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 333 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 331 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 91 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 683 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 679 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 965 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 961 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21184 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 491 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 489 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 491 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 489 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 491 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 245500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 489 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 499500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 496500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadResp 421 # Transaction distribution +system.membus.trans_dist::ReadResp 419 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution system.membus.trans_dist::ReadExResp 50 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 421 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 942 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 419 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 938 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 938 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30016 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 471 # Request fanout histogram +system.membus.snoop_fanout::samples 469 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 471 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 469 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 471 # Request fanout histogram -system.membus.reqLayer0.occupancy 582000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 469 # Request fanout histogram +system.membus.reqLayer0.occupancy 580000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2503500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 2493500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini index 4915dc4bb..ff8cb9e3e 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini @@ -230,7 +230,6 @@ hot_lines=false memory_size_bits=48 num_of_sequencers=1 phys_mem=Null -random_seed=1234 randomization=false [system.ruby.clk_domain] diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 8f334ebb7..585054648 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19998000 # Number of ticks simulated -final_tick 19998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19922000 # Number of ticks simulated +final_tick 19922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99740 # Simulator instruction rate (inst/s) -host_op_rate 99716 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 344211505 # Simulator tick rate (ticks/s) -host_mem_usage 290580 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 38523 # Simulator instruction rate (inst/s) +host_op_rate 38518 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 132470471 # Simulator tick rate (ticks/s) +host_mem_usage 286104 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21952 # Nu system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory system.physmem.num_reads::total 444 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1097709771 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 323232323 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1420942094 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1097709771 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1097709771 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1097709771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 323232323 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1420942094 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1101897400 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 324465415 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1426362815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1101897400 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1101897400 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1101897400 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 324465415 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1426362815 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 444 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 19858500 # Total gap between requests +system.physmem.totGap 19782500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 243 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,79 +186,79 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 332.307692 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 194.430832 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 340.544877 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 29 37.18% 37.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 21.79% 58.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7 8.97% 67.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 5.13% 73.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 5.13% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 3.85% 82.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 2.56% 84.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 3.85% 88.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 11.54% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation -system.physmem.totQLat 3950250 # Total ticks spent queuing -system.physmem.totMemAccLat 12275250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 340.210526 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 203.437950 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 338.690117 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 26 34.21% 34.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17 22.37% 56.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8 10.53% 67.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4 5.26% 72.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 5.26% 77.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4 5.26% 82.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 1.32% 84.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 3.95% 88.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 11.84% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation +system.physmem.totQLat 3750750 # Total ticks spent queuing +system.physmem.totMemAccLat 12075750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8896.96 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8447.64 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27646.96 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1420.94 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27197.64 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1426.36 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1420.94 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1426.36 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.10 # Data bus utilization in percentage -system.physmem.busUtilRead 11.10 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.14 # Data bus utilization in percentage +system.physmem.busUtilRead 11.14 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.79 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 357 # Number of row buffer hits during reads +system.physmem.readRowHits 359 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.41 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.86 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 44726.35 # Average gap between requests -system.physmem.pageHitRate 80.41 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 461160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 251625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2519400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 44555.18 # Average gap between requests +system.physmem.pageHitRate 80.86 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 438480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 239250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2511600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 15077640 # Total energy per rank (pJ) -system.physmem_0.averagePower 952.021468 # Core power per rank (mW) +system.physmem_0.actBackEnergy 10783260 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 40500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 15030210 # Total energy per rank (pJ) +system.physmem_0.averagePower 949.326386 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15318750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 68040 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 37125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 288600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 7492365 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2927250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 11830500 # Total energy per rank (pJ) -system.physmem_1.averagePower 747.228802 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 6597250 # Time in different power states +system.physmem_1.actBackEnergy 7628310 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2808000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 11847195 # Total energy per rank (pJ) +system.physmem_1.averagePower 748.283278 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 6322250 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 10517250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 10715250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2331 # Number of BP lookups -system.cpu.branchPred.condPredicted 1883 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 415 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1931 # Number of BTB lookups -system.cpu.branchPred.BTBHits 661 # Number of BTB hits +system.cpu.branchPred.lookups 2359 # Number of BP lookups +system.cpu.branchPred.condPredicted 1936 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 404 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1982 # Number of BTB lookups +system.cpu.branchPred.BTBHits 725 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 34.230968 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 218 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 36.579213 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -279,237 +279,237 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 39997 # number of cpu cycles simulated +system.cpu.numCycles 39845 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7837 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13501 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2331 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 879 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4391 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 863 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 7679 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13188 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2359 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 949 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3750 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 839 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 153 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 147 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1828 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 299 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12836 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.051807 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.461524 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1822 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 291 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12019 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.097263 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.493815 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10473 81.59% 81.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 190 1.48% 83.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 215 1.67% 84.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 153 1.19% 85.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 248 1.93% 87.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 135 1.05% 88.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 253 1.97% 90.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 115 0.90% 91.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1054 8.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9698 80.69% 80.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 176 1.46% 82.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 221 1.84% 83.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 153 1.27% 85.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 238 1.98% 87.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 147 1.22% 88.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 274 2.28% 90.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 116 0.97% 91.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 996 8.29% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12836 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.058279 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.337550 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7233 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3240 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1952 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 129 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 282 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 335 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 150 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11562 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 472 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 282 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7391 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 953 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 624 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1916 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1670 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11195 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 12019 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.059204 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.330983 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7188 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2504 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1924 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 271 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 317 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 149 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 11315 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 469 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 271 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7350 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 927 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 518 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1884 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1069 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 10932 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1610 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9626 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18124 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18098 # Number of integer rename lookups +system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1028 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9574 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17720 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17694 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4628 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4576 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 362 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2015 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1832 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. +system.cpu.memDep0.insertedLoads 1935 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1629 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 53 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10320 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 10141 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9101 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 75 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4591 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqInstsIssued 8840 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 52 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4412 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 3358 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12836 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.709022 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.537942 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12019 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.735502 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.540494 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9696 75.54% 75.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 959 7.47% 83.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 638 4.97% 87.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 461 3.59% 91.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 440 3.43% 95.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 291 2.27% 97.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 236 1.84% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 68 0.53% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 47 0.37% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8914 74.17% 74.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 959 7.98% 82.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 649 5.40% 87.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 465 3.87% 91.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 426 3.54% 94.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 281 2.34% 97.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 228 1.90% 99.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 65 0.54% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 32 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12836 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12019 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11 4.38% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 121 48.21% 52.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 119 47.41% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13 6.47% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 95 47.26% 53.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 93 46.27% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5531 60.77% 60.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 60.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 60.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1910 20.99% 81.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1658 18.22% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5519 62.43% 62.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1819 20.58% 83.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1500 16.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9101 # Type of FU issued -system.cpu.iq.rate 0.227542 # Inst issue rate -system.cpu.iq.fu_busy_cnt 251 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.027579 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31302 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14945 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8267 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8840 # Type of FU issued +system.cpu.iq.rate 0.221860 # Inst issue rate +system.cpu.iq.fu_busy_cnt 201 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.022738 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29890 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14587 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8120 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9318 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9007 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1054 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 974 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 786 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 583 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 282 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 869 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 271 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 843 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 77 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10383 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 18 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2015 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1832 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 10204 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 34 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 1935 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1629 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 66 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 345 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8700 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1776 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 401 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 72 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 254 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 326 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8485 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1707 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 355 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3330 # number of memory reference insts executed -system.cpu.iew.exec_branches 1363 # Number of branches executed -system.cpu.iew.exec_stores 1554 # Number of stores executed -system.cpu.iew.exec_rate 0.217516 # Inst execution rate -system.cpu.iew.wb_sent 8425 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8294 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4459 # num instructions producing a value -system.cpu.iew.wb_consumers 7044 # num instructions consuming a value +system.cpu.iew.exec_refs 3121 # number of memory reference insts executed +system.cpu.iew.exec_branches 1355 # Number of branches executed +system.cpu.iew.exec_stores 1414 # Number of stores executed +system.cpu.iew.exec_rate 0.212950 # Inst execution rate +system.cpu.iew.wb_sent 8249 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8147 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4452 # num instructions producing a value +system.cpu.iew.wb_consumers 7114 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.207366 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.633021 # average fanout of values written-back +system.cpu.iew.wb_rate 0.204467 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.625808 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4593 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4414 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 276 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12125 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.477691 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.335541 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 265 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11324 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.511480 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.378975 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9949 82.05% 82.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 859 7.08% 89.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 524 4.32% 93.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 226 1.86% 95.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 182 1.50% 96.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 108 0.89% 97.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 109 0.90% 98.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 59 0.49% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 109 0.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9160 80.89% 80.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 847 7.48% 88.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 528 4.66% 93.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 216 1.91% 94.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 182 1.61% 96.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 106 0.94% 97.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 122 1.08% 98.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 53 0.47% 99.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 110 0.97% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12125 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11324 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -555,250 +555,250 @@ system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5792 # Class of committed instruction -system.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22401 # The number of ROB reads -system.cpu.rob.rob_writes 21482 # The number of ROB writes -system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27161 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 21420 # The number of ROB reads +system.cpu.rob.rob_writes 21108 # The number of ROB writes +system.cpu.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27826 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.905559 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.905559 # CPI: Total CPI of All Threads -system.cpu.ipc 0.144811 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.144811 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13740 # number of integer regfile reads -system.cpu.int_regfile_writes 7170 # number of integer regfile writes +system.cpu.cpi 6.879316 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.879316 # CPI: Total CPI of All Threads +system.cpu.ipc 0.145363 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.145363 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13451 # number of integer regfile reads +system.cpu.int_regfile_writes 7138 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 63.810933 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2272 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22.274510 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 64.587343 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2213 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 103 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 21.485437 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 63.810933 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.015579 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.015579 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1553 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1553 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 719 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 719 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2272 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2272 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2272 # number of overall hits -system.cpu.dcache.overall_hits::total 2272 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 114 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 114 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 327 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 327 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 441 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 441 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 441 # number of overall misses -system.cpu.dcache.overall_misses::total 441 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8777500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8777500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 32490996 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 32490996 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41268496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41268496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41268496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41268496 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1667 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1667 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 64.587343 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.015768 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.015768 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 103 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.025146 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5395 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5395 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1492 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1492 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 721 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 721 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2213 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2213 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2213 # number of overall hits +system.cpu.dcache.overall_hits::total 2213 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 108 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 108 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 325 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 325 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 433 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 433 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 433 # number of overall misses +system.cpu.dcache.overall_misses::total 433 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7902500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7902500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23909996 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23909996 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31812496 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31812496 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31812496 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31812496 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1600 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1600 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2713 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.068386 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.068386 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.312620 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.312620 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.162551 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.162551 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.162551 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.162551 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76995.614035 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 76995.614035 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99360.844037 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 99360.844037 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 93579.356009 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 93579.356009 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 93579.356009 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 93579.356009 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 627 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2646 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2646 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2646 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2646 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067500 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.067500 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.310707 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.310707 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.163643 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.163643 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.163643 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.163643 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73171.296296 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73171.296296 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73569.218462 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73569.218462 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73469.967667 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73469.967667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73469.967667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73469.967667 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 598 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 104.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 280 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 280 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 52 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 278 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 278 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 330 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 330 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 330 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 330 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4552000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4552000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4551498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4551498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9103498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9103498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9103498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9103498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032993 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032993 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 103 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 103 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 103 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 103 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4528500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4528500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4006498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4006498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8534998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8534998 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8534998 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8534998 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035000 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035000 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.037597 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.037597 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 82763.636364 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 82763.636364 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 96840.382979 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 96840.382979 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89249.980392 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 89249.980392 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89249.980392 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 89249.980392 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038927 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.038927 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038927 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.038927 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80866.071429 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80866.071429 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85244.638298 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85244.638298 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82864.058252 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82864.058252 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82864.058252 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82864.058252 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 169.178952 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 168.966654 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1389 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.979943 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 169.178952 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.082607 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.082607 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 168.966654 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082503 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082503 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4005 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4005 # Number of data accesses +system.cpu.icache.tags.tag_accesses 3993 # Number of tag accesses +system.cpu.icache.tags.data_accesses 3993 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 1389 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1389 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1389 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 1389 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 1389 # number of overall hits system.cpu.icache.overall_hits::total 1389 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 439 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 439 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 439 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 439 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 439 # number of overall misses -system.cpu.icache.overall_misses::total 439 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31700000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31700000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31700000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31700000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31700000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31700000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1828 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1828 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1828 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1828 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1828 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1828 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.240153 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.240153 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.240153 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.240153 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.240153 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.240153 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72209.567198 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72209.567198 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72209.567198 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72209.567198 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72209.567198 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72209.567198 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 485 # number of cycles access was blocked +system.cpu.icache.ReadReq_misses::cpu.inst 433 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 433 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 433 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 433 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 433 # number of overall misses +system.cpu.icache.overall_misses::total 433 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32237500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32237500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32237500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32237500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32237500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32237500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1822 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1822 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1822 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1822 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1822 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1822 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.237651 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.237651 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.237651 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.237651 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.237651 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.237651 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74451.501155 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74451.501155 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74451.501155 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74451.501155 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74451.501155 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74451.501155 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 497 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 97 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 99.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 89 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 89 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 89 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 89 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 89 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 89 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 83 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 83 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 83 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 83 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 83 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26208500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26208500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26208500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26208500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26208500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 26208500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191466 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.191466 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.191466 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74881.428571 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74881.428571 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74881.428571 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74881.428571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74881.428571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74881.428571 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26589500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26589500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26589500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26589500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26589500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26589500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.192097 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.192097 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.192097 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.192097 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75970 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75970 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75970 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75970 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75970 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75970 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 199.713481 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 199.677803 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.017632 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.020151 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.994608 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.718873 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005127 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000968 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006095 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.770664 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.907139 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005120 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000974 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006094 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4060 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4060 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 4068 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4068 # Number of data accesses system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 6 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 6 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 8 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 6 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits -system.cpu.l2cache.overall_hits::total 7 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2 # number of overall hits +system.cpu.l2cache.overall_hits::total 8 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 344 # number of ReadCleanReq misses @@ -811,54 +811,54 @@ system.cpu.l2cache.demand_misses::total 445 # nu system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses system.cpu.l2cache.overall_misses::total 445 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4478000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4478000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25621500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 25621500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4458500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4458500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 25621500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8936500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34558000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 25621500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8936500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34558000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3932500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 26002500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 26002500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4422500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4422500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 26002500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8355000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34357500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 26002500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8355000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34357500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 350 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 350 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 55 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 55 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 56 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 56 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 350 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 452 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 103 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 453 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 350 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 102 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 452 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 103 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 453 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.982857 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.982857 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.981818 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.981818 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.964286 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.964286 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982857 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.990196 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.984513 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.980583 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.982340 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982857 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.984513 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95276.595745 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95276.595745 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74481.104651 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74481.104651 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82564.814815 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82564.814815 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74481.104651 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88480.198020 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77658.426966 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74481.104651 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88480.198020 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77658.426966 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.980583 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.982340 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83670.212766 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83670.212766 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75588.662791 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75588.662791 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81898.148148 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81898.148148 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75588.662791 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82722.772277 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77207.865169 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75588.662791 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82722.772277 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77207.865169 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -879,71 +879,71 @@ system.cpu.l2cache.demand_mshr_misses::total 445 system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4008000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4008000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22191500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22191500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3918500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3918500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22191500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7926500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30118000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22191500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7926500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30118000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3462500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3462500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22572500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22572500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3882500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3882500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22572500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7345000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29917500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22572500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7345000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29917500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.982857 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.981818 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.964286 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.964286 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.984513 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980583 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.982340 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.984513 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85276.595745 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85276.595745 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64510.174419 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64510.174419 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72564.814815 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72564.814815 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64510.174419 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78480.198020 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67680.898876 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64510.174419 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78480.198020 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67680.898876 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980583 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.982340 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73670.212766 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73670.212766 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65617.732558 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65617.732558 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71898.148148 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71898.148148 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65617.732558 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72722.772277 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67230.337079 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65617.732558 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72722.772277 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67230.337079 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 405 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 350 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 56 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 903 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 206 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 905 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28928 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 452 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 453 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 453 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 453 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 523500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 154500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.membus.trans_dist::ReadResp 397 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution @@ -964,9 +964,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 444 # Request fanout histogram -system.membus.reqLayer0.occupancy 550500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 551000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 2342500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 2342750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini index cf52ef870..d45cde2de 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini @@ -227,7 +227,6 @@ hot_lines=false memory_size_bits=48 num_of_sequencers=1 phys_mem=Null -random_seed=1234 randomization=false [system.ruby.clk_domain] diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index ef02c087f..e476df038 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,58 +1,58 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21012000 # Number of ticks simulated -final_tick 21012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20817000 # Number of ticks simulated +final_tick 20817000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49067 # Simulator instruction rate (inst/s) -host_op_rate 88883 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 191585973 # Simulator tick rate (ticks/s) -host_mem_usage 310932 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 31285 # Simulator instruction rate (inst/s) +host_op_rate 56673 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 121026192 # Simulator tick rate (ticks/s) +host_mem_usage 306568 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory -system.physmem.bytes_read::total 26624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory -system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 837616600 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 429468875 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1267085475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 837616600 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 837616600 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 837616600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 429468875 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1267085475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 417 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8896 # Number of bytes read from this memory +system.physmem.bytes_read::total 26560 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 139 # Number of read requests responded to by this memory +system.physmem.num_reads::total 415 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 848537253 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 427343037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1275880290 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 848537253 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 848537253 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 848537253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 427343037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1275880290 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 415 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 415 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26688 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 26560 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26688 # Total read bytes from the system interface side +system.physmem.bytesReadSys 26560 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 34 # Per bank write bursts +system.physmem.perBankRdBursts::0 32 # Per bank write bursts system.physmem.perBankRdBursts::1 1 # Per bank write bursts system.physmem.perBankRdBursts::2 6 # Per bank write bursts system.physmem.perBankRdBursts::3 8 # Per bank write bursts system.physmem.perBankRdBursts::4 50 # Per bank write bursts -system.physmem.perBankRdBursts::5 45 # Per bank write bursts +system.physmem.perBankRdBursts::5 46 # Per bank write bursts system.physmem.perBankRdBursts::6 21 # Per bank write bursts -system.physmem.perBankRdBursts::7 34 # Per bank write bursts -system.physmem.perBankRdBursts::8 22 # Per bank write bursts -system.physmem.perBankRdBursts::9 74 # Per bank write bursts +system.physmem.perBankRdBursts::7 33 # Per bank write bursts +system.physmem.perBankRdBursts::8 25 # Per bank write bursts +system.physmem.perBankRdBursts::9 72 # Per bank write bursts system.physmem.perBankRdBursts::10 63 # Per bank write bursts -system.physmem.perBankRdBursts::11 17 # Per bank write bursts +system.physmem.perBankRdBursts::11 16 # Per bank write bursts system.physmem.perBankRdBursts::12 2 # Per bank write bursts system.physmem.perBankRdBursts::13 17 # Per bank write bursts system.physmem.perBankRdBursts::14 6 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20963500 # Total gap between requests +system.physmem.totGap 20721000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 417 # Read request sizes (log2) +system.physmem.readPktSize::6 415 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 244 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,310 +186,310 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 99 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 239.838384 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 160.844462 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 248.938264 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 34 34.34% 34.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 32 32.32% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15 15.15% 81.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 5 5.05% 86.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 2.02% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4 4.04% 92.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 1.01% 93.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 2.02% 95.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4 4.04% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 99 # Bytes accessed per row activation -system.physmem.totQLat 3956500 # Total ticks spent queuing -system.physmem.totMemAccLat 11775250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9488.01 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 96 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 252 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 164.484740 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 262.126687 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 35 36.46% 36.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 26 27.08% 63.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15 15.62% 79.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6 6.25% 85.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 3.12% 88.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 3.12% 91.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 2.08% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.04% 94.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 5.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 96 # Bytes accessed per row activation +system.physmem.totQLat 4745000 # Total ticks spent queuing +system.physmem.totMemAccLat 12526250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2075000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11433.73 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28238.01 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1270.13 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30183.73 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1275.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1270.13 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1275.88 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.92 # Data bus utilization in percentage -system.physmem.busUtilRead 9.92 # Data bus utilization in percentage for reads +system.physmem.busUtil 9.97 # Data bus utilization in percentage +system.physmem.busUtilRead 9.97 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.61 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 308 # Number of row buffer hits during reads +system.physmem.readRowHits 309 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.86 # Row buffer hit rate for reads +system.physmem.readRowHitRate 74.46 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 50272.18 # Average gap between requests -system.physmem.pageHitRate 73.86 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 189000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 103125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 951600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 49930.12 # Average gap between requests +system.physmem.pageHitRate 74.46 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 959400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 13085760 # Total energy per rank (pJ) -system.physmem_0.averagePower 826.512553 # Core power per rank (mW) +system.physmem_0.totalEnergy 13105245 # Total energy per rank (pJ) +system.physmem_0.averagePower 827.743250 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 430920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 235125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1521000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 423360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 231000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1536600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10315575 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 450750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13970490 # Total energy per rank (pJ) -system.physmem_1.averagePower 882.393179 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 973750 # Time in different power states +system.physmem_1.actBackEnergy 10696905 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 116250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14021235 # Total energy per rank (pJ) +system.physmem_1.averagePower 885.598295 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 271750 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14667250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15224250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 3416 # Number of BP lookups -system.cpu.branchPred.condPredicted 3416 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 534 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2538 # Number of BTB lookups -system.cpu.branchPred.BTBHits 864 # Number of BTB hits +system.cpu.branchPred.lookups 3234 # Number of BP lookups +system.cpu.branchPred.condPredicted 3234 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 514 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2557 # Number of BTB lookups +system.cpu.branchPred.BTBHits 881 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 34.042553 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 247 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 76 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 34.454439 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 280 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 86 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 42025 # number of cpu cycles simulated +system.cpu.numCycles 41635 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 11194 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 15490 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3416 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1111 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9646 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1195 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 11661 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14637 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3234 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1161 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9674 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1159 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1127 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 2165 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 22628 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.226003 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.725670 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.CacheLines 2075 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 22725 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.149527 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.648759 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 18363 81.15% 81.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 236 1.04% 82.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 174 0.77% 82.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 258 1.14% 84.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 208 0.92% 85.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 227 1.00% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 337 1.49% 87.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 205 0.91% 88.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2620 11.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18699 82.28% 82.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 221 0.97% 83.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 146 0.64% 83.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 231 1.02% 84.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 214 0.94% 85.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 258 1.14% 86.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 336 1.48% 88.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 205 0.90% 89.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2415 10.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 22628 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.081285 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.368590 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 10919 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7328 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3329 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 455 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 597 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 25699 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 597 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 11189 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2276 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 782 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3470 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4314 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 24173 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 93 # Number of times rename has blocked due to IQ full +system.cpu.fetch.rateDist::total 22725 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.077675 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.351555 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11462 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7072 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3206 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 406 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 579 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24310 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 579 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 11710 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1815 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1004 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3327 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4290 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 23005 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 71 # Number of times rename has blocked due to IQ full system.cpu.rename.SQFullEvents 4163 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 27542 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 59265 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 33505 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 26169 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 57126 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 32219 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16479 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 29 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1507 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2438 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1611 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 15106 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 28 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 1472 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2371 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1574 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 20 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21416 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17876 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 80 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11694 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16519 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 22628 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.789995 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.748596 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 20445 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 17161 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 65 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10724 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15317 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 22725 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.755160 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.702113 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17504 77.36% 77.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1142 5.05% 82.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 891 3.94% 86.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 637 2.82% 89.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 831 3.67% 92.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 584 2.58% 95.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 600 2.65% 98.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 315 1.39% 99.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 124 0.55% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17737 78.05% 78.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1126 4.95% 83.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 880 3.87% 86.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 631 2.78% 89.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 810 3.56% 93.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 590 2.60% 95.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 568 2.50% 98.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 280 1.23% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 103 0.45% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 22628 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 22725 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 174 77.68% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 31 13.84% 91.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19 8.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 151 71.23% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 43 20.28% 91.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 18 8.49% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14362 80.34% 80.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2121 11.87% 92.29% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1379 7.71% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13707 79.87% 79.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.02% 79.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.04% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2071 12.07% 92.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1369 7.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17876 # Type of FU issued -system.cpu.iq.rate 0.425366 # Inst issue rate -system.cpu.iq.fu_busy_cnt 224 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012531 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 58676 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 33142 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16350 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17161 # Type of FU issued +system.cpu.iq.rate 0.412177 # Inst issue rate +system.cpu.iq.fu_busy_cnt 212 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012354 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 57316 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 31202 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 15767 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18093 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17366 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 235 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 220 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1385 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1318 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 676 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 639 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 597 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1916 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21441 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2438 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1611 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 58 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 565 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 690 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16903 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1966 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 973 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 579 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1449 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 20471 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 46 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2371 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1574 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 34 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 15 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 136 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 524 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 660 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16265 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1913 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 896 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3248 # number of memory reference insts executed -system.cpu.iew.exec_branches 1659 # Number of branches executed -system.cpu.iew.exec_stores 1282 # Number of stores executed -system.cpu.iew.exec_rate 0.402213 # Inst execution rate -system.cpu.iew.wb_sent 16611 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16354 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10992 # num instructions producing a value -system.cpu.iew.wb_consumers 17112 # num instructions consuming a value +system.cpu.iew.exec_refs 3175 # number of memory reference insts executed +system.cpu.iew.exec_branches 1626 # Number of branches executed +system.cpu.iew.exec_stores 1262 # Number of stores executed +system.cpu.iew.exec_rate 0.390657 # Inst execution rate +system.cpu.iew.wb_sent 16001 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 15771 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10637 # num instructions producing a value +system.cpu.iew.wb_consumers 16589 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.389149 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.642356 # average fanout of values written-back +system.cpu.iew.wb_rate 0.378792 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.641208 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 11693 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10723 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 584 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 20667 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.471621 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.370778 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 565 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 20943 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.465406 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.357230 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17422 84.30% 84.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1008 4.88% 89.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 544 2.63% 91.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 740 3.58% 95.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 368 1.78% 97.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 141 0.68% 97.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 113 0.55% 98.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 72 0.35% 98.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 259 1.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 17686 84.45% 84.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 994 4.75% 89.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 561 2.68% 91.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 764 3.65% 95.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 370 1.77% 97.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 129 0.62% 97.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 114 0.54% 98.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70 0.33% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 255 1.22% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 20667 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 20943 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -535,185 +535,185 @@ system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 9747 # Class of committed instruction -system.cpu.commit.bw_lim_events 259 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 41848 # The number of ROB reads -system.cpu.rob.rob_writes 44866 # The number of ROB writes -system.cpu.timesIdled 151 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19397 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 255 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 41158 # The number of ROB reads +system.cpu.rob.rob_writes 42744 # The number of ROB writes +system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18910 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.811338 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.811338 # CPI: Total CPI of All Threads -system.cpu.ipc 0.128019 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.128019 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 21318 # number of integer regfile reads -system.cpu.int_regfile_writes 13103 # number of integer regfile writes +system.cpu.cpi 7.738848 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.738848 # CPI: Total CPI of All Threads +system.cpu.ipc 0.129218 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.129218 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 20871 # number of integer regfile reads +system.cpu.int_regfile_writes 12651 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.cc_regfile_reads 8054 # number of cc regfile reads -system.cpu.cc_regfile_writes 5036 # number of cc regfile writes -system.cpu.misc_regfile_reads 7483 # number of misc regfile reads +system.cpu.cc_regfile_reads 8081 # number of cc regfile reads +system.cpu.cc_regfile_writes 4880 # number of cc regfile writes +system.cpu.misc_regfile_reads 7277 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.324603 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.950355 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 81.971685 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2383 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 139 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.143885 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.324603 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020099 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020099 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 81.971685 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020013 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020013 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 139 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5349 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5349 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1533 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1533 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 857 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 857 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2390 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2390 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2390 # number of overall hits -system.cpu.dcache.overall_hits::total 2390 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 136 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 136 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 78 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 78 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 214 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 214 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 214 # number of overall misses -system.cpu.dcache.overall_misses::total 214 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10515500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10515500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6241000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6241000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16756500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16756500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16756500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16756500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1669 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1669 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_task_id_percent::1024 0.033936 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5305 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5305 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1525 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1525 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2383 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2383 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2383 # number of overall hits +system.cpu.dcache.overall_hits::total 2383 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 123 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 123 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 77 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 77 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 200 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 200 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 200 # number of overall misses +system.cpu.dcache.overall_misses::total 200 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9653500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9653500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6433000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6433000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16086500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16086500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16086500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16086500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1648 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1648 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2604 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2604 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2604 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2604 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081486 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.081486 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083422 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.083422 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.082181 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.082181 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.082181 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.082181 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77319.852941 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 77319.852941 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80012.820513 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80012.820513 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 78301.401869 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 78301.401869 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 78301.401869 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 78301.401869 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 241 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2583 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2583 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2583 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2583 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074636 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.074636 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.077429 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.077429 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.077429 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.077429 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78483.739837 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 78483.739837 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83545.454545 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 83545.454545 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80432.500000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80432.500000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80432.500000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80432.500000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 269 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 67.250000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 72 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 72 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 72 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 72 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 78 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 78 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5436500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5436500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6163000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6163000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11599500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11599500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11599500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11599500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038346 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038346 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054531 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.054531 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054531 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.054531 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84945.312500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84945.312500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79012.820513 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79012.820513 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81686.619718 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 81686.619718 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81686.619718 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 81686.619718 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 61 # 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number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11642500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11642500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11642500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11642500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.037621 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.037621 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.053813 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.053813 # 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Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.135254 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4427 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4427 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1706 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1706 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1706 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1706 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1706 # number of overall hits +system.cpu.icache.overall_hits::total 1706 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 369 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 369 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 369 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 369 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10043500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29175000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19131500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10043500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29175000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996377 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996390 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996390 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996390 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997596 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996390 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67512.820513 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67512.820513 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67061.818182 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67061.818182 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73625 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73625 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67061.818182 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70267.605634 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68153.477218 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67061.818182 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70267.605634 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68153.477218 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997596 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71045.454545 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71045.454545 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69317.028986 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69317.028986 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73758.064516 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73758.064516 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69317.028986 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72255.395683 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70301.204819 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69317.028986 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72255.395683 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70301.204819 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 78 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 78 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 276 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 64 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 552 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 283 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 835 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 277 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 62 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 554 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 278 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 832 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 416 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 418 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 416 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 416 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 208000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 414000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 415500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 208500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.membus.trans_dist::ReadResp 338 # Transaction distribution -system.membus.trans_dist::ReadExReq 78 # Transaction distribution -system.membus.trans_dist::ReadExResp 78 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 339 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 77 # Transaction distribution +system.membus.trans_dist::ReadExResp 77 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 338 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 830 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26560 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26560 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26560 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 417 # Request fanout histogram +system.membus.snoop_fanout::samples 415 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 415 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 417 # Request fanout histogram -system.membus.reqLayer0.occupancy 505000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 415 # Request fanout histogram +system.membus.reqLayer0.occupancy 500000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 2222250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2216750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 10.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini index c1f4aa57f..56411f6d5 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini @@ -261,7 +261,6 @@ hot_lines=false memory_size_bits=48 num_of_sequencers=1 phys_mem=Null -random_seed=1234 randomization=false [system.ruby.clk_domain] |